 So, today we will look at metal gate transistors, you know you may recall that the very abbreviation MOSFET M here really stands for metal, because that is how we sort of started building FETs right in the very beginning. The FETs that we used to build had metal gates, but the metal gate was due to certain constraints we were not able to really do what we call in the recent past polysilicon gate transistor and hence we were building metal gate transistors. So, when we were building these metal gate field effect transistor way back in you know 60s and you know may be 70s, the problem with the metal gate was the following right the metal gate transistor was it was not a self aligned transistor. So, what I mean by the self alignment is that if you recall the MOSFET flow that we have discussed in one of our earlier lectures, if you recall I had mentioned that in polysilicon gate transistors that we have today ok. We have this gate stack which includes the S I O 2 or of course, high k now and polysilicon and here you do ion implantation right. You convert you know polysilicon into N plus or P plus that is how you make it a very highly doped polysilicon material and that is done along with the source drain implant correct. You see polysilicon was deposited as intrinsic polysilicon, but subsequently if it were to be N MOS region I implant arsenic and the arsenic will sort of come in here right. This would have been a P well region for a N channel transistor and arsenic would have also come in here and in this region arsenic would have come in and stuck in the gate region right that is how I would have converted that gate into a N plus doped region. Now, notice here that when you are done with all these junctions you see the junction is sort of self aligned to the edge of the gate and of course, subsequently there is going to be some annealing process and because of the annealing these dopants will diffuse in and also diffuse little bit inside laterally, but they are more or less aligned to the edge of the gate. You do not want to have an unaligned or you know a transistor where gate does not overlap source and drain you know it is as long as gate is right edge on with source and drain, but of course, you do not want to have a transistor structure which looks something like this you know that would be suicidal for transistor right. If let us say if this is your gate and this is your S I O 2 and only N plus region easier N plus region easier this is all P region when you are trying to do this you somehow ended up with this region which we sometimes call under lap as opposed to having something like this where source and drain are actually going beyond the gate edge this is this region is what we call overlap. If you have under lap where you know gate does not cover some regions of the transistor as a result of that you would not be able to create an inversion channel here your transistor will not be conducting it would not be a good transistor. So, this is certainly a no no correct you should never have this you should either have an edge on which is good because you know right now here you have junctions and immediately this region can be inverted by the gate because the gate field is influencing your channel region right this is ideal, but it is if you have little bit of overlap, but not well if you have too much of overlap is there an issue well there is an issue and that is to do with the parasitic capacitance issue this issue here is with respect to parasitic resistance you know this is a region where you will not be able to turn on the transistor huge resistance for the transistor whereas, here what would happen is that if you were to look at this transistor we call this overlap capacitance you see here is J and here is D and here is S you have these overlap undesired capacitance called C G D and C G S and sometimes these are also called as Miller capacitances that is essentially a capacitance between your gate and the drain especially typically sources at ground potential let us say for a transistor, but especially when you want to use a transistor as an amplifier your gate to drain parasitic capacitance should not be too high that will in turn impact the bandwidth of the transistor in other words you see a schematic representation of transistor in a circuit is like this G D and S let us say I am building an amplifier this parasitic capacitance from input to the output of the transistor that is not good. So, ideally a 0 overlap is best you can get, but it may be very difficult to get. So, you are ok if you cannot get 0 at least you can get something you know non-zero positive, but certainly not negative. What happened with the metal gate the reason the very reason why we moved from metal gate transistors to poly silicon gate transistors was that the metal gate transistor invariably resulted in huge overlap here. So, if you want to compare your metal gate versus metal gate that we used to do in the past early days of the transistor technology your metal gate transistor invariably looked something like this you had this gate let us say metal gate and a huge overlap, but still a working transistor there is a parasitic capacitance all right and on the other hand if it is a poly gate transistor you get almost an ideal transistor structure just may be a little bit of overlap here because of the self aligned nature. So, what is not self aligned here you see if you are doing the metal gate transistor first of all it turns out you cannot do source then source and drain implant after patterning your gate you see let us say that I am putting aluminum here let us recall our transistor process flow in a poly gate transistor I first make the gate stack right this oxide and poly silicon gate is made and implantation of arsenic after implantation invariably I will have to anneal at high temperature typically 1000 degree centigrade. If you were to do the same thing here what would happen at 1000 degrees aluminum will melt aluminum cannot withstand that high temperature even at 550 it will start melting. So, most of the metals that you know you would want to use as gate materials they would melt at temperatures which are used to anneal the source drain implantation and hence in a metal gate transistor you do what is called source drain first and gate last process as opposed to here in a poly silicon gate transistor you do gate first hence you have defined the gate stack you see and hence I do not need anything else to define my source drain because it is going to be self aligned right source and drain last. In this process if you are doing source drain first and gate last you have already defined the junctions correct and then you grow the gate oxide the process flow here will look something like this junctions are defined gate oxide is grown gate electrode is deposited which is metal which is everywhere and now all the gates are shorted right I need a photolithography step to pattern the gate and that photolithography step should be aligned with already defined source drain junction. So, I am depending on a photolithography step to do the alignment. So, what I do in order to avoid an under lab situation because when you are trying to align something which is already printed there could be an offset you see in order to avoid an offset you build in an extra margin even if there is an offset you still get a working transistor which does not look like this right. So, as a result of that you do the patterning when you do the patterning you give an extra margin you actually pattern a wider a longer gate than that is required just to cover the source drain area. So, that even if this gate shifts a little bit to the left you know you still have an overlap here even if it shift to the right you still have an overlap here. So, by giving an intentional margin I am going to get a working transistor because that is the first thing right and then you worry about all parasitics. So, the metal gate transistors always have the large overlap of gate over source and drain and hence that is not a desirable thing. This was one problem the other problem with the metal gate transistor you know is also that you have a one metal to all transistors it is the same metal for n channel same metal for p channel let us say then the work function of the metal is fixed you see whereas, in case of a poly silicon gate transistor your work function for n MOS transistor is closer to the conduction band because it is n plus and your work function for p MOS transistor is closer to the valence band. Now, why is it that important it is very important because in order to get symmetric V t's for n and p recall what is the V t equation your V t is V f b plus 2 phi b plus q d by C ox let us say V f b ignoring all charges in the oxide this is essentially phi m s which is work function difference right which is phi m s plus 2 phi b plus q d by C ox for poly silicon gate technology what happens for n MOS I have n plus gate n plus gate meaning on the gate the Fermi level is very close to the conduction band edge. So, what is phi m s as a result of that phi m s is negative in n channel transistor remember that you have a vacuum level and this is a conduction band level on the gate. So, this is 4.05 electron volt which is electron affinity and your substrate is a p type. So, where Fermi level is below the mid gap. So, work function on the p side is much larger. So, phi m minus phi s gives a negative quantity and in fact phi m minus phi s is half the band gap plus phi b where phi b is the bulk potential in the words you see on the gate side this is E c of n plus and on the substrate side this is the mid gap and this is phi b this phi b is dependent on doping concentration correct bulk potential. So, phi m s is really this which is half the band gap which is let us say 0.56 and phi b. So, it is minus of 0.56 plus phi b that comes here 2 phi b is a positive quantity 2 phi b is a positive quantity, but little less than this because you see phi b can never be 0.56 right phi b is always less than 0.56. So, this minus this will be a small negative quantity and over powering that you will have another positive quantity and eventually you end up with 0.2, 0.3 whatever threshold voltage depending on your doping concentration and oxide thickness right. This is for n channel now p channel very interestingly let us say if you do the right doping and all let us say your V t of n is 0.3 volt let us say now you see what happens to p channel V t V t p is again the same equation except phi m s is going to be positive because now phi m for p channel transistor is p plus which is 4.05 plus full band gap because e V is here correct the Fermi level will be here for the p MOS and what is the work function here it is the phi b let me draw this so that there is no confusion right. So, here this is e V valence band right this is p plus Fermi level is on the gate close to the valence band right that is why we call it p plus on the other hand substrate is n type this is mid gap and this is your Fermi level and this is phi b and this is half the band gap 0.56 let us say so phi m s phi m is larger than phi s. So, phi m s is a positive quantity correct and phi m s is positive 0.56 plus phi b now what happens here the band bending is minus I mean this is a negative quantity now it is a p channel transistor bands are bending opposite. So, minus time to phi b is plus this still give you a small positive quantity and again you have this q d which is a opposite charge and that will also be a negative quantity and all that put together will give a negative v t which is almost same as this positive v t for n channel that is excellent right. So, in other words your v t for p will become equal to minus 0.3 volt this happens simply because we had dual work function gate this would never happen if you have identical gate for n channel and p channel let us suppose that the gates for n channel well you know n plus for p channel they were also n plus then you will get a huge negative number for v t right because this you will not have a positive quantity this will also be a negative quantity because this is sitting here at n plus and similarly you know you will not be able to get an appropriate v t matching for n and p channel transistor. So, this is a problem right and hence the dual gate technology was excellent right and as soon as we figured out how to you know do this poly silicon and dope poly silicon heavily n plus p plus we migrated to the dual gate poly silicon technology because you get this and as well as self-aligned transistors correct two very important matrix. So, why are we talking about metal gate today ok if this is why in the first place we moved from you know metal gate technology to poly silicon gate technology right well there is a reason for that the reason also becomes very clear to you if you look at what we have been doing so far right. If you look at the transistor you see this gate length this is my gate right and this gate length has come down from in microns tens of microns today we are talking of less than 50 nanometer. Let us for a minute look at this direction not the gate length direction but the width direction in other words if you have to look at the top view of this transistor ok and let us say this is the width ok and this is where you will have a gate contact and this will be gate and you will have source here drain here and so on and so forth. This is shrinking right this is shrinking to 30 nanometers and so on and so forth from where it was micron ok. But you see the widths in any circuit are dependent on how much current you want from the transistor right if you want more current you scale the width you increase the width right. So, width is not necessary in your control you make the length as small as possible. So, the transistor becomes fast transistor because the distance between source and drain is very very small. Now if you for a minute look at in this direction what will happen the signal from a previous stage will come on to this contact and this signal should propagate along this direction correct. Now let us look at that and how does it look you know that essentially looks like you know a very something like this right ok. So, the signal is coming at one edge let us say this is where the signal has come and the signal has to propagate along this and you see this is not a superconductor right I mean this is after all you know some material polysilicon ok you have doped it very heavily but nonetheless you still have some resistivity you know its resistivity could be a few ohm per micrometer ohm per square kind of resistivity ok. So, what it means is that as we start shrinking this what is that that is channel length right as we are starting to shrink it that is one aspect what is happening simultaneously the frequencies are increasing right we are no longer talking of megahertz we are talking of gigahertz right. So, at this large frequency this will start acting as a transmission line ok because it has a finite resistance the resistance is not you know 0 as I said and there is a capacitance obviously because that is a gate insulator capacitance. So, this is essentially an R C delay and this R C delay is not negligible for two reasons as I mentioned again this R is increasing why is R increasing if we were to look at your resistance you have decrease the channel length correct earlier when the channel length was long there was what is the area of cross section for the current flow here that is the thickness correct and the length that is the area that is available this length is decreasing. So, area of cross section is decreasing because of that and not only that we have also scaled the gate stack we have not been using very thick gates we have also scaled that. So, even thickness has decreased right. So, as a result of that this resistance has really gone up like this ok poly silicon gate and so much so that because of this large resistance the R C times have become comparable to reciprocal of the frequency of the signal of interest. I am using this microprocessor at you know few tens of gigahertz reciprocal of that is you know it depends on that will dictate how much R C delay you can tolerate that is less than nanoseconds ok. So, this is a serious problem right. So, the problem is the gate resistance gate resistance has become a serious problem right. When we say gate resistance gate resistance as I mentioned for the signal to propagate you know from one end of the gate to the other end of the gate what it means is that when the signal comes here the transistor will slowly start turning on from this edge. So, current front moves from this edge and eventually when the signal reaches this you will have whole transistor conducting which is not good right. Your current is much lower than what should have been for certain duration of R C delay of this gate right. And hence we want to replace this poly silicon gate what is the solution you convert this material into something which has much lower resistivity and what is that lower resistivity metal ok. This is one thing, but there was another equally important problem that came about you know that was to do with the following right. Remember poly silicon when it is deposited it is intrinsic and it had to be converted into either N plus or P plus by doping. If you do not dope it it will not have a low resistivity. So, that resulted in one more problem which I will again briefly discuss and that is called poly silicon depletion effect right. So, what it essentially means is that you have this poly silicon let us say it is 100 nanometer thick you need to implant and diffuse correct. Look at the fine balance that we have to strike here how do you dope the poly silicon completely you see poly silicon which is intrinsic to begin with I will call it I for intrinsic should be converted into N plus for this to convert to N plus this whole region from this point all the way to this point should have very heavy arsenic doping ok. How do you do that one of the two ways right either you implant very deep if you cannot dip implant very deep you diffuse for you have implanted only this point let me do a huge dose implant diffuse it down. So, that it will come down but the problem is the following right it is the same implant that is going to the gate and the source and drain. So, if you want to dope the whole thing your source junction could be at least as deep as this because it is the exactly same process it is not going to be a different process that is the beauty right it is a self-aligned transistor it is the same process that is defining it N plus and N plus source drain. But deep source drains are not good because they would in turn result in bad short channel effect dibble and so on and so forth that we have talked about this coupling volume has to decrease correct that is what we have discussed quite extensively that is one thing the other thing that happened was sometimes when you actually did this somehow let us say you did this this oxide that you had was ultra thin right one nanometer is what we were talking about SiO2 when you have such a thin oxide you know these dopants can also diffuse through the oxide especially so with boron because boron is so light as opposed to arsenic. In fact in literature you will see this problem called boron penetration what it means is that the boron can easily penetrate through this ultra thin one nanometer it is as if it is non existent there. So, now you do not want the boron to come boron will be in a P channel transistor in N channel transistor we can talk of arsenic penetration but that is not big problem. But in a P channel transistor it is complement of this as you know right. So, then we are talking of this is made P plus this is made P plus and your gate is also made P plus this boron will come here that will make this P plus that is not good you do not want boron to come in the channel correct you have actually N well here you do not want that N to convert into a P type you see. So, invariably you have to end up with the situation where the poly silicon very close to gate oxide will not be as heavily doped. In other words if I were to look at the doping profile let me call it you know this is what I call x axis right this is what I have been calling y axis. Let me call it you know x equal to 0 here for just the sake of this plot and this is T poly which indicates poly silicon thickness. So, then what you probably will end up is something like this x equal to 0 here x equal to T poly ideally correct this is where your gate oxide starts remember that ideally you want this whole thing to be doped a very heavy let us say 10 to the 21 per centimeter cube arsenic or boron, but I cannot do that right for one thing the junctions could be deep for the other thing you can end up with having this penetration. So, invariably what you will probably end up is something like this because you are afraid to push it to far. So, the region very close to your gate oxide will be depleted and this is what we mean by poly silicon depletion there is not as many dopants what is the impact of this the impact is two fold one obviously the gate resistance will increase even more. Because the plot that I had shown you earlier of R versus L is assuming that whole poly silicon is doped right let us say that corresponds to this case, but now if you have this case you may have something like this because this region is not doped you see and hence resistivity will increase in that region that is one, but there is even more serious problem with this and that is if you look at the vertical direction what happens now in vertical direction is this is your gate you see this poly silicon we use to only consider the gate oxide capacitance here and the silicon capacitance assuming that the whole thing is like a conductor, but now there is huge depletion here which means there will be effectively another series capacitance. So, this is what is called poly silicon depletion capacitance. So, whenever a new capacitance comes in series the total capacitance goes down as a put to resistances in series. So, what means it means is that your gate coupling to the channel degrades your gate cannot effectively coupled to the channel because now it is C ox in series with C depletion that will certainly be much lower than C ox. So, your transistor will have lower current. So, these were real problems you know we were stuck with these problems and that is why we had to change it to a metal gate technology. So, just to recap that you know the resistance which increase the R C delay was not desirable and poly depletion effect was another undesirable effect. Both this forced us to change poly silicon to metal. But now the challenge for now is how do you make a metal gate transistor which is self aligned because we have been doing self aligned transistor we do not want to go back to our old transistor which has a huge overlap because now we are talking of huge frequencies of operation. So, I must get self aligned transistor that is the challenge. So, I want to get metal gate self aligned transistor. So, there are you know possibly two ways you know one can get there is what is called a disposable gate process and there is another called it is called abbreviated as FUSI fully silicided gate or of course, this is more complicated process and today we have in manufacturing all the 65 45 nanometer technology are actually using disposable gate process. We will see what is disposable gate process in a minute then the first question to ask is do you want to do a single metal gate or double metal gate. Now this is an important consideration remember I told you dual poly silicon gate technology was excellent because you got N plus kind of a work function on NMOS on the gate side and P plus kind of a work function for PMOS on the gate side correct which was dual work function. So, if I need to have a matching VTs I must have two metal gates right. So, we call them you know NMOS you know NMOS work function metals and PMOS work function metals NMOS work function metals if so you see metals have different work functions depending on which metals you are looking at for example, if you look at aluminum zirconium they all have low work function aluminum is 4.1 zirconium is about 4.2 that is very close to N plus because N plus is 4.05 that is the electron affinity for silicon conduction band right N plus that is where the formula values there are others such as platinum and you know few others you know gold also has large work function and few other metals are there like they are all 5.2, 5.3, 5.1 which is what is there in P plus because P plus is 4.05 electron affinity plus 1 band gap which is 1.1 correct. So, the P plus work function should be like 5.2 EV. So, there are different kinds of metals that are available. There was also a proposal for a while is that look if I have to use two metals as opposed to poly silicon poly silicon was a intrinsic poly silicon which was deposited and then converted to N plus during N channel implant and P plus during P channel implant. But here I need to have two different deposition process and two different lithography process you know I need to first deposit aluminum and etch it off in PMOS regions and retain only in NMOS regions and then block NMOS region deposit some other metal and you know again pattern it more complicated right which required two deposition two etching two lithography to pattern the gate as opposed to a single deposition and single etching process and there was a proposal called you know mid gap metal gate. There are some metals you know which have work function neither 4.1 nor like 5.2 somewhere in between like you know 4.6 4.7 EV. So, the idea was that you know you have a single metal gate whose work function is at the middle of the band gap right. So, you compromise both N channel and P channel transistors identically. So, you would probably still be able to get matching VT, but VT will certainly be compromised. So, that was not really a usable solution. So, what we have been doing today is double gate double metal gate using disposable gate process technique and double metal gate one with NMOS and one with PMOS work function. As you know the work function is very important because VT will not be obtained properly otherwise. So, now how do we do this now? So, let us look at disposable gate process. So, what we do here is that we just go through the usual process of making a polysilicon gate transistor. That is you have N well or P well whatever it is you actually do a gate oxide to polysilicon deposition although I want to get metal gate right. But for the time being I do polysilicon and pattern polysilicon wherever I want to have the gates on N channel region as well as P channel regions ok. Then do the source drain implant when I do the source drain implant polysilicon is sitting here correct. So, it will still give me self-aligned transistor correct. So, in other words I will get let us say N plus N plus and this also becomes N plus let us say. Now, what I will do the same similar thing will be done for P plus also ok. Now, after this what I do is that I deposit an insulator on top everywhere ok. Let us say you deposit extra insulator and then etch it off. Let us say I deposit SiO 2 and polish this SiO 2 such that I will end up with all the SiO 2 in this region and this region ok and in this region now this gate is exposed. So, what will happen here then is that oops ok I guess ok right. So, this is SiO 2 here, SiO 2 here correct. Similarly in P channel regions also. Now, what I do I have SiO 2 here and I have silicon here. I can use write H chemistry and I can get rid of this polysilicon gate remove it completely ok. So, when you remove it you will end up with a cavity there correct ok. Remember source and range are already formed and they are formed self-aligned to this edge correct and they are formed self-aligned to this edge because this polysilicon was a place holder. It was just sitting there to define my self-aligned transistor. Now, the polysilicon's job is done because I do not want to use it eventually in my circuit because it will have huge resistance. So, etch it off. Etch it off selectively by creating a structure like this. Now, fill this region with whatever metal that you want in end channel region let us say aluminum right. Of course, you know you do a lithography you make sure that it does not go to P region all your end regions will get this. And similarly you do another set of process meaning only the deposition opening and cavity formation is already done it is done at the same time anyway right. You know you have another cavity here for P channel transistor this is a P channel transistor P plus P plus and there is a cavity here this is SiO 2 and this is also SiO 2 this is also SiO 2. And you fill this cavity with a different metal this will be a P MOS work function metal and this will be an N MOS work function metal. More complex process that is true because you know you had to etch add the polysilicon you have to etch it away fill it differently in end region fill it well you deposit everywhere, but you know retain it here pattern lithography and retain it here and similarly here and so on and so forth right. So, I will just take back what I said you do not do lithography here you just do chemical mechanical polishing right I mean you do not necessarily do lithography, but nonetheless you know you can you know do this process such that metal is there and source drain was before metal. So, you do not have to anneal it at high temperature correct. So, there is no danger of metal melting, but because I had that dummy polysilicon I got self aligned transistor and hence the name disposable gate process. There was a gate polysilicon gate and that was only a place holder and that was disposed of subsequently that is how I got this metal gate here metal gate here perfectly self aligned transistor right. This is one way of doing that and this is what is done very extensively today. Well there are lot of issues you know I sort of filled in that region so easily with you know the marker pen here, but really you know you will have to make sure that there is a huge cavity here the metal should deposit conformally everywhere and you do not want to end up with the cavity here where metal is not deposited properly ok. There is lot of process optimization that goes in, but you have to do that because there is no other way you can build transistors today. If you are talking of transistors less than 45 nanometer you take for granted that the process is certainly more complex, but that is worth it only when you do all that complicated process you will be able to you know get a very well behaved transistor ok. So what is the implication of this you know we started off with the main problem that we had right that is my R versus length you know it looked like this you see if I go to metal gate it would look like this. So this is the metal gate whereas this is the polysilicon gate especially where you are shrinking length very significantly metal gate will outperform polysilicon gate very significantly. What is the second option second option is called FUSI or fully silicited gate fine. So what do we do here as the name suggests the idea is to exploit silicitation process to create somewhat like a metal gate transistor. What is the silicitation process if you remember I had explained this to you earlier in one of my lectures and that is I told you that your transistor looks like this there will be a spacer here there will be a spacer here and eventually the source and ground contacts will come here you will have a shallow extension here and then a deep source drain here correct. I told you that this regions we convert them into a combination of metal and silicon or silicide you deposit a metal anneal it at high temperature and there is a reaction between metal and silicon and you end up with the silicide correct. So here this region and this region this all gets converted to silicide ok. So the idea of fully silicited technology is that you let us say I am doing a titanium silicide you convert this whole region into titanium silicide. So strictly speaking we should not call it metal gate it is more like a silicide gate ok right. In other words it is a combination of titanium and silicon which is either n plus dot or p plus dot ok very interestingly when you convert a silicide the work function of the silicide is governed by what is your initial work function of that silicon right whether you had a n plus silicon or p plus silicon. So in all n channel regions you would have n plus gates correct and that becomes an n plus silicide and in p channel region you have a p plus silicide because you had a boron heavy doping right here you had a arsenic heavy doping ok. So as a result of that you have been able to get somewhat like a metal gate ok. It is not quite metal gate because this is not comparable to having an ideal metal gate right. In other words if you were to interpose another curve what you will probably see is that you know you may get something like this for a fuzzy fully silicide technology. Fully silicide technology is certainly better than polysilicon gate certainly it is not as good as a metal gate. What is the advantage here? The advantage is simply that the process is not very complex you see. I do not have to do a disposing of the gate etching of the gate and then doing another deposition for n like gate and another deposition for p like gate and so on and so forth right. So the advantage of a fuzzy process right simple process flow but there is a disadvantage also right as you know double metal gate that we are talking about. And also the whole thing has to be silicided you know if you cannot silicide if part of that silicon is left with then that is also not a good thing right because you know that region will be a high resistivity region right. So your total resistance will also increase because of that region right. So as a result of that you know fully silicide gate is a theoretical possibility. You will see that lot of literature exists wherein people have demonstrated it is doable and you get reasonable threshold voltage matching for n and p because it works as a dual metal function work function gate. However because it does not improve the R C delay as much as double metal gate technology you know it is not really a practically implementable technology. So that is what we essentially do with the respect to metal gate technology. In fact today all technology today the state of the art technology today as I said you know anything less than 65 nanometer CMOS technology is a metal gate and high k. As we discussed in the last lectures we also have a high k gate dielectric right. High k gate dielectric and metal gates sort of go hand in hand you know they happen simultaneously in terms of replacing the silicon oxide as a gate insulating material and also in terms of replacing poly silicon gate as your gate electrode. The best thing about metal gate is that there is absolutely no poly silicon depletion issue apart from the resistance issue that we talked about R C delay and all that right. So the poly depletion effect is completely eliminated right you get the best gate coupling right. So you know which means the best gate coupling to channel and hence invariably you know you will see that your high k with metal gate as opposed to poly silicon gate will certainly have much better on current of a transistor as opposed to a poly silicon gate transistor fine. So well let me then summarize the discussions that we had today you know MOSFET as the name suggest is you know a metal gate FET that is how we started building a FET. But when we started building an FET with metal gate we had to resolve to a gate last process and source drain first process because otherwise metal would melt during the source drain annealing process right. And hence the gate had to be defined using photolithography process and you ended up with huge overlap gate overlapping source and drain and parasitic capacitances. And that is how we sort of quickly migrated to poly silicon gate technology although we continue to call them as MOSFETs its M here was a misnomer really ok. For last three four decades M was misnomer because it was not really metal gate it was a poly silicon gate technology highly doped poly silicon. The greatest advantage then was most importantly you had self aligned transistor and you also had this you know N plus and P plus kind of a dual work functions for your N channel and P channel transistor which resulted in very well matched threshold voltages for N MOS and P MOS. But as we started shrinking the gate length you know at about 65 nanometer the resistivity of the gate started really influencing the RC delay for the propagation through the gate electrode and that is when we were forced to replace the poly silicon gate with the metal gate. But then the challenge was really to get the metal gate using a self aligned transistor flow right. And that is how we sort of resorted to having a disposable gate process wherein we continued the you know best practices of poly silicon gate technology wherein poly silicon was just a place holder right to define that self aligned transistor subsequently you H out the poly silicon and you define different metal gates for N channel and P channel regions and hence you get the self aligned transistor as well as the very well matched VT is because I am using a double metal gate process ok. So, we will stop here and we will continue in the next class.