 National Chinggong University in Taiwan. In this talk, I'm going to talk about Empower, Embedded Computing with VESC, Rescribe, and Free Autos. In fact, this is the course project in my last semester. And so I'm going to go through how to use this combination. So here is the agenda of this talk. So basically I will go through the motivation of this project and why I choose VESC, Rescribe, and Free Autos as my hardware and software choice of this project. And then we will talk about briefly explain how to port Free Autos to VESC, Rescribe. And the last, I was talking about some difficulty I encountered during the development. So the first topic is the motivation of this project. It's the fact that we are going to enhance the computational power of our devices. It's like the cell phone you use, we try to add more CPU cores or add more RAM, add more GPU to enhance the execution efficiency or the speed. But the fact is that the system must note that you have add the cores or some rinse or the GPU to fully enhance the computational power that your hardware has. And let this come into the fact that we should fully understand the computer system we have so we can enhance or fully utilize the system we use. But what if the limitation is due to the hardware we have? For example, I have Rescribe here and this Rescribe is for 4 cores and 4GB RAN. And due to this limitation, it is impossible to do something like to run 8 tasks simultaneously on this hardware. So it is the limitation of this hardware. So to advance the, enhance the computational power, we have no choice but to customize our hardware. Yes, we have to customize our hardware. So that comes to the best Rescribe. It is the RV32 INC CPU implementation. To this, AI comes to integer and N comes to multiplication, division and modular instruction. And C comes to a compact instruction. And the whole implementation is written with spinal HDL, which is hardware description libraries. And with these libraries, we can design our hardware with several components. So we can combine those components and build our own computer system. And for this project, it also integrates a variator, which is a hardware simulation tool. So we can simulate the CPU we designed and we can use extra tools like Open, OCD and JTAG to connect to our hardware and build the software system of this. And it is, it is interesting that we use spinal HDL to write this CPU implementation. So it is like we have a more high level view instead of some very low or other hardware description language. And with the spinal HDL, we can generate more FPGA friendly code and change the design of our CPU more easily. And let's introduce to the actual hardware design of this project. It is called BE SOC, which is the best respite implementation. We all know that we cannot run our system only on the CPU. So this SOC is trying to provide some basic components like UART timer and some like SD-RAN chip-RAN and also they have VGA control components. And the most important thing is that the author give us some basic sample codes for utilize this hardware. So we will not have to search the documents all the day, try to look into the source code of the implementation. We can first look into the example they provide. So let's go to the software part. After we have the hardware and we should also decide to some operating system so we can develop some other application on top of the system. So I pick up two candidates of our operating system. The first is Linux kernel. But unfortunately, Linux kernel require more components which the Vestgres 5 doesn't support, which is an A extension. The A denotes atomic instruction which is used to influence the synchronization tools. And the second reason is the virtual memory. We all know that Linux kernel try to isolate process and threads with the address space. But it occurs more time on porting into a new hardware with virtual memory mapping. So to focusing on the porting or to make the system run on the hardware we write. So I choose the second one, which is free articles. Free articles is a real time operating system maintained by AWS. This system use physical memory directly. Which means that we can use MAIO to directly configure the peripheral configuration. Because this RGOS is like a minimum operating system. So they try to drop some fancy things like ELF loaders and other components to make this operating system thing and simple. So it is relatively easy for new hardware to porting. So after choosing the hardware and software that's going to try to combine these two components. So it is simple to do this for porting the free articles onto the pre-SOC. The first part is the boot loader. Since we have our own hardware. So it means that the system may not load its image by itself. So we need to have a boot loader to load the free articles image into the range of the SOC. Which is the responsibility of the boot loader. But in this project I try not to focus on the development of boot loader. So we use the JTAG pin of this implementation. This JTAG pin can connect with the open OCD. And we can use some general tools like GDB to debug our systems. And the second thing is the address map. Which is related to the linker script. And this is relatively simple because the example we shown before. So this will not take too much time to revise. And the third part is the peripheral setup for operating system to verify the system is working. At least we should have some text on my show sound text on my screen. So we can know that our system is alive or not dead. So we should set up the UART parts for the bug grades and the pins and so on. And another way is to use the GPIOP to make some LED to blink. And that is another way strategy to verify it. And for the fourth part it is an interesting config in free articles. It is like the dot config in Linux kernel. It can try to enable or disable some features of the free articles by modifying this header file. And I have captured some contents in this header file. You can see that we try to enable the results with this code from 72 to 74. And we are trying to use some timers which is enabled by the code in 81. And with this config file we can try to enable and disable the code without actually looking into the source code. So that's talking about some difficulty during the development. For the first part which is the exceptions. Exception is like something you are trying to mess up the operating system. So the hardware is trying to protect the operating system from doing the wrong thing. So like some classical exception is like H4. And other exception may be illegal instruction. So in this case the free articles. Because free articles relies on the instruction equal which is environment code to trigger the context switch. But the free SOC will not be built with the support of equal instruction by default. So every time when the free articles trying to use equal to do task switching and the system will stream like no the instruction is not in my instruction list. So the system will not do not know how to perform the task with these instructions. So the solution for this problem is to go back to the last five source file and turn on the eco generation during the CPU generation. And this is also the benefit of using the spinal HDL with this high level view of the CPU. Instead of the very low codes we can solve this problem like simple and easily. And the second problem is the lack of machine timer. The machine timer is the it's like the main timer in the risk five spec. It is it is defined in the expectation that machine timer is to trigger the system ticks. And without the system tick the system will not know the time is. What time is in. Something like that. So, but the problem is that the spec says the machine timer must be implements as a peripheral and. Let's record the black diagram we shown before. There is no that such machine timer on the black diagram. So, the three SLC would cannot use the instruction. Provide by machine timer and cannot generate the system tick with machine timer. But we have some basic timer. We can say we can see the timer is here and we don't have the machine timer. So, my strategy is to make use of this timer in the peripheral block. And the next problem is the tick frequency. As we know, the CPU has the frequency. And this frequency can be used to decide the the tick frequency of the operating system. In the in our simulation, it is unlikely to decide the frequency because we are you, we are running the simulator so the frequency of the simulator is something like unstable. So, during this problem, we cannot set up the proper CPU frequency in the free articles configurations. And for the project. Right now I just try to. Pre define some values to make the tick. It works, but it is not that precise. So. Feel free to try this best fast response by three SLC and three articles on your own Linux computer. I use the. In the last example. And the code I write can be found on key hub with this link. And the instruction will be to copy the this directory and the. Specific extension into the free articles directory. So you can use a good new make to build the extent executable and then you can. Start up the simulation and connect with your GDP so you can test this free articles on your own computer. So this is the demonstration of this project. We can see I try to connect the simulator. On the left and the GDP on the right. And. We pass the operating system image into the simulator. And use the GDP config. GDP command. Continue to run the code. And we can see the transmitter and the receiver. Is doing. The task switching. Although this demonstration is only includes. Message passing and some basic. Multi-tasking. Technology or skills. But I think it is. The first step and important step. To fully customize the. Computer system we have. And that is the sound reference I found in the during the below. So I think. It is the end of this talk. Thank you.