 the question from there, if you could please ask the question. Sir, from Kakinata, go ahead. Second order differential equation using op-amps is accurate, which gives full explanation about all these things. How to solve second order differential equation using op-amps? This is our question, sir. Yeah, a differential equation essentially has various terms which are second order, first order, constants and so on. The equation says that the sum of these quantities must be equal to some forcing function. So, we know that how to produce an output such that the two inputs are equal. So, finally, if you give two inputs to an op-amp, its output will change in such a way that the two inputs must be equal. That is equivalent to the equal to sign in the differential equation. Now, all the terms on the left hand side and the right hand side of the differential equation can be implemented using the kind of circuits that I had. So, to give you an example, suppose you have a very simple equation saying that this second order differential is equal to some positive or negative. So, you will take the second order difference, create the second order differential equation and put it equal to a constant and put the feedback such that the two must be equal. Now, the voltage at which it settles, you will notice that in order to use these differential equations, you will have to use c and r. Suppose the value is positive, in that case you will get a voltage which is exponentially varying because the solution to a second order differential equation with a positive value is indeed exponential. If the value, if the constant is negative, then you will find that you will get an oscillatory circuit. So, the output voltage will then be a solution to this differential equation. Indeed, any old equation differential or otherwise can be solved. There is a left hand side, each term can be implemented using op-amp. There is a right hand side and each term can again be implemented using op-amp and now we want to force them to be equal and therefore, you use a feedback which will ensure that the two are equal and the voltages which satisfy this equality is indeed the solution to this. So, by constructing a circuit where each term is represented by an op-amp circuit and by forcing the two outputs to be equal using feedback, we can construct a differential equation or any equations. Sir, thank you. SVNIT Sura, we are connected to you, we can see you there. Could you please go ahead with your question please. Hello sir, my question is related to the morning session, FET characteristic, wherein it has been said that at the pinch of condition, the effective channel width at the drain and almost touches. Now, if it is so, then there is no path for the carrier to flow from source to drain, so the current has to be zero, but rather it is seen that it is almost remain constant. So, I just want to get the idea that how it is possible, over. Yeah, let me answer this question. In fact, we had a slide on this. Let us take two situations and this is your P plus which is the gate and of course, it is symmetric, so there is a gate at the bottom as well. So, let us say you are at V D sat and the depletion region looks something like this and here is the pinch of condition. Now, at this point and if you make V D greater than V D sat, what happens is this pinch of region extends just a little bit, not too much compared to the channel length. So, let us plot, let us sketch that as well. So, what has happened is the most of this channel is not really, there is no real difference between these two situations except at the drain end. Now, although it looks like these two regions have touched and it looks like there are no carriers there. If you expand this region, you will see that there is actually the electron density is not exactly zero, but there is a small opening there and then there are electrons going from this channel all the way to the drain. Now, this is something that you, it is difficult to understand analytically. So, what people do is they have numerical solution, numerical packages to solve these problems and then you can get a more clear picture, but this region which we call the pinch of region is not completely devoid of carriers. Otherwise of course, as you said the current will actually drop to zero, that does not happen. So, what happens is there is a very high field region here. So, any additional voltage like V d minus V d sat will in fact, just drop across this region and most of this channel will remain the same as before and therefore, the current really does not change. So, the key is that this although we say that it is a pinch of region, the number of carriers there is not exactly zero and then there is a small, there is a small region where you have carriers and which are going from the channel region to the drain at high speed, because the field is high. I would like to add just a little bit of point. This is of course, an excellent explanation that has been given, but we should ask a more fundamental question from ourselves. What is a depletion region? What causes the depletion region to be there? It is because of the p n junction effect, the field have removed the carriers from that region. Now, this depletion region is caused by the vertical junction. What it means is that the average concentration of carriers in this region is exceedingly small. However, in this little tip here, carriers are coming in here, in this tip carriers are coming from the left. What it means is that it is depleted because of the vertical field. That means no carriers are left from the original semiconductor, but there are carriers arriving here. Because the field is very high, they will be swept across very quickly indeed. Therefore, the net concentration of remaining electrons in this region continues to be very small. That means it is still depleted. However, the current is kept constant because the velocity is very high. Remember, the current is given by the product of the number of carriers and their velocity. The number of carriers continues to be extremely small, which is characteristic of depletion region. Notice even in the regular depletion region, this value is not 0, it is extremely small. However, the field is so high, the voltage drops across such a small region that the velocity is extremely high. That is what makes the current continuous. It is continuous at the value at which it was just before arriving at this tip. That value is the id set. Therefore, the current remains constant at id set rather than dropping to 0. In fact, this is exactly the same thing which happens in MOSFET devices as well. Thank you, sir. It is over. Go ahead with your question. Sir, what is the virtual ground concept? Can you explain? I think we did it briefly, but let us look at it again. Here is the op-amp. Suppose the voltage at this end is some v. Call it v1. And you have some negative feedback here in the general case. Let us not talk it, talk the other case I had worked out in full detail. But let us say some general case in which the output has a connection to this inverting input. Now, we know that no current can flow into this op-amp. Therefore, whatever current is coming in here must be carried out and this output itself must adjust itself to carry this current out. Now, should there be any voltage difference? So, let us take a numerical example which will make it quite clear. Let us say this is 1.0 volt. Suppose this was 1.01 volt. Now, the gain of this is very high. Rather than infinite, let us take some 1,000 or 10,000 which is typical of op-amp that you will get. This means that the output starts going towards minus 10 volts from 0 and that because it is connected through some negative feedback. As the output starts going towards large negative values, it pulls this voltage down because these two points are connected through some network. And it will pull it down till this point reaches exactly 1.0 volts. Once it reaches 1.0 volts, the output is 0 and there is no need to pull it down any further. Similarly, was it 0.99, then the output will go positive, pulling it up and it will pull it up till it is exactly equal to the input. So, in short what it says is that if there is a negative feedback, the output adjust itself in a direction such that it brings the voltage at this point equal to the voltage at this point. This is called a virtual short. These two points are not connected directly to each other. They are not shorted. However, the output is guaranteed to behave in such a way that it brings the potential at this point exactly to the potential at this point. That is called a virtual short. If you help for op-amp, you can able to amplify tc signals also, but is it does not affect the biasing circuits? In the initial stage of differential amplifier, we will have dual input, balanced output and dual input and unbalanced output. Yeah, it is clear that we can amplify dc inputs, but the point is because of the virtual short, these two inputs are at equal value and differential amplifiers are indeed designed to be tolerant of changing the bias potential as long as the two potentials are equal. So, if there is no differential voltage, but the common mode voltage varies all over the place. The circuits inside the op-amp are so designed that they are tolerant to this. The details of this we will probably do in one of the lectures where we see how differential amplifiers are made, but just because you have raised this question, consider this configuration which is quite often used where there is a current source in common of the two emitters. Now, as long as these two voltages are equal, it does not matter what their absolute values are. If they are equal, then both will both branches that means this branch and this branch will carry equal current. So, therefore, their biases will continue to be i by 2 where i is the current drawn by this irrespective of the actual voltage here. So, circuits like this are used inside the op-amp even though the absolute bias voltages change, but the amplification of the op-amp is unaffected. Therefore, an op-amp has to be carefully designed so that it is tolerant of changes in the common mode voltage. The feedback ensures that the differential voltage is kept to a very small value because of the virtual shock. So, the bias does change, but the circuit configuration is such that it is tolerant of changes in voltages, their current bias normally and the amount of current remains the same irrespective of the common mode voltage as does this. To a logarithmic amplifier, how to analyze the sort of circuit? We have not done non-linear amplifiers. A later lecture will take care of these, but the way of analysis is no different. You just have to assume, if there is negative feedback, you just have to assume virtual shock and equalize the input current to the output current. These will now be non-linear functions, but when you equate the current, then you will get the expression of output voltage versus input voltage. Gallium arsenide with silicon or germanium, what kind of bonding it is difficult to understand? So, these are called amphoteric dopants and if silicon replaces gallium, then it has a valency which is higher and now it will become a donor. On the other hand, if it replaces arsenic, then it will become acceptor. So, silicon has the capability of being both a donor and an acceptor in gallium arsenide. Such dopants are called amphoteric dopants and the actual technological process favors depending on the temperature and other conditions. It favors the replacement of either gallium only or arsenic only with silicon and the result is that silicon will show up either as a donor in the previous case or as an acceptor in the latter. We are connected to Jaipur college. Could you please ask your question? Sir, my question is from semiconductor physics. Sir, according to Hall, the holes are not vacant spaces but individual particles which have mass and the positive charge. So, when a p-type specimen is there and a hole travels around the circuit and it reaches an ohmic contact, how does it enter a metal because metals don't have holes? So, that is my question. The answer is simple. You have not understood Hall properly. You can explain the situation by an equivalent one where the hole is considered as an actual particle. It is not an actual particle. In the beginning of this class, if you had seen, I had explained what the situation is. Let me just hark back to that just a little bit. Essentially, you have a whole network of silicon atoms. Now, suppose you have made, you have created an electron hole pair. That means, one electron from here, let's say, has gone away as a free electron. This leaves this region electron deficient and therefore, there is a net positive charge at this location. No physical particle, the nucleus has a certain amount of charge and the net negative charge in the electron cloud is less by one electron charge. If I now apply a field, then these electron clouds will all be deflected. They will be attracted towards the positive plate and repelled away from the negative plate. As a result, if this was the original, if this one was the original electron deficient atom, electron cloud will be deflected this way and as a result, this will now become the electron deficient atom whereas, this will have a full quota of electron. Now, this is a bit of an oversimplification. I am talking of a transfer only between nearest neighbors, but the wave function in the valence band is actually spread over many, many atomic sites. That means, an electron does not belong to one silicon atom, but it belongs over a very wide region. Its wave function is spread out. As a result, what moves is the deficiency of electrons in position because it moves it is not an ionic charge, it is a hole and the hole itself is not a particle. It is the absence of an electron from a particular position. You have this interesting question of what happens when it reaches a metallic contact. Essentially, what happens is that this silicon in touch with this metallic contact is now electron deficient. There are lots of electrons in this metal and an electron, the potential is such that an electron from the metal now drops into this. That means, the electron deficiency is now over. There is no atom which is electron deficient. The electron deficient atom was here and the deficiency moved in this direction because the electrons moved in this direction and now this was the electron deficient atom. There are zillions of electrons in this metal and you have applied a potential which means that this is negative and you had positive here. That is how the positive charge has moved in this direction. Now, an electron will come from the metal and fall into this electron deficient location. Therefore, it will appear as if the hole has moved away out of the semiconductor and into the metal. That is how the conduction will take place at the quantum. Sir, my question is again that a vacant space, that is a hole, can be replaced by two kind of electrons. One is a mobile electron that is free in the specimen and another is a bound electron that is coming from a nearby bond. That means, it will have to break the bond and replace the hole. So, now these two kinds of electrons, the quantum physics cannot be applied. Similarly, to a free electron and to a bound electron. A bound electron has a different application on the quantum physics. So, that is my question. Again, the same way I am just… Indeed, the two cases are widely different. In one case and let me go back to the picture that I had drawn earlier. This was the situation and let us say this silicon atom is electron deficient. If a free electron happens to wander here and is captured here, the free electron has vanished and the electron deficiency has vanished. This is called recombination. This is the reaction we started with. That is to say an electron and a hole have recombined. The electron is not there anymore. The hole is not there anymore. I notice from your question that you keep on talking of vacant spaces. It is not a question of vacant space. It is a question of charge deficiency, negative charge deficiency. It is not a special, it is not a mechanical factor, but the charge density factor. Now, this atom is no more electron deficient and this free electron is not available anymore. It has got bound. This is a case of recombination. The electron and the hole have recombined and because this is a more stable configuration, it will give off some energy which will appear as added vibration in this lattice. The other case is that the electron was not free, but bound and that is the case that I was talking of earlier. This is an electron bound to this atom and it has moved from here to here. As a result, this position is no more electron deficient and this position is now electron deficient. That is therefore, an electron movement from here to here is equivalent to a hole movement from here to here. That means, when a bound electron moves, that is exactly equivalent to a hole movement. Whereas, when a free electron moves into a hole, that is a recombination. So, always we treat them differently. We are not saying the two are different. Two are the same. Thank you very much. Do I see Srinagar, could you please ask your question? Yes, good afternoon. My question is to Professor Patil. I would like to know about, in case you are increasing your drain source voltage excessively, means it is greater than the V D set. If you once again look into the pictures you mentioned, where you represent picture A, B, C and D for different characteristics, for different behavior of JFET at different drain source voltage for constant gate voltage. So, if we exceed the pinch of voltage and we move further with drain source voltage high, would you expect eventually it would break down or would it continue to have a constant current over to user? The question is what happens when you keep increasing the drain voltage? Doesn't the junction break down? We had actually discussed this a little bit in the morning. Let me repeat this. So, let us say your gate voltage applied is, let us say minus 2 volts. And for minus 2 volts, your characteristics, the IV curve looks like this. I D versus V D and let us say eventually the drain junction, drain voltage becomes so high that this, let us say the breakdown voltage is 12 volts. So, when the drain voltage is 10 volts, this 10 minus, 10 minus minus 2 will give you 12 volts and then this junction will break down. So, at this point what happens to the IV characteristics is the current, the drain current, very large current will flow because the junction is not insulating anymore. I am going off. So, what happens is the drain current starts rising and in fact, it rises without, almost without any control and that is the manifestation of the breakdown process. And of course, this area is to be avoided. We do not really operate the device in this region and if you continue to increase the drain voltage, the current will eventually become so high that the device will just burn, melt away or something. Okay, over to you. I am related to this. If we go on changing the gate voltage, would you expect that this breakdown voltage would also change with gate voltage? Okay. All right. The question is what happens if I change the gate voltage? Let us say instead of minus 2 volts, what happens if I change the gate voltage? So, instead of minus 2 volts, let us say I have minus 3 volts, right? So, in that case, what will happen is the I V curve will now be another one. Bike is... Can you hear? Can you hear now? Okay. So, if I change the gate voltage, let us say from minus 2 volts to minus 3 volts, I am now on another I V curve, I D V D curve and now this same breakdown voltage will reach at V D equal to not 10 volts, but 9 volts. So, when I reach 9 volts, now it will break down. We will see these little differences in the breakdown with respect to gate voltage. Okay. My question is related to the placement of pin 741 operational amplifier wherein we use pin number 2 and 3 for the input and pin 6 for the output. My question is that is there any reasoning in picking up 2, 3 for input and 6 for output? I mean why not 1, 2 for input and 3 for output? Over to you, sir. The reasons for this are rather mild. Indeed, there are op-amps in which other pins are used. You are talking only of one op-amp. So, there are, for example, quad op-amp packages in which very different pins are used for input and output. So, there is nothing holy about pins being 2 and 3 for input and 6 for the output. However, there are a few considerations which apply to the choice of input and output pins. And some of these, if they can be met, are indeed observed. We would like a balance as far as possible between the inverting and non-inverting input that keeps essentially the symmetry and therefore, the common mode rejection ratio high at all frequencies. As a result, you would like a, as far as possible, a symmetric placement of the circuit with respect to the positive as well as the negative input. Therefore, in the early designs, it was put on the middle somewhere on pin 2 and 3 because on the die itself, the connection is not linear. As you see in dual inline packages, the pads are actually surrounding all around a chip and these are towards the center of one of the arms of the chip. The output is generally kept far from the input to avoid any inadvertent feedback so that it does not start oscillating at high frequencies due to some parasitic feedback. So, the general consideration is that the two inputs must be symmetrically laid out and the output should be reasonably well separated from the two inputs. Now, whether it is exactly fulfilled by pin number 2 and 3 and 6 or any other pin, that will vary and indeed if you look at some more modern integrated circuit, then you will notice that it does not always follow these pinouts. However, because 741 was the first widely used op-amp, many of the circuit use that layout and if you wanted to make a replacement op-amp in which you can just pull out the 741 and put in the new IC and now have better performance in frequencies, flow rate or what have you. Therefore, it was important to keep the same pin out and therefore, a large number of modern ICs have also mimicked that same layout, but that is not a fundamental consideration. The fundamental consideration is that the inverting and non-inverting inputs must be symmetrically placed and the output should be well separated from this. Thank you sir. Another question is related to the operation amplifier. We understand that this slew rate is an inherent property. Would you suggest something that this slew rate can be increased while putting some external circuits around this like we do in transistor biasing. So, is there any alert net for that? Over to you sir. Actually this question requires discussing the circuit on the inside of the op-amp which we have not yet done. However, just to give you a brief answer since you have raised it, the easy way to increase the slew rate is to increase the bias current of the differential stage because the output is then charged by this bias current. The maximum current that you can get out of a differential amplifier is the tail current since the total current is limited by the tail current. So, by increasing the tail current you can increase the slew rate. However, this will increase the power dissipation as well. So, there is a tradeoff between slew rate and power. There are some dynamic slew rate compensation schemes and so on, but I think really that we have not yet reached a level in our discussion where we can meaningfully describe those circuit tricks. There are circuit tricks which allow you to temporarily increase the slew rate when it is required. Thank you sir. Thank you very much.