 Namaste, welcome to the session design of mod counter using IC7490. At the end of this session students will be able to analyze and design mod counters using IC7490. In this session we are going to see design of different mod counters using IC7490. Modulus counters. Now take a pause here and recall what is modulus and mod n counter. So modulus means the number of states through which the counter passes before returning to the starting state is called as the modulus of the counter. And mod n counter means it is a counter circuit which passes through n number of states before returning to the starting state. Now let us see IC7490 which is a asynchronous counter. IC7490 is a ripple decayed counter and also known as a mod n counter. IC7490 is also known as BCD counter because it counts from 0 to 9. It has mod 2 counter and mod 5 counter. So let us see the block diagram of IC7490. So in this block diagram you can see there are two counters mod 2 counter and mod 5 counter. So in mod 2 counter only one flip-flop is used. So when one flip-flop is used there are two states. So that is why it is called as a mod 2 counter. Whereas in mod 5 counters three flip-flops are used. So whenever three flip-flops are used it is giving you eight different states. But here it is internally connected in a such a way that it will go through only five states. So input A is a clock to the mod 2 counter and input B is a clock to the mod 5 counter. Output of first flip-flop here is given as a QA whereas output of mod 5 counter are QB, QC, QD. Whereas QD is the MSB bit and QA is the LSB bit. And there are few more inputs as reset input R1 and R2 are representing reset input. So whenever reset input is activated as these are active high then output will be 0000. So it will be get reset to the 0 and S1 and S2 are set inputs. So whenever these inputs are given as active high so output will be get set to the terminal value. That is the last value 1001 as it is a decayed counter. Now let us see the pin diagram of IC 7490. So here you can see it is a 14 pin IC. So at the pin number 14 we have a clock A which is clock input to the first flip-flop. And clock B at the pin number 1 which is clock input to the mod 5 counter. Then at the pin number 2 and 3 we have reset inputs. Then pin number 4 is not connected. Pin number 5 is VCC whereas 6 and 7 are set inputs. At the other side of IC 7490 we have ground at pin number 10. At pin number 13 not connected that is NC. And the output of this counter is at pin number 12, 11, 9 and 8. So here you can see QA, QD, QB, QC. But we are connecting at the output from MSB first QD, QC, QB, QA. So let us design a mod 10 counter using IC 7490. So as we know that there are two mod counters in IC 7490, mod 2 counter and mod 5 counter. So individually the first is working as a mod 2 counter and the second one is working as a mod 5 counter. So when these two are connected together there will be multiplication 2 into 5 and that will give us 10. So it will work as a mod 10 counter. So here we have to make the connection in such a way that it will start counting from 0000 and will stop at 1001. So for that we are giving basic clock input to the clock A and as it is a asynchronous counter. So output of first flip-flop is given as a clock to the second flip-flop that is input B. So here you can see QA output is given as a clock input to the B which is a clock input to the mod 5 counter. Then we are taking out the output as QA, QB, QC, QD. Then we are connecting set and reset to the ground. So you can see here both set S0 and S1 and R0 and R1 where it may be referred as S1, S2 and R1, R2. So all are connected to the ground for the normal operation because these are active high when these are given as one that may be reset or a set. So we are connected here all these set and reset input to the ground so that it will work as a mod 10 counter. Now let us see the timing diagram for mod 10 counter. So in the waveform you can see the output from each flip-flop as QA, QB, QC, QD and then there is a clear input that is nothing but reset input. So here you can see the output of first flip-flop is always changing its value at the negative H clock. And then QB changing its value when there is a negative transition of the QA and similarly QC and QD are changing their values with respect to the previous clock. So in this way you can see here first output as from MSB QD to the LSB QA 0 0 0 0 which is representing decimal 0. And next at the next clock the output is 0 0 0 1 so it is representing decimal 1. So similarly when 9 comes so it will be 1 0 0 1 representing 9. So 0 to 9 when count is completed then at the next clock it will be get resetted or it will be automatically resetting because the second counter is a mod 5 counter. Now let us design mod 6 counter using IC7 for 9 0. So again we are taking the help of this block diagram so 2 into 5 10 but we want our counter to work as a mod 6. So what you have to do is we have to connect both mod counter as we have connected earlier. So basic clock is given to the clock A and then output of first flip flop is given as a input to the next mod counter that is input B. Then the both sets are connected to the ground because we do not want to set the counter but we want to reset the counter when 6 counting are over. So whenever output comes as 6 0 1 1 0 so from MSBQD 0 1 1 0 which means the counter is at a 6th position. So already 0 to 5 are counted and when the 6 count comes it should reset itself. So that is why we have connected here output of QB and QC because those are high to the AND gate and output of AND gate is connected to the reset R0, R1 commonly. So in this way the IC7 for 9 0 works as a mod 6 counter. Now let us see the waveform here. So in this waveform you can see again we are taking the same waveform. But now as it is a mod 6 counter when the counter counts from 0 to 5 so it will reset whenever 6th clock comes. So at this point you can see output is 0 0 0 0 which is representing decimal 0. Similarly when it is at the 5th clock then you can see the output as 0 1 0 1 so it is a 5. And when 6 clock comes it is get resetted and the counter again starts counting from the 0. So in this way mod 6 counter works. Now let us design mod 7 counter using 7 4 9 0. So again with the help of this long diagram so mod 7 means it should count from 0 to 6 means 7 counts. When 7th count comes as 0 1 1 1 from QD to QA it is 8th count. So you can see here output of QA and QB is given to the first AND gate then output of QC and this AND gate is connected to one more AND gate. And that is then connected to the reset input. So whenever 8th count comes it will automatically get resetted and our counter will start counting from the 0. So in the waveform you can see so after counting 7 counts means from 0 to 6 when 7th comes then it is get resetted automatically. So here you can see output as 0 1 1 0 that is 6 and when 7th comes it will automatically reset and again it will start counting from the 0. So in this way you can design mod counters using IC 7 4 9 0. These are references. Thank you.