 Hello friends, welcome you all to the session 19 of on this development. So, in thiswe would cover the interrupt processing in detail ok. So, we are not talking about exception handling, we are talking about IRQ or FIQ ok and what are the different schemes that can be supported ok and then we will touch upontwo kinds of handlers ok. I will tell you a sample exceptinterf handlers implementation and then we will go through that in detail how it is implemented ok. So, the scope of this discussion is understand about all the different screen schemes available ok and then we will see two implementations of them ok and I leave the remaining thing as an exercise ok. They are available in the reference book that I have mentioned ARM systems developers guide ok. They have given in that book there are some sample code implemented for the remaininginterf handlers I urge you to go through them ok at your leisure, but thisgoing to this lecture andunderstanding these two implementations will help you knowhow it is implemented to understand clearly and then you will be able to follow with the remaining schemes ok, follow up with the remaining schemes very good. So, let us see ISR is interrupt service routine there are two levels normally in handling the interrupt ok. I will explain you withexample know how not typically some implementations are done in the realized scenario ok. So, that you understand what do I mean by first level and second level. So, the interrupt handlers are divided into two parts ok one is the first level. So, after the interrupt has been organized and after it has been found which device is interrupting then there are two levels of handling them ok based on the device and based on the data that comes into the processor . So, the first handler is called hard and fast interrupt handlers why do I why do we say you know in a typical real time scenarios we say hard real time and soft real time ok. Hard real time is very it is very time sensitive andit needs to be processed within a fixed time duration and any latency in handling them may be troublesome ok. You may have a failure or catastrophic failure if the time time line is not met. So, that is what is called hard real time and soft real time is something which can be done you know even if it is delayed there is nonot much of catastrophic changes, but may be a degradation in the performance is expected. So, the same line the handling of interrupts also divided into hard and soft are fast and slow ok. So, the this is the first level needs to be handled within some time gap ok otherwise the data will be lost and if it is a very critical data then it may be a catastrophic failure from the system perspective. But soft means the second level handling could be delayed and it can be done once this is done on time this can be little bit delayed no issues ok. So, we it is not very time critical. So, basically the interrupt handling is divided based on these two functions and then we put most critical things to be done into the first level handling and then the remaining processing involved which can accept some kind of a delay could be put in the interrupt service routine which is a second level ok. So, the naming is different where so, what you should remember is the first level handling is the most critical thing which needs to be done with a limited time gap and then the second level could be a longer a processing and it can take sufficiency a long time. The sufficiency in the sense it is not it is not in terms of seconds it must be some milliseconds or less than that, but you can differ this you know allow time allotted for this particular processing you can differ it little bit and it is not very time critical. So, let me give you an example ok. So, this is the processor ok at assume there is some interrupt controller ok I call it as IC to simplify. So, we are going to be looking at only IRQ input ok. Similar thing is done in FIQ only thing is normally the FIQ is directly connected to the processor ok not through any controller ok. I will tell you what is the function of interrupt controller we will maybe when I am talking about peripherals where I will touch upon this it will be to you know tell you what it exactly this coprocessor or you know a module dash it is a another hardware module which can be connected to. So, a IRQ input is here ok. So, some of the peripherals it could be I can call it as some peripheral 1 then peripheral 2 it you know multiple peripherals can be connected to the controller and then it will generate one interrupt to the processor which could be connected to IRQ ok. So, as you are aware processor has only 2 inputs to accept interrupts from external entity. So, it is IRQ and FIQ and you are all very clear now that FIQ has a higher priority than IRQ. So, processor has a its own priority among these exceptions and interrupts. So, there are other data prefetch and thenyou know prefetch data you know instructionexception and then data abort and then there is a reset pin right reset. There are so many interrupts you know the reset could be a direct input and thisaborts are handled internally that means, it can be generated based on the instruction being executed ok during the you know when it is accessing the memory right. So, it has got its own priority among these aborts and then the interrupts that are coming in. So, as you are aware reset is the most highest priority and then data abort comes then fast interrupt FIQ then IRQ ok that is the order in which the interrupts are processed. So, first is reset just to recap on that reset ok and then we have data abort this is during data access to memory if exception is coming then that will be given higher priority and then the rest is this will be FIQ ok FIQ interrupt will be handled and then IRQ. So, this is the relative priority that processor alert node gives interrupt and you can decide a selectively to enable some interrupt or mask some interrupts and then react you know give different priority to them and then you can even configure it for level trigger or h trigger those are so many things which are there toconfigure this interrupt controller how it has to process the input coming from different processor. So, individually you know you may wonder what are the different peripherals that are possible there are UART there and then USB controller could be there UART is a serial controller ok and thenthere can be a different a disk can be connected to this you know interrupt there are so many ways you cantimers can be connected. So, the semi peripherals can be connected to this and then they will the interrupt controller will prioritize them and then they will generate an interrupt to this. Now, when the IRQ handling happens ok IRQ. So, when this interrupt happens the processor may not know which device has interrupted if it is coming through a controller. So, what will you do the first level it will try to find out which you know first level it will try to find out which device is interrupting and then it will read that device ok some some devices there suppose some data is waiting it will read it from there and then keep it in a memory the processor will keep it in the memory and then defer the processing to the second level ok. So, first level is only to do the minimum work acquired as soon as the interrupt is generated you know whenever it is being processed ok IRQ is generated and then it is this is the ARM processor. So, whenever it is generated and ARM processor when it gets a time because there is no other FIQ or data abort or reset pending then it will come and you knowservice this interrupt and then on the first level handling it will do what is minimum required to satisfy the device that means, ok if it has to be read from the device and then put into the memory it will do ok. So, or it has to you know inform that to say that ok you continue with the processing of next thing and then it will defer the processing for the processing to the second level of interrupt handling. Now, why are we are we dividing this into two because after this first level is done we can re-enable this particular device which has generated originally in fact, in fact even we can re-enable the IRQ itself. So, that the next device which is in the priority may be coming and then it may be interrupted and then IRQ will be generated and then you will have that service routine coming up. So, basically what happens is after the first level handling we want to re-enable the interrupt. So, while handling the second level handling in a interrupt we want to keep this first level open. So, that the processor is not blocked until this longer processing is completed ok that is the purpose of this. So, that typical for a real time scenario this is very much required. Now, you may wonder you know can you can I have an example for this ok. Let me tell you some example ok this is very becoming very difficult to rub it ok ok. Let us see one example suppose you have a serial port ok this is your asynchronous universal asynchronous. So, basically this is a serial port controller a PC ok you are connecting to RS232 assume ok a serial protocol which you may be aware. So, there are two inputs ok one ok from your perspective PXT is descending into PC and then from this RXT is input to the UR ok. So, this is connected to the interrupt controller and that intern is connected to the ARM processor ok through IRQ input. Now, you are sitting in a PC and then you are trying to give a command ok. Let us give a scenario ok you are here ok you are giving a command ok may be read memory ok. There is a debugger or some other your own monitor running here in the ARM processor which can read from memory and then contents can be sent to the PC and then you can display you know you can see that contents in the memory in the PC ok. Now, basically what are you trying to do? We are running some program in the ARM processor and then we are connected a UR which is a serial port controller which you can configure it for some particular board rate and then particular bit configuration parent parity 8 bit or 9 bit ok and then parity is even or odd parity you know and then board rate you decide and then the same configuration you do it on the PC side. So, these two talk to each other through a serial port. Now, we are sending a command an ASCII command ok may be it may say that you know read mem ok read memthen you will say that from 200 ok high fun 300 ok assume that it is an hexadecimal and then carriage data. So, what happens when this command is given the monitor which is running will wait for this complete command to be received from the PC. So, it will reach it will read one character at a time or then D then mem and then you know it will understand the complete command is given the carriage written is given then it will assume that ok complete command is given then this processing takes place here to look at the values what is given and then whether it is a valid command or not then if it is a valid command perform the job. May be it will initiate another task or something to do the job it all that may not be handled in the handler interrupt handler, but there are two things to be done one is first read these characters as soon as they are received by this you are ok it will be in a receive buffer one character may be there then know it will interrupt the controller and then interrupt controller based on the priority of other devices connected to it it may interrupt the processor with the IRQ input. Then the processor comes and then executes the first level of handling that is where is it ok this is the first level of interrupt handling. So, it will read these characters first and put it in a buffer command buffer or something inside ok and then it will check whether it is a carriage written or not may be you know A or D ok this if you remember this you are the character written in line feed. So, one of this may be a terminator to say that the complete command is given. So, based on that you thefirst level interrupt handler can inform the second level handler to say that complete command is received now the second level handler can come into play. So, you can imagine how frequently this will be executed compared to this until the whole command is received this will not be executed right if for individual characters it will not be executed only when the complete command is given this is executed, but it will take some sufficiently a longer time to execute correct. So, now it says we have seen a example where a first level handling and second level handling is required in the interrupts ok ok this is the typical one example in a real life scenario where you may have to split your handling of interrupt in two differentfunctions and then perform the first job copying the character from the interrupt and you know you are peripheral and then copying into a memory and then complete command is received then call this function to run the command ok. So, this will be the second level of processing of serial code interrupt ok. So, I think this much ofintroduction is enough. So, let us see how we we will be implementing it in a real life scenario ok good I hope that is clear to you. So, this is the different procedure call which will be handled in the second level ok fine. Now, I am giving you a exact you knowdifferences based on whatever I explained you through a serial code you should be able to appreciate this differences. So, this implements a minimum platform specific interrupt handling similar to interrupt proteins. That means, receiving a character from the device ok and then copying it into a memory is a simpler minimum platform specific job and then implements long interrupt processing that means, processing the command is done by this second level ok. Intent is to quickly service the interrupt correct and then this is deferred job is handled there. Here record the platform system critical information which is only available at the time of the interrupt. So, if you do not read the character which was received and then you enable the interrupt the serial you know if you say the you are can receive the next character that will be over written. So, you have to copy that into a memory before enabling it. So, the minimum platform specific job in terms of serial code it is what I explained and the it could be different things for different period peripherals. So, and then upon further processing here schedule the execution of SLI head. So, who who does the scheduling of SLI head the first level handling because once the command is completely received then only this is scheduled ok otherwise second level may be deferred it is not that always the second level will be executed for every first level interrupt ok. And then if it is re-entered what I mean by re-entered the interrupt handling could be you can enable the interrupt while you are handling the interrupt ok. So, the same interrupt is re-enabled. So, that during the time some same or higher priority interrupts can come. So, no actually we are enabling this re-entering by dividing this into two functions and then normally during the second level interrupt handling the interrupt is you know enabled. So, partially sometime we may enable during the first level itself that is the work kind of a schedule you know scheme handling schemes or if you are handling it if you are not enabling it here the second level you need to enable it ok because it is going to be a longer processing. So, we cannot afford the interrupt to be waiting for second level also to be completed. So, that is the reason of splitting it, but there will be some occasions where you enable it in the first level itself ok that is another way of handling it I will explain you. So, program must move maximum processing to this level and minimize the execution time of the first level ok that is the difference. I hope this is very clear to you from the example that I gave you serial port interrupt very good. Now, let us see what are the different kinds of handlers ok. First I am handling I am touching upon the non nested interrupt handler. This is a simplest handler ok non nested in the sense why the handling of particular interrupt is suppose you are handling the IRQ ok the process the IRQ handler is inside the IRQ handler and the IRQ interrupt is not ok that is what is non nested it is not nested. So, let me erase this ok this arrow has come inside not a problem. So, SPSR this is SPSR of the mode here if suppose I am taking IRQ as an example this will be IRQ. So, when the interrupt happens ok. So, what is the sequence of operations I have already explained to you ok. Maybe let me go back to. So, just to recap ok this is a device ok and this is ARM it is executing some instruction I am doing it again to just recap on to make you are ready for looking at the code that I am going to show in this class ok. So, device is interrupting it assume that in this case I am just connecting the device directly to IRQ to simplify the scenario. So, it is the program is at 200 and it is executing it ok assume that it is in ARM state ok PC will be at 208 all of you are aware that it is plus 8 now because of the pipeline ok. So, this is the instruction which is being executed it could be any instruction does not matter because you cannot decide when the interrupt will come on you know when you are executing the instruction. So, it may be any instruction. So, the processor what does it do? It will first finish the instruction which is being executed that is there are different stages right three stages are there whatever instruction is there in the execute stage it will be completed ok. At the end of the execution the processor checks for IRQ input FAQ input reset input anything is there or not ok it will be checking holding these bits ok. So, once it encounter that ok IRQ is there then it will not bring the decode you know decoded instruction into the execute stage. Now, it knows that ok I need to handle the IRQ. So, let me abandon this. So, it can easily afford to abandon because it is not being executed. So, any anything that is supposed to be done by these instructions are not reflected in the register file ok register file is not affected by any of these instructions ok it is all inside the pipeline. So, we can defer it we will defer the execution of these two instructions and then handle the interrupt and then afterwards you can start executing from here. So, from the programmer perspective you will not see any difference at all because of the interrupt happened ok. So, that is the reason why the execute stage is completed because if suppose the processor decides to process the interrupt in the middle of execution what I mean by middle of execution the execution could be a LDM or SDM right that is the maximum you know cycle it takes multiple register load or multiple register store. So, it would have it is you know the ARM is interacting with the memory and then trying to load or you know store some values. So, if halfway through if it interrupts processor then the register contents are you know in deterministic now the half of the registers are with a new value, but the rest of the half is you know old value and if you allow the interrupt handling to go in between the execution then the stability is affected. So, you cannot restart this instruction because you have halfway through you are executed, but you cannot start with this next instruction also because this is not completed fully. So, to avoid all the confusion what the any typical any processor does this it will complete the execution of the particular instruction ok, complete it and then defer this instruction which are in the decode stage and the you know page stage and then go and service the interrupt. So, now what happens it has completed the 200 execution then what does it do? It has to keep this information of register file and CPSR in a safe place. So, which is the safe place the bank registers for the safe place. So, IRQ has come. So, it will go to IRQsbank registers and then you know it will copy the CPSR into SPSR automatically the processor does. Now we are not writing any code and then it will copy this you know whatever is the PC value this is the PC value it will put it in this R 14 and as you said this is R 13 these are the bank registers this. So, later on ok I am not right now using the stack remember that the stack is there and then what will we do? So, the processor could be in ARM state or it could be in thumb state when this interrupt was generated ok. The processor may be executing at ARM instruction or from the instruction. So, based on that but you you remember that the interrupt handling is done only in ARM state. So, it will change if it is a thumb state it will change to ARM state ok and then what it will do? It will ok. Now the next sequence will be PC will be loaded with the ok the IRVT interrupt vector table meant for IRQ that whatever is the address it will put into the PC and then mode it will change it to IRQ mode ok and then it will start executing from the vector table. So, IRQ it will go it will be a branch there. So, it will branch some interrupt handler then interrupt handle comes. So, this much of job is done. So, this is the first one and then this is also done together and then changing the thumb mode to ARM mode is done here and then it goes to the interrupt vector table ok and then goes to the interrupt handler start executing the handler. So, in this case till this point a handler has not come all the job is done. Now what happens after the handler is done it will come back to the it should come back to the next instruction to be executed. So, the handler has to take care of whatever the PC is loaded it should minus 4 it should do. So, that it comes here and then it should restore this value into CPSR and then it should restore the return address anyway is here. So, it will come here that will be put into PC right minus 4 will be done into PC and then start executing from here. So, from the user perspective in the to be in these two instruction lot of things have happened, but as a user you may not know because you are not seeing any change in the register file or in the CPSR or any other execution. So, the interrupt has come in the to be in with over affecting our normal flow of execution. I hope this is very clear to you I will try to explain this again. So, that you get back ok let us umber back cover. So, this is what is done here ok I will not explain this whole thing it is what is done then the save context ok this is because the handler also needs to use some registers right. If it is using some registers it should make sure that it is saved here because you do not know when the handler in the interrupt has happened this registers may be in use you have to assume that all registers are in use. So, the user program is using it. So, you have to make sure that the handler saves the registers of the previous content and then uses them in the handling in the handler. And then after you perform the handler job you restore the context handler that is the restoring of context and then it does whatever I explained you just now and then return to the task which was executed. So, this is the flow normally done it does not matter whether it is for IRQ or FIQ ok. And then now the question is here in the non-nested case we are not enabling the interrupt throughout the case ok whenever we are doing this we are not enabling the interrupt. So, only one interrupt can be served till this whole thing is completed ok up to this point ok. When it goes back to the return task then only the IRQ is enabled this is what is called non-nested ok. Now, let us see what I mean by this is not suitable for complex embedded system why because here this sometimes the processing may be longer because we are trying to do the first level as well as the second level here please remember first level as a second level is being done without enabling the interrupt that is what is called non-nested that means, I told you the second level could be a longer processing little bit compared to first level. So, during this time if you do not enable the interrupt then we are unnecessarily delaying the processing of any interrupt that would come from different devices because of processing this interrupt. So, which is not suitable for a complex embedded systems ok. Now, next level of handling is nested interrupt. Now, what happens in a nested interrupt one simple change this is same ok. This level is same this is same only difference is even the saving of context everything is same only thing is here somewhere either in first level handling or second level handling it depends on the implementation the enable the interrupt. What I mean by that somehow you make sure that know if interrupt once again one more interrupt of the same type kind IRQ is being processed and one more IRQ is generated the first time may be it is because of serial port coming and then another may be because of some timer interrupt happening it does not matter because if it is coming through IR interrupt controller ok you may have different sources right. So, we do not want to block while processing one interrupt we do not want to suppose you are working a serial port you are processing it we do not want to block the timer interrupt. So, that is why we are enabling the interrupt inside that ok. So, that will have a side effect that means you have to take care of that in your processing in the handler. So, latency is improved that means, because of this enabling of interrupt you are we will be able to recognize the processor may be able to recognize interrupts coming in from other sources why it is handling this interrupt, but the problem is we have a latent you know complexity in the implementation ok, but it improves the performance it improves the latency ok, but one more thing you have to remember that we we are just enabling the IRQ, but we may not have any prioritization among this ok whatever is being provided by the IRQ it is handled by by this method non external method there is no implicit priority given to the different sources ok. This is normal interrupts could block interrupt case if there are say suppose there were timer device serial device there are so many devices connected and if we do not give any priority to them then what happens is if suppose you are processing a serial interrupt though you enable this ok you are not enabling it immediately. So, it may have some blocking of that particular it may service the in service serial port first and then it will come to timer interrupts, because it does not recognize that they are two different interrupts it it recognizes they are two different interrupt, but it does not associate any priority among them. So, that means it will have some limitation. So, one more level of complexity is providing a priority among the different sources of interrupt ok. So, that is the one drawback, but it is a need careful implementation here, because you are enabling the interrupt you better be careful that the context what you are saved is not mixed with the the one more interrupt which is going to come it might come ok. So, I will be showing you an example of an S-ray as well as non S-ray. So, it will become clear to you ok. Now, what are the other ways of handling I am going to just give you a you know example of thisjust you know major points I will be highlighting here. So, this interrupts from various sources ok various sources means various devices are prioritized based on their criticality of the various system designer. See this priority is different from the priority which I mentioned about a reset FIQ IRQ and data boards that is priority of provided by ARM to different kinds of exceptions and interrupts that is different from the different devices that are coming to a particular input like IRQ ok. So, we are talking about a second level of priority different devices are connected to the IRQ and we are trying to give priority to them. So, that they will have some you know when two interrupts happen together one of them will be serviced the high priority one will be serviced. The priority level is used to dictate the order in which the interrupts are serviced ok um the high priority takes a high precedence. So, this is highly desirable feature in many embedded system and method of handling prioritization can either be achieved in hardware or software ok you can do it in software in the inside the handler or you could do it in hardware. So, what are the different between these two? In the hardware main the interrupt controller that I talked about is helping you in terms of giving you information about which is the highest. So, suppose this is the interrupt controller and then two interrupts are you know coming in from two devices based on the programming or based on the particular in to which this interrupts are connected the device takes a call ok this controller. Though both of them are generating the interrupt it will only first ask the ARM processor to process this first the high priority one and then once this is serviced then it may say that ok if this is also enabled ok individually you can you know enable an interrupt from a source or not by the you know ARM processor um from the micro controller ok processor. So, it can decide the priority based on the hardware. So, that is one way of implementing it. Suppose you do not have this hardware you you have a you know a dumb device where it you know it gives you a source, but it does not have a intelligence to give a priority then what you have to do in the handler in the first level handler the software goes to every peripheral and then checks who is having a pending interrupt ok. So, it will check in the order in which the individual priorities are suppose if it encoders the second device is the highest priority and this is not generated interrupt, but this is a generated interrupt then it will start processing that second level processing for this particular device will happen. Whereas, even if 3 and 4 are generated these devices are generated to interrupt it would not be recognized that means, it will be pending. So, it will it will serve is the second interrupt and then it will declare it will tell the device that ok I have served your interrupt then what happens next time again the IRQ comes it will check ok this is done this is done oh there is another interrupt happening from the third way. So, it will process it. So, this is the way this is how a software through software you implement the priority. So, this is as you can see that it is slower because it spends time in checking everything whereas, if it is done by hardware it could have done the job of you know identifying which device has interrupted and it will inform that particular device to the processor as soon as the interrupt is recognized. So, it will directly go to the possible level handling of the device highest priority device pending waiting for the interrupt handling. So, you will see that the performance is better if you use hardware software in the sense it will be less complex from hardware perspective, but you you may have to pay penalty in terms of it is putting that and identifying the device which has interrupted. So, these are the prioritized level no interrupt ok. How to handle different interrupts from different devices which have been alerted different priorities to them ok this is who is doing it this is system designer ok the system designer who decides the priority of different source of interrupts ok these are the people who does that. So, I explained about the hardware prioritization and a you know is otherwise other way of doing it is in software. So, it needs more initialization code of course ok the start of code will be there because you have to initialize it with all the handling of interrupt and devices you know interrupt controller needs to be initialized and priorities needs to be decided. So, these are the things we need to do. The advantage is interrupt latency is deterministic what I mean by deterministic suppose there are two interrupts coming from one low priority device and then high priority device because high priority device is processed first it can have a a deterministic. So, the handling of this high priority device is not dependent on the low priority interrupt happening ok in this case whereas, if there are no priority then it is not deterministic why when this high priority interrupt is you know coming that time there can be a low priority interrupt just before that it has to happen and then the handling is going on in the previous case then it will complete this handling then only it will come back and then recognize this interrupt. So, the it depends on the time at which the low priority interrupt is generated in with respect to the high priority interrupt. So, it is it is tied to the some other scenario. So, it is not deterministic ok whereas, in the prioritize case it is deterministic I hope this is clear to you other handling scheme the the other handling schemes are combinations of the previous two things what I mentioned ok. The the entrant handlers what are they do re-enable interrupt earlier in the service routine and also support priorities to reduce the interrupt. So, it re-enables it and it provides the priority also to the devices ok both are done this is the combination of these two. So, this is the most complex. So, compared to the so handlingmethods I have explained so far ok. Another one is priorities standard interrupt handler what I mean by that arrange the interrupt priorities such that time taken to decide on which interrupt to be handled is reduced ok. So, in this case what happens is it looks at everything and then on the order in which they it checks it will it will go on the service the highest available interrupt which is enabled it will go on service. But it has to be a time in checking that whereas, in prioritize case it is hardware is coming into play and then it helps you in terms of reducing the time taken for deciding which interrupt to service. So, the hardware does the prioritization. So, it is much more efficient ok that is what is called associating a priority. In this case it can support priorities, but it will do it in the software routine ok not too hardware support. Now, one level higher compared to this method is grouping the interrupt handler that means, suppose you can say that all the disk related interrupt to all group okUSB may be no hard disk interrupt. There are all some secondary devices connected to one source to interrupt controller and that in turn connects to ARM controller ARM processor to IRQ. Now, this whole thing is grouped the devices external devices and then you can divide you know you can decide all the timer 1 timer 2 ok and multiple timers you can group them all and then connect to the controller ok. And then you can decide one more thing okit could be UART ok I squared C this kind of a different say you know inter devices can be grouped together and then they are all connected to the controller and then they interrupt it. So, what are you doing we are grouping them all and then we are giving a single priority to each of the groups. So, we may say that timer is the most important it does not matter which timer it is and then second level may be commands coming from the UART or I squared C responses and the third level may be hard disk interrupts ok. So, these are the group level priorities. So, this is next level of complexity ok. So, in thissession we are we are covering only non nested handlers and nested handlers ok very good. Now, you are all ready to look at a real implementation ok get ready fine. So, this is a typical some code which is being executed by the processor ok. Assume that it is in user mode assume can you see from this whatever I have given whether this processor is in ARM state or thumb state you should be able to find out from the code that I have given. This code is being executed in the user mode ok the mode bit of the processor is in user mode. This is the code these are the addresses in which this this code is stored in the memory and then it is being executed by the processor I am asking you a question whether it is in ARM mode or thumb state ARM state or thumb state ok. Ifyou have guessed it right it is here ok ARM state why the difference between the instruction addresses gives you a clue this is there are 4 bytes ahead right there are apart from they take each instruction takes how many bytes each instruction is taking 4 bytes. So, naturally it is a 32 bit instruction if it is a 32 bit instruction being executed that means it is in ARM state right if it was in thumb state this would have looked like this 200, 202, 204 correct the all instruction could be there except that there cannot be 3 parameters for the thumb state. So, 206 it would have been this kind of addresses I would have given and this instruction I would have given you which is would have been in a thumb state. So, you you have to keep your mind such to recognize these things you are all now system programmers. So, I expect you to be alert good now I want maybe you can if you want you can you know freeze for a 2 minutes and then try to see what happened, but this is same as what I have explained you know need of even a break ok. I will just go through that I have already explained this in detail CPSR is copied into now I have specifically said IRQ mode because we know that it is an IRQ input ok I have told you that this is an IRQ input. So, no longer mode it is SPSR of IRQ mode which is copied in you know SPSR is copied into this please remember when this copy happened the CPSR is not modified it is same as what was in the original case ok that is when this particular instruction is executed at the end of the execution whatever is the value of CPSR that is copied ok remember that. Suppose if it was a move S ok and this instruction has changed the CPSR value condition flags that will be reflected in the CPSR already because it is executed. So, that will be copied into SPSR ok. So, it is safer to start execution from this instruction onwards after the service routing is serviced you know after the interrupt is serviced. So, there is a break in between the instructions the way it is executed this is executed at a particular time t and this is executed the next instruction is executed after time term t plus some delta t. What is delta t? Delta t is a time taken for processing the interrupt protein and coming back and executing the instruction. Though this step is there, but even these two executions the correctness is preserved by saving the CPSR values as well as making sure that the all the registers of user mode registers are intact ok. So, PC is saved please remember what is the value of PC which is so stored it is not this address what is stored in the IR 14 of IRQ mode is this value 2 naught C why because PC plus 8 only will be there PC would have advanced to this address. So, while saving there is no subtraction addition than to the value it exact just saves the PC value ok it is left to the handler to adjust the PC. So, that we start executing from this instruction sorry this instruction and then can you see the reason why this bit is there this particular thing is there think it over this corresponds to CPSR bit 5 ok CPSR if you want to this is CPSR ok 5 bits initial 5 bits are what mode right mode bit which mode system mode user mode a what mode whatever then this bit is for. So, bit 0 to 4 5 bits means 0 to 4 is a mode bit and bit 5 is the thumb mode and IRQ bit is here and FIQ bit is here ok 7 and 6. So, bit 7 is as a thumb mode it needs to be cleared why because all the exceptions are handled in ARM state please remember all the exceptions are handled in ARM state. The processor could have in this case it is not a different because already it is 0 because I told you that it is in the ARM state, but there is a possibility that it could be in some state the processor may be in some state and executing some thumb instruction and that time the interrupt happens and that time also we have to make sure that the exceptions or interrupts are handled only in ARM state. So, it has to be cleared please you know you should keep in mind this some manuals and some books may not know explicitly mention this ok. I do not see so, lot of books mentioning it, but they have mentioned it in the documentation. So, you have to relate to that ok and then IRQ is disabled please remember default this is done by the processor the whole thing what I am showing is done by the processor it is not with the instruction it is all done in sequence. The processor knows what to do it is all hardware and it knows what to do when it has to service the IRQ interrupt ok. And then it will load the PC or between now it can overwrite the PC value say CPSR can be now cleared because it is already copied please remember that. Similarly PC can be loaded with a new value because the return address where it is supposed to come after the servicing of interrupt is already copied. So, we are safe now to change the value of PC or change the value of CPSR or change the value of IRQ bit. Disabling IRQ is changing the CPSR value right and then we are changing the mode also. A processor is changing the mode also from user mode in our example it is user mode it changes to IRQ mode. And then now it goes to PC one night what is there this is the branch instruction to handler ok somewhere some handler is there. So, branch to handler happens now let us now I think all of you are clear about this clear about this I do not have to restate that. Now let us go to handler I want people to take some 5 minutes break not to walk out of the class ok please be there, but read through this code ok read through this code and try to understand what is happening very good. I think I do not have to explain at all because you might have understood it already ok, but just for the completeness and the continuity sake I will explain you . So, do you know the reason why this is done what is being done R 14 ok this R 14 correspond to which R 14 let me draw the register banks ok. When the diagram you can know what I am I am trying to come up with right this is CPSR all of you know this is SPSR all of you know sorry about this it is P this is R 15 this is R 0 what are they let me R write it in order R 14 and R 13 where this is pointing this is pointing at a stack which stacks whose stacks which mode it is this is IRQ because IRQ has come right. So, this is the IRQ stack. So, this is in some memory somewhere it is pointing at some location which has already been filled with some value because you can make full full decrement this is the stack operation we can if you recall you should go back to your previous class or look at the manual what do they mean by FD R 13 typically we assume R 13 as the stack pointer it is pointing at a full location that means, the stack value stack address wherecontent is already filled into and if you want to store anything into the stack stack we should decrement it ok please removelet me give us you know this is a high address ok memory this is a high address and this is a lower address. So, if it is pushing it will go downwards stack is growing downwards ok towards the lower address when I call say lower address I call it as a downwards. So, when one push happens it is here the one content will go here and then the stack pointer will come here because it is full decrement that means, it will first decrement the value decrement the R 13 and then store the content ok. Now, let us see what are we trying to do here these are the register list which which is getting saved because it is a store store multiple and then which is the base register it is very specifically mentioned because in ARM state it is not assumed that R 13 is the stack pointer. So, you can have anything, but for because it is in a IRQ mode you better use R 13 because you have only 2 registers in the bank register. So, you cannot have some other register as you know stack pointer because you do not have a bank register for it. So, it is always prefer and better use R 13 only as the stack pointer ok. So, now R 13 is used ok and there is a exclamation mark here you if you can notice it it means when you are updating the stack you have to update the pointer also the base pointer ok. Now, if you recall how this values in the registers are saved it always saves from the lower register to the higher register and it saves from the lower address to the higher address please you know these 2 are very important. Lower register to higher registers that means lower register means R 0 is a lower register ok and and then it always do a multiple multiple it is a store multiple right. So, multiple cycles memory cycles are you know multi cycle n you know non sequential and sequential if you understand the sequential cycle is started. So, it is going to do a sequential access of memory either for store or load. So, in this case it is going to store. So, it is going to start from a lower address to higher address why that is the way the memory can increment the addresses and then store that. Now, tell me ok assume the stack is right now pointing at some 400 ok. Now, how many values are there in this register list you can count it 6 registers. So, let me allocate space for 6 registers ok I am exactly showing you what is in the stack and where it goes in ok. So, that you understand it. So, 1, 2, 3, 4, 5, 6 very good. So, next after the loading is done whatever the you know 16 to 4 24. So, I will write it in decimal form not as a hexadecimal form ok. So, now this is the address where the stack will come. Now, tell me where which registers will go where in the stack I told you lower address I am sorry extreme is sorry this is not 424 it is going towards a lower address right you have to subtract 24 from there ok. So, please remember that it is some 300 some ok it is not 376 ok let me be specifically in decimal ok. So, it has gone below in the lower addresses it is not increasing addresses lower address. So, 376 correct my arithmetic is correct I suppose. So, from 376 to 400 is the increasing address. So, in this place as you are correctly thought of R 0 will come here R 1 will come R 2 will come here R 3 also here then R 12 and then our friend R 14 why I am calling it as friend because this is the register which is going to take me back to the original code. So, this is my friend ok good. So, this is how the registers are saved ok by executing this instruction clear ok I am not going to rub this whole thing because we will lose other things. So, let me ok I cannot write I thought it is written by me ok good let us see. Now tell me cause what has it what is happening is the actual service routine you can call it as a first level or second level whatever you call no problem, but actual processing of that interrupt is done here it is another function call. So, you remember BL what does it do is a branch with link register right that means, it is now currently you know it is executing some handler may be it is in 1200 address the handler is started ok. So, if this BL may be somewhere in some other address ok may be some 1300. So, handler is somewhere ok it has to PC has to go there now please remember it came from here it came to vector table from vector table it came to the 1200 assume this is the address of the handler this code is located in 1200 and from there it is now going to another place which is 1300 assume ok you can see the flow please remember where it is supposed to come back. Now it comes from here to this place now someone has to store this address right who does it because you are executing a BL instruction automatically the R 14 of IRQ saves the address this address assume if it is 1200 this will be 1004 ok 12004 this instruction this will be 12008 right this will be 1200c. So, R 14 now will have the value ok let me write it if can I write it here write it ok oh shoot I am sorry I do not know that I can go back ok let me sorry about that. So, we have ok so let me recall this is 1200 ok I told you that this is may be it is good that your board has become clean now. So, I am I mean memory is ok it is a short term memory 1300 ok this happens to be 200c ok. Now let me draw the stack I do not know whether I mentioned 3 in that I think or 276 ok I said 4 no problem ok this was originally R 13 ok R 13 is here ok this is R 13 this is R 14. Now this is a full location address is moved ok stack is I think it is a good recap for you ok. Now how many I have 1 2 3 4 5 6 so R 0 comes here R 1 here R 2 here R 3 here R 12 ok I will make sure that I do not erase this R 14. Now tell me what is the value here may be instead of writing ok I do not go there I do not want to go here ok here what is the value you know it is 20 what is that 208 why because originally R 14 was having 203 ok when the handler came at this place it has just save the PC value originally it had a 203 ok. After that this instruction this is R 14 right we are subtracting minus 4 and then writing into that to R 14. So, this value has become 208 now it is holding the address to which the processor should go back after the handling is done understood. Now this 208 is after this execution ok it has come into the stack 208 has come into the stack. Now this R 14 is free to be overwritten does not matter because you are not bothered about the previous content because we have the copy of it here. So, when we when the processor executes a branch with link automatically it is in IRQ it is executing this. So, it it sees R 14 as its own IRQ bank register. So, it will write the address to which it is supposed to compact that is 120C please follow me carefully here the processor ok gives you exact PC value to which it is supposed to compact after this execution. So, 20C is there in the PC andautomatically that is stored in R 14. So, you will see 120C here ok and then assume the PC is now loaded with a new value which is 1300 where the handler is. So, PC is here now R 15 is here see now R 15 you see the flow of R 15 what all has happened to R 15 initially it was here and then it became 18 and then it became 1200 then when it executed this BL instruction it has become 1300. So, R 15 is keep on changing please remember R 15 is not bank. So, that is only one copy of R 15 is there in the processor. So, it is being used by every mode ok there is only one R 15 you know do not mistake it that you know if that R 15 is also bank there is no R 15 in the remain other banks there is only one. So, R 15 keeps on changing now, but you do not have to worry now because from here if you want to come back if you execute an instruction which copies PC with a value in R 14 ok it is enough. If you execute at the end of the ISR if you execute a instruction which is called move S PC to R 14 it will copy this 12 0 C into PC PC will come back here you agree. So, now what happen after the servicing is done we have to put this instruction move S ok. PC comma R 14. So, it will come back to this instruction now what will happen now it is a very interesting part LDM FD again same logic ok the stack is same now you cannot have a different stack operation and then R 13 happens to be the same, but you may wonder whether R 13 is modified it could be suppose if there was a BL inside you have to save this you know you should take care of saving the value of R 13 you know R 14 there and then that would have you know overwritten the previous value and then it will come back, but in our case assume there is no BL executed. So, R 13 if there is no stack operation done here if it was done it should be restored ok. Please remember any subroutine if it is touching the stack ok before entering the subroutine ok after entering the subroutine suppose after entering the subroutine it is pushing something in the stack before leaving the subroutine you should pop that values ok please remember how many words are pushed into that that many words should be taken out. So, in this case we can assume either if the stack was used or not used, but does not matter when you come back here the R 13 would have come back to the previous value ok that is what is assumed that means it is pointing at the location where you know loss thing was pushed into. Now this LDM FD is loading how many words again 6 words ok this comes to R 0 this is copied back to R 1 this is copied back to R 2 this is copied back to R 3 this is copied back to R 12 these are all correct, but you may wonder in this case PC is it is copied to PC that is because we directly want to go to this location because effectively 208 is the address which is stored. So, this is where the PC should come back after the handling is done because at the end of this instruction handling is done. So, now processor will come back now please see this there is one second please see there is one carrot signal here if you recall I mentioned that when you have a a destination register a loss destination register as a PC and then you also have a that you know multiple copy in that you have mentioned this then automatically the processor now while assembler looks at it it will check the now particular bit in the code encoded and then the processor automatically copies the SPSR value I did not talk about SPSR at all so far. So, SPSR was having the previous value of CPSR right originally during this time it will copied into this. So, when we come back from the handler this SPSR is copied into CPSR ok and R 14 which happens to be see while copying into R 15 it is not taking from this location because this is no longer valid it could have been corrupted also this is what I call it as corrupted because of the BL instruction this R 14 is no longer having the old value. So, it has to take from the stack only and then directly copy into this R 15 ok please that is what is happening here it was originally saved from R 14 to the stack and then copied from stack to the R 15. So, that is what is happening here by directly saying PC here and then along with the PC a SPSR is also copied. Now what are what you get it you get the original mode user mode you get original conditional flat that was there when this instruction was executed and then R 15 also comes back to this. Now you see that from the user perspective when it is this instruction is executed now it is after coming back this instruction is executed it does not see that there is something has happened immediately that is the job of the handler you have to make sure you do not impact anything that was done originally before the handling was executed handler was executed understood. So, this is the simplest code I mentioned in that excel I took so much time to explain you I hope you understood this because next is going to be little more complex. So, I wanted to spend more time here so that you understand this fully ok very good I am ending this discussion now. So, let us just see you know completeness sake IRQ handle example assumes IRQ stack has been already initialized ok that because we are using the stack to store our you know values these two instructions are using the stack. So, stack should be initialized RJR to R 3 and R 12 are preserved because ok you may wonder why I am saving that there is a reason normally SC convention these registers are used for parameter passing and normally they are scratch registers which need to be preserved it is not that you do not have to preserve other registers where they need these two are these two are compulsory, but you may save the other registers also if you are using them inside ok that is the job of the service rotator. So, I will talk about this later ok do not bother about on composite call standard right nowyes for come I can say I mentioned it. So, R 14 holds the return address pointing at the instruction next to the last instruction completed next to the last instruction ok because we have modified the R 14 value. So, next to the last instruction completed this is the last instruction completed it is pointing at this instruction and it comes back very good I hope this is pretty clear to you if you do not please listen to this lecture again because this is very important for you to understand the next nested IRQ handler ok there are this that is going to be much more complex than this ok very good. So, it comes back now ok. Now, non nested handles on handler handles and services in individual interrupts sequentially high interrupt latency cannot because cannot handle further interrupts occurring while on interrupt is being serviced because we are not enabling the interrupt in between ok. Did you see that it was enabled anywhere in the previous code we are not changing the CPSR IRQ value at all I I I bit at all right we are just saving that and then going to the handler mode and then we are servicing it. So, we are not enabling the interrupt inside advantage relatively easy to implement and debug this is not it cannot be used to handle complex embedded systems with multiple priority interrupts ok understood you are all ready for the nested IRQ handler good. So, you have to pay a lot of attention here because it is little more complex do not worry about this particular flow diagram ok this it is very simple I will explain. So, interrupt is coming the same IRQ interrupt is coming ok, but the processing is little different in the handler ok I am I am entering the handler now this is I am not going to explain any more about the what is happening before this is the interrupt handler ok. So, this is enter the interrupt handler save the context ok then service the interrupt that means, what this is the first level that I call the BL service routine it may be a first level handling and then it will whether check ok inside this function it will give whether you need to do a second level processing or not ok whether second level processing needs to be done or not is answered by this particular first level typical example will be the serial port command I said. So, every character you do not have to do the second level only when carriage return is given you have to do the second level. So, suppose some in the first level interrupt and where you are checking whether the character received is a carriage return or not ok if it is a carriage return then you may say that a I need a second level processing now because on complete command is received only. So, that kind of a thing is happening in the service routine ok. So, prepare stack now if the interrupt service routine is not complete that means, second level processing is required then what happens is it is switching the mode ok from IRQ mode ok I will show you in the next example it moves to a ok system mode. So, it moves to another mode and then it prepares a stack and then copies the values from the IRQ to that new mode I will tell you why we are moving to another mode and then enabling the interrupt. Once we enable the interrupt that means, one more IRQ interrupt can happen ok that means, after this point ok after this point another interrupt can come and then the same code can be executed here ok no harm because we are doing something in between to make sure that the original content is saved. So, that when you go back from this handler ok you may get another interrupt and you can service it ok it could be IRQ interrupt it may be serviced ok. So, how to do that that is what we are trying to now see in terms of implementation ok let us complete thisflow ok. So, I will explain you this ok another stack is built in another mode and then we are copying from the IRQ mode enabling the interrupt and then if the frame copying everything is done then complete the second level service of interrupt that is this is the second level handling ok. Once the second level is handling is completed that is when command is given and then you have done done the job of the second level and then you go back to original task ok. So, one thing you have to remember when we enable the interrupt we are not going back anywhere ok it is continuing here only thing is because of enabling the interrupt the control can be taken back to IRQ handler again. That means, it can go this code whatever code this second level interrupt crossing is happening it will be interrupted see originally user mode code user mode was there it was interrupted and it came here and then we came first level first time you came here and then we enabled we saved all the things and then we enabled the interrupt and then we are processing we are sequentially we are here. Now during this time one more interrupt can happen and this can be interrupted and then another interrupt can come and then it can enter the handler again. So, please remember the interrupting is happening to the core which is being serviced ok in the second level interrupt handling the original user mode we are not going, but the original user mode because that is not more important compared to servicing the interrupt or that is always there, but we want to keep the processor open to see whether any other interrupts are coming in or not that is a way enabling it intentionally that is all ok this should be back of your mind it should be there and then we restore the complex and go back to the user mode ok good. I hope this this much you understood only thing is we are enabling the interrupt inside and then before enabling we are doing something ok I will tell you what we are doing. Now is the example ok please be ready these are all some core some constant which we can define ok please remember now please you do not use the same syntax for our ARM simulator because some of them may not work. Because this is taken from the book so you may have to change this code little bit as I explained in the earlier cases dot eq then this command this constant and then followed by this. So, I am taking from the book so that now you can always go back to the book and then refer the same code. So, I am explaining the same piece of code that has come in the ARM systems developers guide ok. So, let us see what are we doing this is the constant you mask the lower bit 5 bit ok CPSR lower 5 bits for the mode bit and then this is the SVC mode this is the supervisor mode ok. We are going to supervisor mode ok and then in between wait for processing for the processing and the i bit is 8 0 because I told you know the seventh bit which happens to be the i bit which you can we are using it to enable it ok. And then this we have already seen the code we are subtracting 14 from the R 14 and then saving it back. So, this is the code it is supposed to go and then this also you have seen already we are storing the same R 3 to R 0 to 3 and R 12 R 14 with this also I have explained you earlier nothing different and then we are servicing interrupt we are reading the device and all that and then ok some code piece of code do not worry about what is being done it is early just you know reading from the serial code means we are reading the character and all those very device specific is nothing to specific to the particular handling it is a very device specific there it is nothing to the scheme ok. So, then we are having a branch to a read schedule flags. So, is it safe to execute this instruction now BL yes because R 14 is safe. So, the original user program return address is modified by minus 4 and then it is saved also into the stack. Now we are free to use this BL instruction by overwriting the R 14 R 14 of which which mode IRQ mode please remember we are still in the IRQ 100 only. So, I think this piece of code you are able to understand I presume ok I hope I do not want you to have any doubts on this piece of the code. Now please do not be you know shocked with the so much of code I will explain everything ok another 15 20 minutes I will take. So, this is the some constant design ok constant is defined ok that is you is a hash defined up to C if you know it is defined as C then we are adding C ok sorry frame R 0 is defined as 0 and then frame R 0 is added with the 4 and then R 1 is defined as 4. So, basically we are recursive definition we are doing we are using the definition of this to define this and this constant is defined using this value we are defining this constant. So, basically this is a value 0 this is 4 this is 8 this is C like that it goes. So, so effectively these are all the different register values ok they are nothing, but R 0 to R 15 ok, but R 12 is there then we are using PCR ok and then R 13 is not saved because R 13 is a stack pointer where we are using the you know we are using the R 13 to increment and then store the values in the stack. So, we should not save the R 13 inside ok. So, this is the order in which they are saved ok these are the constant used for accessing them. So, do not worry about this definition this is only a constant definition, but I will explain the source code then you will understand it. So, LR is the link register which happens to be R 14 of IRQ then this is the PC ok R 15 value is going here it is not accepted R 15, but the original R 15 which came from the user mode and then this is nothing, but a frame size total frame size ok do not worry about this ok. So, I hope this constants you understood. So, let me erase it now let us see see before coming here what did we do we call this function ok the BL and then it has come back. So, after the BL this code is there ok. So, it is a continuation ok I have put it in a different slide. So, after the BL it comes here the control comes here and then suppose that routine is returning some value in R 0 it is like it has written some value in R 0 ok. If it happens to be non-zero ok not equal to we know if you are I hope you all of you are able to read the instructions from this ok LDM not equal to increment after ok. It is a it is a load instruction load multiple instruction with respect to R 13 ok and then it is restoring the values when when R 0 is not equal to 0. See it is a very specific to the implementation ok in the previous case ok if this routine says that ok not this routine the read schedule flag says that I do not need any second you know second level process in that all ok then it will return a value which is not equal to 0 ok ok. If it is a 0 second level is servicing is required ok. So, come back with that kind of understanding now it can go back to the original user program by executing this instruction this I have already explained you because prior to this STM of this is done. So, stack will be having those values which I explained you earlier the order in which they are stored. So, I will explain now also because you made for this particular ok ok. Now, let me draw the stacks which stacks IRQ stacks ok. Earlier R 13 of IRQ was somewhere something it does not matter which address it is ok it is load of you know pointing at I am sorry about the straight line ok my control on the mouse is not good. So, R 13 will be pointing here this is IRQ's R 13 and this is original saving ok which we have just now see. So, these are the values very good. So, I do not have to explain this this is the return value ok I will modify the return value ok. So, I will write it as a return address ok actually it is R 14 value which is copied, but it is a return address ok let me write it as R 14 ok which was subtracted by 4. So, that it goes back to the user mode got it. So, this is the status of IRQ stack right now ok. So, if there is no further processing required it will it will execute this instruction and IRQ mode has got a SPSR ok IRQ has two registers you know SPSR which happens to have the original value it should have ok. So, R 14 R 13 it need can be anything. So, it goes back by copying because I have put a character when it is copy this into CPSR and then it copies this value into PC. So, it goes back to the original code ok. Now, we are not interested in that part of a discussion ok. We are interested in something else ok that is not terms ok. So, this is stack is there ok this we need it now ok I sorry I I am sorry about this. So, this is R 14 return address this R 12 R 3 R 2 R 1 R 0 ok I will not erase it anymore ok. So, R 13 now see assume we are coming here ok this NE is not true that means, this value is 0. So, not equal to is not true. So, the control comes here you know that it is a conditional execution please remember I do not have to explain this thing load a LDM will be executed only even it is not equal to otherwise it will not be executed at all. So, if MRS will be done what is MRS very simple status to R register. So, now the SPSR was there originally right this SPSR is whose content it is this SPSR this is sorry this is the IRQ SPSR we are in IRQ mode this is the original SPSR value of user mode ok that is here. Now, this is copied into R 2 now we may wonder how can you over it on R 2 ok correct I told you that you should not over it on any register without saving it please remember you have saved it R 2 is saved in the stack. So, we are free to over it R 2. So, SPSR is copied into R 2 because you have to use the MRS instruction we cannot access theyou know SPSR or CPSR directly. So, it is fine I hope this is understood now what is happening here move R 13 to 0 ok. So, again IRQ mode there are how many registers 2 registers R 14 R 13 ok this R 14 is already saved into the register you know stack here ok IRQ stack is already having ok. Now, this R 13 is currently pointing here that value whatever is the value ok we are writing into which registerR 0 R 0 ok maybe I should put R 2 here and then the value is here ok value goes here. So, R 0 can also be over written can it be over written yes of course because R 0 is here we have saved it. So, we can over write with a value from some other register I will explain you why I am copying R 13 right now you assume you understand R 13 is copied that means, what wherever this stack is pointing at ok is copied into R 0 very good. Now, what happens add R 13 with 16 to 4 ok who does this 16 to 4 assembler would have done it ok it would have made 16 to 4 as 24 ok it is given like this so that we understand it as a normal human being we do not know suddenly 24 is put we will question why 24 right. So, you see 6 registers were pushed into the stack and you know that it is a execution is in arm state because it is the exception handling it will be arm state there is no question about arm state and then it would have taken 4 into 6 that many 24 bytes of location. Now, when we add R 13 with this 24 and write back into R 13 what happens R 13 goes back to the original location please remember R 13 goes back to original location what are we trying to do here we have moved all the values into the register in the stack and then moving back this R 13 into this now you may wonder oh what happens to the value in the stack it is lost no it is not lost it is in the memory only ok only thing is R 13 is now saying that I am know the stack is at this location and if you want to push anything please go ahead and then write on this ok if you want to and if you can, but actually speaking we have not restored this value into some other place this values are very important ok because because this value register values are in the stack we are overrating this register ok, but we are the R 13 is now gone back, but please remember we are inside the IRQ handler and we have not enabled the IRQ interrupt yet ok it is not enabled a default it is disabled on entry. So, there is no possibility of another interrupt coming while we are executing this code. So, we are assured of no one else coming and then trying to push something else other the unless you want to push something in your code here itself because the control is control is here IRQ cannot give the control to another IRQ handler to come and modify the value of R 13 by pushing something into it please you know you should have that in mind, but does it prevent from FIQ happening no because IRQ is a lower priority than FIQ during this time ok FIQ is enabled and FIQ can come FIQ will be serviced, but remember that FIQ module has a its own bank register and its own R 13 and R 14. So, see these interrupts will use this R 13 R 14 automatically, but if they want to use any other register they will save it and then use it they will stay in their stack and use it and then they restore it back and then come back. So, they will save it in their own stack FIQ stack. So, if the FIQ happens it will not be a problem for us this register values will not be corrupted it will be you will have to keep track ok even if it in between it goes to FIQ and comes back no issues. So, please remember that in mind and then now we are moving the R 13 up, but we are not copied the values from the IRQ stack here this R 0 on 2 3 and 12 and 14 are still there they are very valid they need to be copied, but we are right now just advancing the R 13 for some reason ok I will tell you later on ok. Now ok take it from me we have changed the R 13 value ok and I am giving an assurance that R IRQ will not come because IRQ is not enabled now because as soon as the processor regains the interrupt it has disabled the IRQ interrupt. So, unless we specifically enable it it is not a issue and then now what is happening CPSR what is CPSR here is moved into R 1 ok please remember the CPSR is currently had some value correct it will be and while the processor came into IRQ mode it modified the CPSR if you remember recall it made this into IRQ mode that is why we are seeing the IRQ registers. So, it is currently saying that the CPSR more bits are saying it is in IRQ mode ok and then it says IRQ is disabled the I bit is disabled ok that means, 1 you know it is set means it is clear it is disabled ok I think that is the convention. So, we are not. So, this is the state of CPSR mode ok original user mode CPSR is in SPSR correct which is there which we have copied into R 2 ok. Now, original user mode CPSR is here ok you have to keep track of that flow because we copied the CPSR into R 2. So, that SPSR was having the original CPSR value of user mode. So, that is now here and then the CPSR is currently saying that I am in IRQ mode of course, it is in IRQ mode. So, now that value is copied CPSR is copied into R 1 we can copy into R 1 because R 1 is old value of R 1 is safe it is safe. So, no problem we can overwrite the R 1 and then R 1 is masked with the loyal 5 bit ok we are just making sure that the oneness we are we are bit inverted we do the original CPSR we are only you know you are interested only changing the lower mode bit of the CPSR ok. So, that is masked and then we are r-ing it to the ACCD the basically the R 1 R 1 we R 1 this is the R 1 ok the mode bit we are changing into say it is in it to SVC mode still the processor has not moved the SVC mode R 1 is R 1 is modified. So, that we can write that R 1 value there. So, that is we are changing it to SVC mode ok one second and then right now what we do you see we still not enabled IRQ interrupt please remember. So, SVC mode they are made and then we are writing see that value into CPSR now ok. Now, this is a very crucial instruction which you should understand ok I need space for this I need to be careful that I do not by chance erase everything ok ok. So, we where are we we came up to this point ok we have changed the in R 1 we have made it a SVC mode SVC mode another supervisor mode ok we are going to that mode now and if you recall SVC mode also has its own R 13 and R 14 ok supervisor mode has its own R 13 and R 14 SVC mode you should remember that ok. So, we are now on executing this only control flags we are writing that into CPSR once this instruction is executed now it has come to SVC mode ok. So, no longer the original IRQ this mode registers are visible now this is not visible now ok and because of that we will not be able to access the R 13 that is why we modified that value of R 13 prior to come in into SVC mode because we know that once we get into SVC mode we will have the visibility of these registers which belongs to R you know SVC mode and we would not have the access to the IRQ mode registers even the SPSR of the IRQ mode we will not have the access that is why we copied them into R 2. So, you should remember all these values ok. So, let me now erase all this now ok we have any space for constructing a stack of the SVC mode. So, it will take another few more minutes I hope you will learn this fully ok then any you know anything you can understand ok any handler. So, I am going to now we we we should keep in mind that we are now into SVC mode ok. Now, I am sorry about this straight line supposed to be a straight line I am constructing a stack ok whose stack SVC stack assume SVC ok SVC supervisor mode its own R 13 is also pointing at a full location something is low the I am not bothered about that. From that place onwards to frame size take it from me this is ok 12 words ok this is totally we need space for 16 words 16 words means 16 to 4 bytes ok 16 words in the stack that is the total frame size minus R 4 this is 4 minus 4 ok 16 and just telling you what is the values of this constant. So, effectively we are subtracting 12 into 4 ok because 12 words into 4 only we are subtracting ok 48. So, from here onwards the R 13 is brought back to some lower value. So, let me painfully write this I hope I will have space for what are you trying to do we are trying to create a space in the stack by how by moving the R 13 down that means, because the stack will be going downwards right which stack SVC stack. So, this is 1 let me know 1 2 3 ok 4 5 6 7 8 9 10 ok 11 12. So, I said we are subtracting 12 into 4. So, it will come here and then we need 4 more ok later on that is a total size 16. So, let me write this numbers also. So, you may wonder why are we needing it because this is to save the registers see please keep the context ready clear back of the mind. We have where are we now we got a IRQ interrupt we came inside the interrupt we came here IRQ stack and then we realized that we need a second level of handling. So, before we start with the second level of handling you know we called this routine and I said that we need we cannot go back from the IRQ routine we need to start process the second level of handling. So, during the second level of interrupt handling we want to enable the interrupt we wanted to enable the interrupt, but we still not enabled. So, before enabling interrupt what we did we copied you know we modified R 13 to go back to this original place ok. Though we have the contents already in the stack which is not disturbed and our IRQ is also not enabled. So, this content will not be disturbed by anybody modifying the value of R 13 and pushing something into it. And then we took the SPSR value of the R 13 into R 2 and R 13 of R 0 ok wherever which R 13 actually wait a minute we want you know please R 13 sorry R 13 we copied into R 0 right that was which value it was before the addition was done. So, it is this value ok this value. So, because right now R 13 is now of IRQ mode has gone there, but we are we are having this value in the R in the R 0 register ok. Please remember that I am showing this maybe I can use different color it will help you ok. So, I mean color let me use blue. So, this is here ok that R 13 is here ok sick of R 13 you know red color. So, SPSR is here ok. Now whatever is happening in the SPSR mode I will show it in blue. So, that you will have some respect from red. So, now these are the status say you know current state and then we are here ok. Now I am doing a subtraction of R 13. So, R 13 will come here this R 13 is of which mode SVC mode please please remember we are into SVC mode because we did the MSR we modified the mode. So, as soon as we change the mode R 13 which we use in the code it will refer to the bank register of SVC these registers ok R 14 and the R 13 and the so on SPSR ok. We are not used to that yet SPSR ok. So, now R 13 we are just modifying it to this location and then executing this instruction ok. Now what all is blue is it is the SVC SVC mode what we are going to do. So, here we are storing from R 4 to R 11 ok wherever R 13 is pointing it. Now R 13 is pointing here I said because we have subtracted it 12 into 4 we have subtracted. So, we are going to save starting from here R 4, R 5, R 6, R 7 ok R 8, R 9, R 10 I hope I am not going to over board R 11 fine because we are saving only up to R 11 ok no problem. We have kept the space we are left it blanks that means, something no earlier value was there it will remain there no problem, but the R 13 which was here is moved here, but it is why it is moved because we are giving a STM instruction with the based of R 13 and remember that we are not giving a exclamation mark here. That means, it is it is doing a multiple say store, but it does not modify the R 13 value. So, R 13 remains here as it is, but the values get written into it from the register ARM processor to memory I hope it is clear to you ok and it starts from R 4 because R 4 is the lowest register in the list I hope this is clear to you. Now, let us go to another instruction LDMA R 0 from R 4 to R 4 to R 9 ok I need some more space let me create it here once again you have to be very careful ok I will create some space here ok ok. See you try to understand this this instruction now we are here ok LDM LDM is what load increment after ok. Now, with respect to base register R 0 what is R 0? R 0 is this R 13 value which happens to be this value I told you we saved it earlier right. So, this value this is the actually the memory which belongs to IRQ, but see even though you are not in IRQ mode nobody prevents you from accessing the memory which belongs to the stack IRQ stack. Only thing is you cannot access IRQ registers in the SVC mode, but you you can access any part of the memory right. Here we are not assuming some protection against some mode and all that ok. So, we will be able to access this content the stack content though IRQ registers are not accessible that is the reason we copy that R 13 value into R 0 which is visible in the SVC mode ok. So, now actually we are copying from the IRQ stack ok though IRQ in the IRQ mode R register R 13 is pointing here these values are still there in the memory and we can copy them. Now, where are they coming to they are coming to the registers starting from R 4 to R 9 let me draw that R 4 to R 9 ok let me for a simplicity R 4 R 5 R 6 R 7 ok R 8 ok R 9 these are all the registers we are trying to now overwrite with ok from this we are just one on one copy. So, R 0 will sit here you know you have to you know keep in mind it is it is copying you know lower registers higher register from lower address to higher address how many registers are mentioned that many words will be copied you agree right. So, it is increment after that means, you copy this content first and then increment. So, that is also working out fine. So, R 0 original users R 0 will sit here R 1 will come here R 2 the original user mode R 2 value will come here original R original user mode R 3 will come here R 12 will come here and then return address that modified return address R 14 will come here. So, why are we doing this because we want to save it in this stack we do not there is no instruction to copy from one memory to other memory. So, we have to bring it to the register and then move it to the memory because both stack are in memory then why you may wonder why are we doing it why do you have to copy it I told you IRQ is mode is we are out of IRQ mode and then we are we are going to enable the interrupt now ok that time what will happen interrupt can come and then this will be overwritten. So, before it is getting overwritten we want to preserve this value because these are the values which will take us back to the user mode code. So, before doing the second level processing we want to get the all the value which we left behind in the IRQ mode back into SVC mode why are we coming to SVC mode this is like a temporary place holder for us because this is SVC mode is modified no supervisor mode it will come ok. So, you should remember supervisor mode will come only from reset and SWA instruction ok. So, if it has to come from external world it has to come from SWA instruction execution or reset if a reset comes no problem this anyway whatever you are doing in SVC mode can be lost, but no other interrupt can bring the control to the SVC mode. So, it is safer and we want to enable IRQ interrupt ok after while we are servicing the second level of this ah interrupt. So, before doing that we want to restore the values that we originally left with IRQ stack into the SVC stack. So, before doing that we need to bring them into a register and then move it to the stack. So, why why are we moving into this register because we are saved this registers now R 14 to R 9 are already saved. So, we are no harm in overwriting them original user mode register these are all user mode values ok. We have restored we are kept it saved and then now original user mode values of this are brought here ok. I hope you are clear with this instruction. Now, what are we trying to do here? High bit we are taking that the seventh bit bit 7 we are writing it into R 1. Why R 1 is already having the original content that we copied from the CPSR CPSR right this R we R 1 is still continuing to have and there is no change to any of the conditional flags here there is no instruction which is modified the conditional flag. So, conditional flag is also consistent. So, you can use the same thing ok, but even then we are only changing the lower part of the book by it. So, no harm it. So, we are modifying the high bit now. We are continuing the SVC mode, but we are enabling the IRQ bit ok. This is what we are doing here and then we are writing into back into the MSR. MSR is a register to CPSR. So, we are writing R 1 into CPSR. So, now what happens is we are in SVC mode, but IRQ is enabled please remember at this point ok. After this execution IRQ interrupt is enabled. That means, it can effectively if there is a pending interrupt in IRQ now if the control can go from here to IRQ interrupt will it will there be any problem no problem because we are not dependent on this register anymore this stack values anymore because we have copied that into our own registers. So, please remember this registers are still can be used by the handler, but we assume that any handler using this register will need to preserve it and give back when it comes back right. So, we are not bothered about whether this interrupt register values will be corrupted, but the stack may be corrupted because R 13 if IRQ interrupt happens it will come and then push values into the stack. So, the handler will come again do the same thing what we did so now just now, but we do not bother about this values getting lost because we do not have any more dependency on them because the SPSR is also copied we have the copy here we have the R 13 value which we used to use value. So, we do not have any dependency with IRQ mode ok very good. So, I hope you understood up to this point now ok. Now, what is this instruction STM DB R 13 R 4 to R 7. Now, STM DB R 13 that means, R 13 is here how many values we are copying R 4 5 6 7 4 values that means, it will be decremented by 4 because decrement before ok R 13 will come here and then it will copy from lower address to higher address the way you have given it ok. The values are R 4 to R 7 register these registers you are copying that actually this register happen to hold R 0 value of the user mode. So, please see this now we are restoring the remaining registers which we left behind in the IRQ stack which we brought it here to R 4 to R 9. So, we have taken care of these registers now it has been copied now good. So, that is done now. Now, what are we trying to do here? STR STR means single store R 2 R 2 value whatever is the R 2 value R 2 is value is having SPSR value of original user mode correct. So, where is it supposed to go? It is supposed to go at a frame PSR. So, that frame PSR happens to be this offset ok let me tell you where the offsets are this is the PC offset ok this is constant we have I already showed you that this is R 14 ok where R 14 value should go and then this is the PSR PSR is the processor status register it could be SPSR or CPSR ok and then this is R 12 ok. These are the places where the values need to go ok that is the constants are these constants are actually giving an offset from R 13 to this value ok. So, R 13 this offset is added that means, we are accessing this location and then storing the value that is the address we have R 13 plus this it will access this location and we are storing value in R 2. What is the value in R 2? It is the SPSR value SPSR value of IRQ which happens to have the CPSR value of user mode please remember. So, basically user CPSR has come here ok good I hope you understood this better understand ok. Now, what is R 8? R 8 is holding see here R 8 came from this location I agree R 8 came from this location which was R 12 of the user mode. So, R 8 is copied into frame R 12 that means, R 12 comes back here through the register R 8 does not matter ok that is why we are trying to store storing the R 8 in this location. So, R 12 has come here ok the CPSR value has come here. Now, R 9 to PC ok R 9 what is it having R 9? R 9 is having the R 14 value which was the modified subtracted by code this is the original user mode code where it is supposed to go back to ok after the servicing routing is servicing is done. So, R 14 that is the return address ok R 14 will come here ok and then that is what is done here and then R 14 to link register ok. Now, where does R 14 what does R 14 have? That R 14 is this current SCC mode R 14 ok we have not saved it at all we have not used it at all, but we need to keep it somewhere because we may have a branch with link and all that. So, we do not want to lose the original link register value. So, this is the SCC mode ok R 14 this is the return address this is the return address ok you remember this 2 R 14 are different this is the return address originally to go back to user mode which is back to R PC and this is R 14 it is the SCC is R 14 we are just keeping it here ok. Instead of the order if you see R 0 to R 12 and then we are having a PSE PCSR PSR and then R 14 then R 14 that is all R 13 we are not saving because R 13 anyway is required to if want to push something into the stack we may need it. So, that is what is happening here. So, the whole stack construction is clear now ok. Now, we can do a complete inter service routine we can have a branch with link to some other second level service routine in this place what will happen it will go back it will go to some other service routine second level processing it will happen. So, R 14 of the SCC will be overwritten with the link register to come back to this location no problem because this we have already saved. So, that when we go back we will restore it and go back. So, now assume that we have as you go to the second level instruction ah second level processing then we come here R 13 ok with exclamation mark we are copying now up to this R 0 to R 12 ok and then see order does not matter what you are writing does not matter the processor copies in the sequence in the memory to these values ok these registers. So, effectively R 14 now will be ok after this execution R 14 will have the value which is here why after R 12 R 14 is here. So, in the memory. So, this PSR value will come to R 14 of SCC ok this is what this is the original CPSR value of user mode of user mode. So, where we bringing into R 14 this is the temporary place holder we are copying the full thing into SPSR CXS means all 32 bit are copied into the SPSR of the SCC mode SCC mode as the SPSR right please remember SPSR is the a bank register. So, we are copying that value. So, this is now original CPSR of user mode is now here ok understood we are we are in SPSC mode and we are copying the SPS value of PSR ok into SPSR and then now R 13 will be pointing here I am sorry it will be pointing the to the full location it will increments after right. So, R 13 will be pointing here now we say ok load two more values also now what happens this R 14 originally what was there in the SPSC because we over route with the PSR value. So, we are restoring it back and then we are copying the PC with the return address original user mode address with the exclamation mark when we divide exclamation sorry carrot mark what happens it copies the SPSR also into CPSR ok you remember that when we execute this instruction both PC and then R 14 is copied PC is copied the loading loading from memory and SPSR is copied into CPSR the user mode. So, effectively we have come back to user mode now ok actually we came out of the user mode to IRQ and then came coming back to the user mode through SBC ok the supervisor mode that is what is happening here I think this with this we are ending this particular I hope this is very clear to you the construction of the frame and then coming back how we are copying back the value from the stack you should go through this code again draw this stack understand every line of the code. So, that you comprehend this whole thing ok I have taken extra time to explain you ok I hope it is useful because nowhere you will see this whole lot of things explained in detail. So, I thought I will take time to do this for you guys I am I hope you know it makes some a difference in your understanding and you enjoy you know writing your own handlers ok you will be equipped to handle your own handlers after this I hope this is clear to you guys ok with this I am ending this explanation. So, let us go back to I am erasing right let us ok somewhere is handlers multiple interrupt without priority assignment median to high interrupt latency advantages can enable interrupt before servicing of individual interrupt ok I told you the second level handling is done after enabling the IRQ interrupt what is the disadvantage it does not handle priority prioritization interest, but so lower priority interrupts can block the higher priority because IRQ it is enabling IRQ, but the second level from it is taking some time to enable them. So, there may be a block because of that because it is not done in hardware it is done in software, because we are first level handling is done in on software second level is also in hand software, but we are enabling the interrupt here, but during this time there may be some wastage of settings because there is no hardware specificenable priority. So, with this we have come to an end of this class I took a little longer time I hope it is useful to you guys. Thank you very much and I hope you enjoyed I ideally enjoyed sharing this with you have a nice day all the very best with your understanding. Thank you very much for your attention. Bye bye.