 Okay, so good evening. So tonight I'm just like I put it here. This is the messenger. My name is Brahim. I'm a chef I work for a star If you know me well, I'm into FPGA. So all my papers have to have some FPGA aspect This paper is a paper I found Quite recently. It's actually I don't remember actually the date of it But it's not really a recent paper and I will show at the end of the presentation Actually, there's some new models that you can actually buy which have really really good Sorry good Performance and this is actually more of a design project from from some years ago my interest in FPGA is really for my work and for my background in single processing and I'd like to see with some people who are Into a radio amateur like this young young man behind there Into how to combine some of the FPGA design and some of the communication aspects And I came out came across this paper, which is an FPGA based Transceiver module from this guy called John Stephenson. So this is his indicator thing and is is from California in in America so basically he had a little platform that he designed and he really tried to To to to to get a motivation from the fact that what you buy is usually very expensive for that type of Communication systems and he wanted to design some very small module that can do the job compared to To to the sort of equipment that you can get and also it's more of a design study With a lot of different models and FPGA aspects of it. So the hardware is actually based on a quite small Xilinx Spartan 3 FPGA and he really put some some specification on having an analog to digital converter and Yes, it's It's the Papillot 1 500 basically. So it's quite quite a small small one Compared to yours but for like Yes, you can put the 16-bit microprocessor. That's what it's actually doing. That's that's the whole area So it's quite a small hardware that you can you can play with and so he really wanted to have some sort of high throughput in terms of It's just six. I'm not sure. I'll check it out. I think it's a yeah, it's a risk So it's really here is the amount of data that is really 80 mega sample per second and also with Processor you also you can also plug basically an internet Port which is here in So sample right if you look at the specs actually it's like 80 mega samples per second. Yeah, 100 mega bits per second This is the just to you know to use the the bandwidth They would have to have some kind of RAM static RAM inside. Yeah They don't have it today. The the the spatter has some some block RAM inside. It's like 64 Yeah, but you will see afterwards the the thing it's actually it's not really using a lot basically using Yeah, that's true 80 mega samples that's it goes really through is basically it doesn't really store a lot It's not like sampling like sound or so Basically, it's really a small you have to do all reduction or data reduction on FPGA and You cannot do something like, you know The hacker of that that is just down to roll data But but in this case it basically this is more because of the of the frequency of The modulation etc rather than and really the amount of data you want to keep you basically same samples The transmission actually not not not so I think it's 12 I can look in the there are some side of the schematic at the end So basically as this Ethernet connector, which he wants to basically pump data through four megabits flash ROM That's basically an external Flash ROM coming away is it probably this one You have some low speed the DAC A GTAC port which is to communicate with the FPGA and program it etc and the areas to 85 port just to debug You also have some 10 pin header here. These are the standard Basically connectors when you want to connect sensors and so Really it's a small little card that he basically designed and I guess the whole exercise for him to basically Look into what is actually required to actually have an FPGA transceiver model So if you look at the the schematic here the diagram The central here is a CPU and then basically talk to some RAM for the different functionalities and then he has some CRC some filters Asquecy to know your codec that's quite standard He has some codec decoder and codec and then here is that he has an SPI Go into some flash and he also can talk to you are this is a quite standard modem and VTB decoder So the whole system is really to show some sort of communication sort of of implementation The thing is it has a two kilobytes of RAM does mean that What is the packet size that you can push through? Most of the thing is 16 bit. I think if you look later on the other side 16 bit data that he push 16 bit But how how many samples for this? I don't remember it's exactly The I don't judge the the choice of these stuff I'm just presenting his work in a sort of bigger context here. I'm not sort of criticizing and okay The you know for sure when operating parameters that when you see a system like this You can obviously have much more RAM into into you know a more recent FPGA. You can have a you know Very good with this pattern 6 you can get no much much more than what you have here the whole issue is more implementing on an FPGA or whole system that can do the transmission of Media matter then again, you may be interested in specific band widths because here the RAM the the bandwidth is it tends to be the issue of the of the Of the duck, it's really the duck or the throughput you can go through the duck. The duck is 80 mega samples. Yeah Yeah, but I don't think you will make 80 mega samples Unless the signal so you could not put that's the common coding is they also go now You know that you do FFT on the whole on the whole package To fill in MS 80 MSPS. That's 40 megahertz with this This is the paper if you read the paper is doing some some communication with it. I'm not But he will not saturate He has a pretty exhaustive explanation of all Yeah, all of his design for me the the the main issue here on the sort of paper like this Which I find interesting is really that he explained all the different circuitry that are basically used in those in this sort of Transceiver module. So the signal here is analog Sorry analog here you get sample you see 12 to a bit some sampler then you have some some CIC filter The other way is CIC is a comb filter. I will go through the slides So really from an FPGA or hardware point of view each different blocks like said this one is a filter a clip a resample He actually explained all the different blocks in his paper So from someone who wants to learn how this is actually implemented on an FPGA This is a good paper that give you a kind of a broad Image I mean, you know representation of all the different building blocks of a transmitter Yeah, yeah, sorry, do I see correctly that it allows you to pre-mix ADC with this I think this one becomes a sort of exclusive either you get then also this is only one way I assume so although otherwise here you can go that That way, but you can also go that way and then all the processing to the to the baseband thing So it's like a usually it's like a two it's like a two porting you send that and this is This one is doing the job of going that way, but also this is basically the more later more later in the same same thing so in terms of of system you have quite a complex Blocks which for example here you were mentioning by the FFT This is a 16 bit it use some of the RAM for the CPU to read to write the rest basically goes into the baseband output input Some of a block or Cordic. That's a specific block time recovery before Going to the CPU apart. So those blocks that I would say from an FPGA design. They're quite standard and He's basically for me the interesting thing what is paper is that really is showing all the different blocks and how they Integrate and interrelate to actually have a full picture of a transmitted receiver. So Afterwards he goes into some details about the different blocks that he basically implement For example the frequency that comes here It basically gets you know some etc goes to some ROM and then some output here So the DSS which is this direct digital synthesizer, this is like the master clock in a sense to have some sort of Emission and reception and down the line. He actually also explained the different blocks how he implement like the ROM etc Different buses. So it's quite detailed and I haven't actually found I haven't really find any papers that go into such detail This is quite simply simplified because there is some design choices For example in some parts here these that tends to be registered at pipeline the delay of some blocks here But he doesn't go into too much detail, but at least I get an overall Image and actually representation of all the different blocks So it's easier to understand what is you know that sort of module and how You can also simulate those blocks even in software because down the line This is done in hardware as a ROM as a multiplier, etc But you can also look at it from a software point of view from a module point of view. So he also Get some algorithm from some original. Let's say a motor and notes and he gives some some specific Level or specific number of stage bit width, etc to to basically also justify his His his design Yeah Yeah, so this one is That's what afterwards you end up with a CSE so the the CIC is a cascaded integrator comb filter This is the implementation and what you want Basically here is that the FC that you have the central frequency that you want to really focus on The comb is like a comb filter. It's like a comb that you are and all the different I would say notch here the stop band here exactly at to FC So it is basically all the different harmonics you try to eliminate all the noise so these are the type of signals that You can see that also in audio some some specific effect in audio are using this but this is quite specific also for this because What do you want is the maximum amount of energy that goes into your antenna in a sense receptor or emitter and then at those harmonics There the the signals gets all the noise related to it gets attenuated. So Afterwards you can basically work out that you know, you have some counter you get some some gain here And then the transmission reception and then it gets this is a Subtractor and then this is an additional another and then you end up with a big circuit here And then it goes like this Overall disease also a CIC is also quite a complex but but non block in signal processing Yes, yes, so the filter That's the whole the whole issue is to keep into the digital domain The thing is you sample and everything is done in the digital domain here You don't want to have analog the only analog part is the the card with the duck the input of the duck once it's it's inside The issue is to have a fast FPGA doing all the filtering all the decimation all the with sudden RSA Correspondence with an analog circuit if you're actually doing it in analog domain in the first place So if I have filters these are standard filter also And then you have some data that you pump into here You have your coefficient in your other one and then you do those Multiply multiply carry and then you have an output here. So these are quite standard blocks Of course in it doesn't actually say what are the filter coefficients, etc. But these are standard techniques that you can also apply and these are quite a nice I'd say building block for you to implement in an if I filter those filters You can also use for all the project not only for communication, but all the other type of thing There's a that's quite specific. This is I never came across that type of block is called a nice blanker And it seems to to do some some quite specific delay thing with some reset. So this is something that Is new even to me knowing a single processing for many many years So this is kind of building block that that is interesting to actually study and actually you know simulate itself and Feed with some data and see what of course there's some function here Let's say absolute value that you had it to implement usually it's with a look up table because this is 8 bits only Then you take the magnitude you compare you have a limit and then at some point that's out of circuit Basically reset the output here So you have this effect of of blanking the noise that you okay enter There's like a threshold noise threshold blank to be honest I need to see me do because I you can represent this like You know as some sort of equation answer Well, here is like a delay line that you you will basically blank or reset the fourth every so often because of the value So this you need to basically Something here for example here you you also have different stage with a single clock and then you have Or gate or none get okay. Is it all open source? I cannot find a source code So I need to email the guy I find only that that actually that document I don't know I don't actually find the Yeah, yeah initially actually I thought that would manage to get some of the code or something on the project But I cannot find it Yes, yeah, it should be yeah, I think the the board he must have designed it to maybe sell it as a small project at some point Yeah, because it's like it's almost Yes, yes, yeah, yeah, yeah, you can possibly upgrade it with slightly larger Spartan or Spartan six sure because they have similar been helped for me the Yeah, the motivation is not really to ask the code of someone is more like I Can write the code to actually implement this one and see what is actually because those those a fire filter They are very standard thing, but this one. I don't know. So actually this one is more interesting for me to To try to tweak and see actually what he knows more about It's quite a complex and of course the whole system because it's based on the CPU has all those different Registered you can tweak so it's a bit like getting a data sheet of you know of a component saying you know if you tweak this one The decimation you need to put the value here, etc. So down the line You could have a even a Linux driver that actually poke Yeah, yeah, yeah, I mean the the whole thing here is that you see 8 bits here 18 bits here Which one of the 18 bits do you actually use here? Yeah, these are not always, you know clear So there's also some box where suddenly there's two arrow and there's no source in the diagram So like what what's controlling this, you know, you have to yeah Yeah Yeah, this one is is the is really the one that you know minus 60 dB here it gets, you know massively Yes, this is after the Yeah, correct within the the whole system Unless I get the code because basically it's a machine that you know read something they do FFT control everything unless you I get the overall I would say behavior of that no transceiver. It's very hard I could guess the other 50 doing some FFT and try to get the spectrum try to have this and that but otherwise It's still only a specific view of this system. It's not the fool You cannot replicate it from from that paper basically But it's still an interesting paper from a from a hardware a pure hardware point of view for example automatic gate control You have this in your phone You have this in in all sorts of equipment because you don't want to saturate, you know So you have for example 20 bits impulse. You have some shake for it No, sorry, sorry. Yeah No, that's like many That's Also in my laptop went into some funny I can put a PDF He's getting he's getting That's not the problem. The problem is up from the I said yeah, so it's not the laptop. It's not it's not it's because he's he can still capture the signal from here Oh, he can't push it up to the projector. Oh Because remember the engineers that I she's doing the recording so they get a signal first They then they split it they capture it. Oh, okay. So it's okay Yes, yes, yes So how does it work you set up you you Hgc so automatic gain control so these are standard also blocks that basically have some measurement of the magnitude here which feeds back into a control and afterwards this is basically here some valid data and somewhere here you can specify the attack and release Basically influence those so it's basically feedback. It is a feedback of the signal and you adjust. So this is like a classic more less classic Hgc signal a Lot of tweaking parameters I like the fact that you end up with a system that can actually be poked with a lot of parameters and afterwards The whole thing runs. There's a resampling part. So the resampling here says it may be be switched for application with the boot rate that a lot integer values of the ADC so this Becomes maybe the main thing that you mentioned. He ended up basically done sampling probably some of the other values If if required So for these I mean those those blocks they tend to be all others And then some sort of register that you specify which output from and then some ROM that calculate things And then those are pipelines. So you end up with registers to align the data So down the line those you have basically here OSR and the new sample and then here you have end up with two output And you have some counter in the middle, etc. There's a compressor and a clipper So it takes the absolute values. It calculates some Which one is the biggest and afterwards it will interfere here and this depending on the gain will multiply the 16 bit value by 16 bit here and so here you can Softened or I mean compress of or basically clip the values at the output of the whole chain is not really clear in actually in the thing because You get all the different blocks, but you don't get the overall so for this For the but there's two there's two here. So I assume it's for the the receiver and transmitter Otherwise, it wouldn't be the voice is really mono. No when you have the microphone So do a lot of those the path the data here tends to be To get to to and afterwards later. There's this. Yeah, this one the this is more like the modem Which uses a Cordic so Cordic is a block which Is like multi-stage and you basically approximate a certain value depending on the input So here you have x and y and z and then it basically do some processing So these are quite interesting because there's a lot of paper on Cordic in literature So this is probably a specific implementation and he mentioned a lot of you see the rotating engine consists of three multipliers 16 bit each of them the 32 bit other so he really specify all the path and he also in some of the part of the text he also Justify the number of bits, which is the basically precision of the data with the performance of this system There's some time recovery aspect also in one of the block So this tends to be Some input that comes here If you have say 14 bit ADC It's pretty normal if you don't sample or the Cordic or another analysis usually also don't sample That you will get a much more accuracy. Yeah, but here I think the path is is typically 16 bit I think because of the If you some B ram in the data in the in FPGA, you have like 8 bit 8 bit B ram So this is sort of sort of standard thing, but no a path of 22 bits This is not a standard thing for microprocessor. It's more on an FPGA design when you can adjust all the different Like both a bus width and everything There's a new detector. So it's the same this It's quite a good exercise to actually understand, you know, it is an input the ram Output something from an address that would be an address The address would be the output of this of this other and there's a feedback here So this is tends to be some sort of accumulator Etc as a counter and then at the end it split some signals go to different different part of the system So this is quite abstract in a sense, but this is a second FIR filter. It has also some Some registers and then there's this FFT. So this is a quite an important block in single processing when you want to have this The data in time domain and you want the frequency domain and get a spectrum of signals and then you have usually all these Blocks here are Ram block ram. So one of the specificity of FPGA is that you have two ports port A and port B and you can write and read So you basically really have to to write or to read and you cannot read at the same or write at the same location there's some sort of Limitation, but these are also blocks specific block of FPGA design that you can take advantage of so the FFT let's say output can write can write into the ram and at the same time you could read some of the data So you can actually think like this. So in one clock you can read and write. So this becomes more advanced from an FPGA design and then there's this polar to rectangle conversion so for this Assume is the I and Q of those signals in in RF when you have the intensity and the quadrature and So there's a circuit to do polar to rectangular conversion So it's just a rom and afterwards is basically a selector here And then the other round is a rectangular to polar. So they have those Distinction and afterwards this Select select select and at the end is another so here is the magnitude and the phase. So this becomes really the You you you interpret the data as a complex in mathematics. It's a complex variable with the magnitude and the phase a lot of a lot of Same a lot of like pre-calculated tables and also registers. You can park and pick In communication, you usually have this cyclic redundancy check Which is you send some data and you also send some parity bits that calculate some syndrome or specific function of the data and When the data is received you check that those bits are right if they are wrong Then he means that you have specific bits in the error. So these are quite a standard Like the bits go here. They so And at the end you have some output. So these are CRC circuits that allow to to verify the the good behavior of the transmission There's also a VTB decoder. So that's a whole also Big topic in communication VTB is a I think that's was 1970 the first few papers. So actually my work. I actually use a flavor of this For for for some design. So this is a small VTB decoder But it has all the different state and the distance between the different words, etc And the minimum distance get basically reused and ultimately you try to find the Path within the bits that has the smallest value and then you basically choose this one as a good good code word Overall, there's also what we call BCH So it's a three researchers which have invented also a coder decoder which has specific Behavior for communication. So this is also included. So actually when Yeah, yeah, so they when actually first read the paper there was this CPU, etc But actually as FFT, there's a lot of functionality in there that actually, you know It can be really study from from from a communication or system point of view So this is basically that paper. It's a bit It's not I wish I could you know, like implemented the whole thing But I think it's a bit of a long exercise, but for people who want to dive into Communication and FPGA, I think it's quite a good introduction into all the different blocks There's a big part in the appendix of the paper dealing with the risk processor Hardest and recently With the Pavalela, there's also all these boxes that like you know both that actually have Implement they implement those multi processor, multi-corp like risk Architecture, so I think this is for me also some some sort of background Platform to actually look into he basically doesn't really cite a lot of Lot of papers, but those quakes or winter package something this Maybe this is his own sorry Publication as small articles and this one QST. I assume that these are My magazine or more like a publication Yeah, publication for radio amateurs When I look for them, I don't find a specific URL Okay, okay, so that I'm looking to some some some by all papers, but they are usually into introductory of This one, I know because this one I use that back in my BNGS to actually since I sound so this the day the motor DSP is Is quite quite Yeah So there's a second paper I think he wrote after which has this title with a mesh mesh communication Yes, yeah So so I assume he built that board to also implement like a bigger a bigger bigger system So this is really just to print that paper. It's not I mean it's quite for me It's FPGA, so it's not so technical But it's right to know to to to show that FPGA can also be used for that kind of application Like Michael's no Mica mention One can implement a lot of algorithm which are not About communication, but all the domains to accelerate and so he actually provides also is Yeah, the schematic. This is basically the part with the the ADC and the duck It's actually the very poor quality you can when you zoom you actually cannot really this Distinguish the the thing The backs are on board. Yeah. Yeah. Yeah. Yeah. No, they're on the on the board But yeah, no, no, they are not sure I think because yeah, you cannot go to that that amount of And then you have this like simple oscillator with the I think 80 megahertz oscillator Yeah Okay To to light up the Rest in peace So by looking at those modules, there are some new design Which are also Looking at streaming video, etc Using RF model and you can find recent thing from this Sidekick Which are very small PCIe so actually this board you can actually fit that into your PC because that's like the size of You can basically have a slot is really like the the Bluetooth module used to have etc so those have if you look here They have a mega source. So these become 70 to 6 gigahertz And they have a connector to receive and some connector to Emit so those boards with an FPGA which is a zinc This thing of Spartan Arctic seven This becomes a more Modernized version of basically that's small project. So if you're interested in in some of these, I don't know about the price I think it was more like a So a flyer and I think I posted this into the the group but Basically, they advocate that the issue that having this FPGA here can also reprogram all the different module that you want I would say nice thing is that mini PCIe you just put inside Yeah, but having a seven gigahertz Box here Why not I don't know I'm not sure the Wi-Fi the Wi-Fi is 2.4 and then 5 5 something 7 gigahertz and it becomes a bit But something that is the port those port here No, it's it's connected to a bus this is this is connected to your boss. I mean between I think it's a bit like those thing you end up with a small So how Oh, you mean Did this one put this in a laptop? But if you put it in any of the small little mini PC things you can just run the UFL out But they show they show that you can you know, this is the format of a Laptop module and they use me used to have I have that actually out of my old laptop those Bluetooth Wi-Fi, you know, you used to clip and basically M2 is slightly more interesting because it's also used for SSDs Yeah, so a lot of laptops they just give you like two or three of those ports one is used by the SSD ones used by the Wi-Fi And you can do whatever you want with the third and most of the time the antenna is actually In those laptop actually it's outside the high frequency. Yeah, but for low frequency. This thing is You can just use Arduino because the antenna will be your main The 70 megahertz Maybe Going through the spins of Arduino and it's an animal show An APG for sure I mean, this is just you know the This schematic or this sort of system is quite, you know a small one and then when you look now I wonder even this one is a Kickstarter or something like that. I'm not sure but this is more modern version of things And I assume that when they provide the boards like this see here the API software provider needs interface So this will have a Linux interfacing and API drivers, etc. for you to to play with so remember you showed Something on your laptop once When we were in paper thing is that the other question I have here you have mini PCI so you need a PCI driver Well, that's that standard in I have played with Have USB driver So they they have interface of USB serial or is our USB a raw data stream so streaming I assume that those those those project will will provide Yeah, you know in interfacing Think yep, they probably provided but the nice thing is that if they have they will eventually be a free one Yes, yeah, that's me. They would work better than Hakarev because Hakarev when It tries to use the whole band. Yeah, they were saturated What's the best of the PCIe mini one They're both PCIe on this one Compared to compared to USB. This is ridiculous. Yeah, so this is a PCIe 2.0 x2 That is 8 gigabit per lane. So that's 16 gigabit on the mini PCIe one. Oh, it's like the Lots of lanes. Yeah And the size is Just like, you know line directly to my memory Okay, that's my presentation. I think it's a I think in the future. I'll try to present something that has a demo like something that you know works Otherwise it tends to be a bit more Maybe it's possible to some just send an email to guy and ask if he's he said he passed away. He passed away Brandy passed away No Four years ago The good news is that the ARL has picked up this world and their team is actually working on it for a info The ARL is not just a radio society They are actually a corporation and they have the proper equipment and that's stations and all that Required to do all this coupling is only whether you You see the some of the materials they only give to the members Who have or are signed by plates on the membership and all that and they do How this all these all here and all that If they do release it out for free But it's like association the question is Somebody has to have motivation to push it and the question is also how much they want to share Oh, yes, true But most of the time they do I mean, you know the guy put the schematic on the internet if he doesn't want to share He don't put schematics. So You know, it's not uh for for playing with this you need something like VHDL code Yeah, I assume that is probably programming very long not just, you know abstract schematics But ideally ego file if you want to quickly start To make the board Unless it's some somewhere and one of so, you know, maybe he has the website himself. I didn't look because you need to At some point say you are the Around I mean the whole issue is that the the whole system here is all in the pga You know only only only all this is all a pga The urt is programmed on a few pins of pga. This is a connector. This is a chip This is a connector. This is a connector another chip This is the the FE Fee just yeah So Actually, some of these uh system are assumed that they could also migrate be migrated into a zinc Then you a macro blaze or something and you have But the issue is how do you program? All those fancy stuff inside So that if you have phdl code, you know, yeah And also according or fft. This is the standard This is standard I haven't actually looked in the open core whether there's some project dealing dealing Nobody like a whole a whole whole system like this. I don't know I mean in my case, I'm interested in that risk here because I read a lot of papers and the trend in fpj is to have a Big fpga and a massive network of small processors that do a lot of stuff. You should look at open risk Also, yes, yes Risk v risk five, right? Yeah, the the guy in ntu the some professor at you Work with the with those having mesh of risk fiber processors. So we try to try to see Okay, thank you very much. I leave uh Is if I would be trying to replicate it from scratch without any board design For low frequencies that probably doesn't matter but for five gigahertz There may be a matter. How well you designing a board because you probably need a ground plane You know isolated signal in my case if I if I use one of my phdl from work I would try to Have a high speed port which is usually a bnc a proper bnc and you have two into a Board which has those and those Analog device has those boards so Somehow there's there's already some some some you already have well. I went to a course. I went to a course Yeah, I went to a course when they have a zinc and We bought two kits basically with antennas and there's an ad 9000 something You simulate basically all of this into into it, but it cost money. I mean it cost it cost money Do you have standards in board and standard ad cdx on it? I think it's a It's an analog analog ad There's a chip a transceiver chip. So whether it's interface With a high-speed port or whether it's actually a bus. I assume it's actually a high-speed sport I went to a course like this. So once I got those boards, maybe you can have a demo into a Thing or something maybe a packet Yeah There's a the issue is that they they they you go to the course and afterward two months later They say there's a delay because of some So sighing and you're like when does the board? but It's more like from you know radio a matter or ham radio The blocks in the fpga and you know understanding the sort of behavior inside And and having when I actually when I first read the paper the fact that there's a cpu Like a whole cpu like this. It's quite already quite advanced. It's not the basic fpga blocks or something So that's the interesting thing for me. Thank you very much. Thank you very much