 Welcome to the session on 8086 system bus architecture where we are looking for maximum mode configurations. At the end of this session students will be able to describe the maximum mode operation of an 8086 based system. Let us see maximum mode 8086 system. The maximum mode is for medium to large size systems which often includes two or more than two processors. Again if you are looking in this mode there may be a more than one processor in the system configuration and the components in the system are same as minimum mode system. And here the processor derives the status signals to control signals using the status information. Now here we are observing the block diagram of maximum mode system bus configuration where the processor derives the status signal S2, S1 and S0 and our chief called bus controller derives the control signal using the status information. In the maximum mode there may be more than one processor for system configuration. The basic function of the bus controller chief 8288 is to derive control signals like read, write for memory and IO devices and DN, DTA, ABLICAR, ALI etcetera using the information made available by the processor on the status line and the bus controller chief has input lines S2, S1 and S0 and CLOP and the inputs to 8288 are driven by the CPU it derives the output ALI, DN, DTA, ABLICAR, memory write, then IO read, IO write, memory read. The AEN, IOB and CEN pins are specifically useful for multiprocessor system AEN and IOB are generally grounded and the CEN pin is usually tied to plus 5 volt. Now here in the pin diagram of 8086 if you observe the microprocessor 8086 is operated in a maximum mode by strapping its MN oblique MX pin to logic 0. A processor is in maximum mode configuration of 8086 when its MN oblique MX pin is grounded and the maximum mode defines pins 24 to 31 as follows. So a processor is in maximum mode configuration of 8086 when its MN oblique MX pin is grounded or logic 0. The maximum mode defines pins 24 to 31 out of that the very fast pin or the pins QS1, QS0. These two output signal reflects the status of the instruction queue. The status indicates the activity in the queue during the previous clock cycle. So if you are looking in the table the possible signals are 4. So as per the first signal 00 we can observe there is no any operation that means QE is idle for the 01 first byte of an opcode for 10 indicating that QE is empty and for 11 subsequent byte of an opcode. So the second one pin is S2, S1, S0 these three pins or we can say the status signals indicates the type of transfer to be take place during the current bus cycle. And also if you observe in the table the number of possibilities for the status signals are the 8, for the input 00 it indicates the status is interrupt acknowledge, for second one 001 it is IO read, third IO write, for 011 fourth that is halt, for 100 it is instruction phase, for 101 it is memory read, for 110 it is memory write and the last status signal for the possible input 111 it is inactive or passive. So such a 8 different signals or we can say the status are indicated by S0, S1 and S2. Now the next pin is lock this signal indicates that an instruction with a lock prefix is being executed and the bus is not to be used by another post processor. And the next one more important pin is RQ oblique GT, RQ is nothing but request and GT is nothing but grant. So there are the two different pins RQ 0, GT 0 and RQ 1 and GT 1. So in the maximum mode configuration of 8086 hold and HLDA pins are replaced by this request and grant kind of signal. So by using bus request signal another master can request for the system bus and processor communicate that the request is granted to the requesting master by using the grant. Both signal are similar except the RQ 0, GT 0 has a higher priority than RQ 1, GT 1. Here you have a question which bus controller is used in maximum mode configuration of 8086. So please take a pause and write your answer. Your answer is 8288 bus controller is used to provide the signal eliminated from the 8086 by the maximum mode operation. Here you can observe the timing diagram of the memory or IO read cycle without any weight state in a maximum mode of 8086 system. So in figure the status beats S0, S1, S2 are set just prior to the beginning of the bus cycle upon detecting a change from the passive state. The 8288 output upholst on its GT oblique R pin during T1 in T2 the 8288 sets DN equals to 1 thus enabling the trans receiver for memory read operation. It activates memory read cycle also which is maintained until the end of the clock period T4 similar to the memory read cycle which performing the IO read cycle. The control signal IORC is activated instead of memory read cycle the same way. We can observe the timing diagram for the memory write cycle without any weight state for the maximum mode 8086 system. So in figure for a memory write operation memory write is activated from T2 to T4 and memory write is activated from T3 to T4 the status beats S0, S1, S2 remains active until the end of T3 and become passive during T3 to T4. As with the minimum mode if the ready input of the 8086 is not activated before the beginning of T3 and weight states are inserted between T3 and T4. Similar to the memory write cycle while performing the IO write cycle the control signals of IOWC and AIOWC are activated instead of AMWC and memory write or MWTC respectively. And these are my references which I used for our slides. Thank you.