 so this is going to be at least by 2 sessions we will go into details of all kinds of different and then we will see how to use them later on but during the learning of instructions I will give you some sample code also so that you understand how each instruction function and I expect you to try the ARM simulator writing these instructions in that and write out what happens so that you understand when you play with the simulator you understand the instructions better so in today's discussion we will be touching upon data processing class of instructions before that I will touch upon the conditional execution which is a very unique feature of ARM and then we will go on from there there will be another follow up section we will talk about other instructions of ARM so with this we have completed the unit 2 also now we are entering the unit 3 of course so the topics that we are going to cover I will just give you how the ISA the instruction set architecture and the processor variants are mapped okay then at a high level what are the different types of instruction and then we will go into the instruction set of ARM 7 TDMI which follows the ARM V4T ISA remember a processor will be based on some instruction set architecture so that would be different families of processors following a particular ISA so they will have what are the differences among them they though they are implementing the same instruction set they might have different features or hardware modules to enhance the execution of and in the instruction set come in a thing we will be talking about conditional execution and data processing instructions to start with so this is a normal teaching which I introduced earlier so ARM family has this kind of a acronyms used for indicating different features different hardware modules which are supported in a particular processor so when you hear ARM 7 TDMI if you know that this is a 7 X is 7 so it is a ARM 7 family of processors P it is it has a thumb mode which is the this is bit wide instruction execution and D means it has a data debug port that means you will be able to debug the hardware the chip by connecting it to the data data port and your development platform and you can do a debugging, stop, break, apply break points and other things okay so we will talk about this in the now a fragment of the course M means it has got a force multiplied unit and I means that it has got a in circuit emulator macro cell so that you know you will be able to perform break points and stop the code in between the execution of instruction and look at the contents of registers so for doing all this a processor need to support the debugging, online debugging facility so these are the different modules which are available in the ARM 7 TDMI which we are looking at but there are other block modules which were added later on to support different kinds of features the last one yes means that the IP core is synthesizable that means if you remember that I mentioned about hard core and CPU core hard CPU as well as a SOC CPU so this is a SOC core where we will be able to get the IP and then we will get along with the other chip and you could even change the layout of that particular CPU what you have purchased from ARM now how a particular revision of these are all the ISCA revisions okay that means starting from ARM V1 we are currently talking about ARM 7 TDMI which follows this ARM V4T instruction set architecture so there are subsequent improvements to that instruction set architecture and there are different names to that and they are mapped to the ARM processor cores so if the ARM 7 TDMI as well as ARM 9T follows this ISCA whereas ARM 9E and ARM 10 follows V5 ISCA and ARM 11 follows V6 so you could feel you could see that following this ARM V4T there are both ARM 7 and ARM 9 processors that means here in ARM 9 there is a 5 stage pipeline which we talked about that in the last class so the ARM 9T has a 5 stage pipeline following the same architecture ISC instruction set architecture of the ARM TDMI so what does it mean the same instruction set goes through the high stage pipeline so this will ring you a bell that I mentioned in the last class that when a particular instruction while executing it is accessing the R15 of the from the register file it is expected to get a current instruction which is getting executed that address plus 8 because that is what is being called by 7 so ARM 9 also simulates that so in the 5 stage pipeline it would be plus 4 so that difference I said that ARM 9 is emulating the behavior of ARM 7 it is for this purpose because both of them are following the same instruction set architecture and when you are quoting an assembly program or a campaign program from which was meant for 7 TDMI to ARM 9 it should also run without any problem so to do that they were they introduced this emulation of ARM 7 in ARM 9 4 okay so these are the different CPU cores along with their features now we are not going to the details of each one of them but I just highlight you of them see this has no cache into that inside that if there is no MMU or MMU is memory management unit and there is memory spectrum unit so we will be touching upon these features in the later discussions ARM 7 TDMI as such does not have this block hardware block built into the SOC so this follows V40 ASA and it has got a firmware now if you see the later versions the ARM V40 is followed by different other CPU also which has got MMU but they follow V40 and they have a built-in cache also so following the same instruction set architecture they they have no modules hardware modules in terms of memory management unit or a cache and they build the SOC using this ARM core okay so let us see what are the different ARM is between type hello hello someone is talking in the background sorry for the question so let us go into the instruction types of ARM so this is data processing instruction which this class of instructions manipulate data within the processor register okay so in this particular session we will be talking about more on this kind of instruction and then data store instruction as I told you the data processing instructions work on only registers and anything to do with memory is there are separate set of class of instructions which help you in transferring data between memory and processor registers so they are called data load store instruction and program status register instruction as if you remember we spoke a lot about current program status register CPSR so if for any reason we want to know the contents of CPSR and then manipulate them in fact to change the modes from one to the other we need to copy the CPSR value and then change that so to do that there are special instructions which will help you to take the copy of the CPSR and then manipulate it and write it back and software interface instruction this is to call operating system routines okay from the user mode so this will be going to supervisor mode so that there are some instructions for that and branch instruction of course to change the flow of control there are special instructions for them and if you want to use the functions in the CPSR and there are some instructions for that we will go into the details of each of them you start with now let us see what are data processing instructions once data is there if you are manipulating data we have to see what kind of data that we get from the memory okay so again that depends on the way it is stored in the memory so here if you see a particular data at that address one thousand one zero you see that bit zero is here and bit thirty one is here and this is the lower address and this is the higher address now when the LST let us write of the data 32 bit data is stored in the lower address and this is a little ambient so what we are showing the contents of the memory here is a little ambient mode now this is the address how the address is increasing now let us see how different data types are supported by the processor basically it supports six data types to each for 8 bit 16 bit and 10 bit data but if you remember we said that arm registers are all 32 bit value and any operation being done on the 32 bit registers so then where are where is the support for this in the arm it is only when you want to store a load from the memory okay so any data which is in the memory could be of any of this type but once they come into the registers they are extended to 32 bit words okay and internally arm reads are operates on 32 bit value so even if 8 bit value is there in the memory when it comes to the registers it will be extended to 32 bit value now the actual base it could be done based on the type of data which is being read from the memory suppose you are reading a 8 bit value from the memory and its MSB is set that means it is a negative value now when it has to be copied into a register since you are copying the byte from memory it will go into the LSB of the register LS byte of the register and because that byte which you are copying from memory has a MSB bit set that is bit 7 is set that is extended to all the higher bits okay 24 bits of the 32 bit will be made one so it will become a complete 32 bit signed value what happens if an unsigned byte is read it will be extended by zeros so the byte value will remain the same so how does the processor know whether it is using a signed value or unsigned value from the memory processor does not know so only the programmer who has stored the values in the base memory knows whether he is what he is storing he or she is storing the value based on that they have to use the proper instructions while transferring the byte from memory to register based on the instruction it will either the processor will either extend time extended or zero extend the bit so that complete 32 bit value is got in the register and then it can operate on so the data processing the instruction that we are seeing all operate on 32 bit values only the data transfers instructions which help you in accessing the contents of memory support different types of data types or how are they stored an 8 bit value could be anywhere in the memory that means it could be in the lower byte address 0 or byte address ending with 1 or 3 or 3 so based on the lsd bit of the address the particular byte will be picked from the memory and then it will be copied to the ls byte of the register and signed extended or zero extended based on whether user wants the byte to be signed value or unsigned value in the particular signed value or unsigned value now what happens to half words half word can be stored only on 2 byte boundaries what I mean by 2 byte boundary mean the ls byte of the half word half word here means 16 bit byte so ls byte of the half word should be on the even addresses okay it cannot start from this these two cannot be combined as a one half word half word has to be either this which is address now this is 2003 and 2004 is this address so the ls byte of half word can start on 2004 or it can start on 2006 that's an even address so that's about half word now 32 bit 32 bit data types need to start on 4 byte boundaries that means it has to be either on 0 4 or 8 now we can see that the word here starts from 8 it can't start from somewhere in the middle and then go to the higher byte so this this 4 words 4 bytes cannot form a word so when the processor is accessing a word or 32 bit value from memory it will always assume that the lowest 2 bits of the addresses are 0 so it will always read from 0 or 4 or 8 or 12 so the ls or the 2 bits of the addresses will not be considered when it is accessing a 32 bit value so you should know of what we mean by word aligned or 2 byte boundary aligned or a 4 byte of the address only the byte values can remain anywhere and once they are accessed it will become a 32 bit value inside the processor so this is all about data types now let us see now either you have accessed a word or a byte or half word it has come and come come into the register then it has become a 32 bit value now how does it has data processing instructions operate on them that is what we are going to see in this lecture so these instructions manipulate data within register so there are different classification a simple move instruction why move instructions are coming at a data processing instruction because the move instructions which helps in transferring between registers can manipulate the data okay it can manipulate the data using the barrel shifter so that is why we call moving a contents of one register to other register also as a data processing instruction now there could be arithmetic operation like addition, subtraction and logical operations like AND or OR or exclusive OR comparison instruction which compares to register values and then say whether it is equal or less than or greater than using those condition flags and multiply instructions multiply the contents of the register now if you remember there are three operands that you could mention in a typical instruction r and rm and rd r and rm are two operands and then one of the operations are done and then it is copied into rd which is the destination register so all these values are all internal registers which are called gender purpose registers which is one among 15 registers that you have which are all are always 32 bits right now what are the difference between the two operands the rn operands directly come into a lv whereas the rm operand the second operand will go through the barrel shifter based on the type of input okay now let us see now how the data processing instruction affects or does not affect the cpsr if you are familiar with 8086 instruction set you know that whenever you perform any arithmetic update or logical operations based on the content of the result the flags are always affected whereas in ARM it is option i will explain how it is being made option except for one set type of input which are comparing if you know the compare instruction is meant for say whether a particular two particular values two values are same or more or less so that means they have to affect the cpsr this is current program status register so that based on the flag set then control flow can be different control flows can be taken by the instruction so ARM ASA gives a special observation for comparison instruction which always updates the flag now you may wonder how other instructions are differentiated or how a user and a programmer could say whether a particular instruction can affect the cpsr or not this is the way it is done suppose add is an instruction which you want to use in the a typical way it is written is rd comes first that is a destination register this is a convention ARM follows okay different assembly programming of the programs of different processes all are different convention so you should be very familiar with what is a great ARM interface the values when you write like this passenger interface it has r1 and r2 are added and it is copied into rd now you know that when two numbers are added it is going to impact all the flags of the condition flags of the cpsr register what are the conditions flag carry flag zero flag negative flag or also flag now when you write a code saying that add or zero all in command so it doesn't change the values of cpsr though this addition can do it but it is disabled when the user has written just an add but suppose user has said add yes that means they the user wants whatever arithmetic this particular instruction is doing and if it impacts the cpsr that should be reflected in the cpsr thing i will give an example suppose you are adding two zero values suppose r1 is having zero and r2 is having zero if you add these two numbers what you get you get a value zero in r0 now when the result is a zero which flag should be set naturally zero flag should be set but if yes is not there in the instruction add yes was not mentioned if it has only this even though r0 has a zero content and it is supposed to affect the zero flag this instruction will not change the value what i mean by that suppose prior to this instruction execution if the zero flag was set or it was clear it doesn't get changed because of executing this instruction so the old values of cpsr remains the same but if add yes is there this zero adding two zero values and resulting a zero returning to r0 reflects the cpsr it is reflected in the cpsr flag so zero flag gets set and negative flag of course it has to be zero because msg of this result is zero and overflow flag there is no overflow here there is no carry here so all of them will be clear except for zero flag all the flags will be here so that will be the state of this after the execution of this instruction so i hope you understand that when you mention a yes after the instruction of course this is a of course which adds if you mention yes that means this instruction is allowed to change the values of cpsr now how they are affected if it's not only those sort of any arithmetic operation even logical operation or rotate or move or logical shift or anything can affect the flag so if all of them will affect the flag only when you have a yes associated with those instructions so this is the way they affect these are the flags they get impacted if they get impacted anyway we will talk about those logical operations in detail and then we will see how the different flags are getting impacted because of those this is very important concept and this is very unique of form instruction set architecture so i want to understand this and try out this in the simulator so that you see those flags getting changed now there is another concept which i am going to about conditional execution this is also very but unique about unique in our so you have to understand the difference between this and the previous thing what i mentioned what i mean by conditional execution is each instruction doesn't matter whether it is a compare or add or mandatory or and operation entry every instruction format i told you that instruction in a binary format stored in the memory and all instructions are of 32 bit so above this 32 bit value different bits in those instructions talk about what type of instruction it is what parameters operant it is taking where it is supposed to write the results all those things are there let us not bother about those speeds now i am talking about the highest n must be bits of the instruction the four bits every instruction is coded with a conditional bits which are four bits wide and given here this is called r4 okay now what does it mean inside the r4 these three four bits mean different things that means if it is set 00 it is a for eq eq is a mnemonic that you will be mentioning in the instruction i will give you an example so that you will understand it better actually what does eq means the zero flag is set now suppose you have an instruction let us take an example of add eq and then you say add eq okay r0 comma r1 comma r2 let me write it and then show you what is it mean suppose if you return an instruction sorry okay like this instead of just mentioning our add you said that add eq then r0 comma r1 comma r2 what does it mean it will be executed only when the ctsr value that is that is set okay only when the zero flag is set for due to some other operation before okay because of that the zero flag was affected and it is in a set condition then this instruction will be executed now what happens you have to add eq r0 comma r1 comma r2 but zero flag is not set at that moment when this instruction getting executed it is that process is verified whether the zero flag of the condition flag is set or not if it is not set this instruction is ignored that means this addition is not performed so this is what is called condition and execution okay i hope you understand this so the eq is one of the example it could be any of them okay it could write add nb r0 comma r1 comma r2 that means this instruction is sitting there in the program it will never get executed because it does not take any flag never do not okay but what i am saying here is this actually it should never be using this particular option assume that you have used any of this maybe you have used the le option add le it will get executed only when this condition is true okay either that is your zero flag is set or n is not equal to b the you know in a negative flag is not so equal to post flow flag they are not same then this instruction will be executed similarly there are so many ways you could say that a particular instruction has to be executed or not now what is this a l this is about always what i mean when an instruction is coded like this whatever may be the state of this flag this instruction will get executed now you could write add r0 comma r1 comma r2 and they saying r0 r1 r2 for an example it could be any general particular so when you just say add it means similar to add a that means when you write this add that instruction will get always executed or you could have even say a f so when you say add and then instruction is not having any of this mnemonic the conditional bits in that instruction will be set to 1 1 1 okay so i hope you understand that in the earlier case which will show that an x indicates whether a particular instruction can impact the cpsr or not okay we said every instruction can decide whether i can you know affect the values of cpsr or not along with this if you say add eq and f then what happens is whether this execution itself will be based on the value of the current cpsr value and then if it suppose if it if it is allowed to execute you know executed then whether it can impact the flags or not so these two are the different conditions so for a particular instruction both can be mentioned you could say that whether this instruction if it is executed can it impact the case of flag and then you can also say whether a instruction need to be executed based on some condition so both can be there in simply we will we will see some examples so that you understand the different bits in these two so this is all about conditional execution let us see few examples which will make that thing clear to you though i have not introduced assembly program so far to you don't bother about too much to understand each of them i will explain you what it means suppose you have a stream of instruction like this compare means it compares these two values the content of r0 with a constant file which is coming along with instruction and then if it is same i told you that compare instruction law always impact the cpsr so it is same it would have set the zero flag now branch on eq i told you eq means zero is set so branch won't even give you a forget it so if step suppose these two values are same you jump to bypass okay as you jump to not you or me but the process becomes to be bypass now what happens if suppose zero flag is not set then these two instructions get executed and then it comes to this one this particular instruction now how does it match to this actually from here we go so if suppose r0 is not equal to 5 the programmer wants to execute these 10 10 now instruction so if it is not equal okay you will not bypass this that means you will execute this so what does it do these two are from the same job of what is mentioned in this scenario here and then it comes here now this is the way typically any processor would be the assembly would be written now because of this conditional execution the code provided by arm you could do this with a simple instruction like this compare this because why there is no s here it doesn't matter because compare always whether you put s or not compare always changes the value of cpsr based on the outcome of this instruction so if these two values are not same zero flag would have been clear now from here add any any means was not equal to not equal to it suppose zero flag is not set that means it is clear then you execute this again subtract any that means you subtract the r1 minus r2 and then attend the value to that back to r1 provided that the zero flag is clear so this is the way programming data using this conditional execution support towards the arm so this is what I am explaining here so what is the advantage of this if you look at the number of words occupied by these three instructions and only two instructions here perform the same job that means your code density is better in this case and then there is one more inherent advantage of doing it this way which will I explain to you in coming slides so code density included here and it also says it is efficient in terms of execution time because of pipeline flow is not disturbed you have to remember whenever you see any instruction at least we are talking about arm 78 minutes so three state pipeline now what happens when branch execution is encountered and assume this was a jump that means they were not equal and it has to go to the body form now it happens in the this when does this instruction that executed in the third stage of the pipeline which is of execution already subsequent instructions have been fetched okay this has been fetched and decoded and this instruction has been fetched they are all in the pipeline waiting to be executed now it encounters that oh this bypass condition is true okay these two values are same though now the instruction flow should jump to this platform that means what the pipeline has to be flushed and the first instruction fetch has to be initiated and this instruction whatever may be has to come from the memory after this third cycle and it will take two more cycles to go through the threads and decode stages and then this instruction will get executed after three stages you could you you can see that it will be delayed this execution of this instruction will be delayed by two more cycles if we were not using the conditional integration now let us see the scenario here now compare assume the same thing happens here okay compare as resulted in may be equal that means what these two instructions need not be executed because they are not equal but already these instructions are in the pipeline so when this compare instruction was executed this is in the report stage and this is in the fetch stage so what will happen is the flow will continue and that these two will come to the execute stage and but it may not be executed because this condition is not true so it will just be a no off so it will be skipped through this will also go through now the advantage is that within two cycles the instruction which is there to the executant next will be in the pipeline so there will be additional two cycles of delay because of the term so that is why here we say that the conditional execution is efficient in terms of the execution time also apart from four density four density you can see that only three instructions here whereas here we have four instructions to do the same now so four density is better here and execution time is also better because of this particular feedback supported by ARM but there are some limitation or side effects to this which we will talk about in the subsequent so this is an unusual feature of ARM IP conditional codes are and this I am summarizing it so conditional codes what we talk about are these four slags so most of the data property instructions do affect these slags for some one program plus so almost all our instructions contain a code the conditional field which I showed you the first four bits of the instruction is always to talk about which whether the instruction is to be executed based on the particular combination of slags if it is 1110 it means execute that slag it will give that instruction it will give the value of whatever may be the value of other 14 types of the 14 values of those conditional fields gives you different conditions which I showed you in the table so conditional execution is supported in all the in almost all instructions which improves the throughput I explained you in the previous slide so if the conditional code flag indicates that the corresponding condition is true then that instruction starts executing otherwise so what happens is when that instruction that comes to this execute screen execution stage it will check the code flag and if it is matches to the condition then it will execute normally okay otherwise it will be a no off no off means it is just skipped so nothing happens one cycle gets wasted but no changes to the cpsr or any other register content of the processor now what are the equality conditions as per the table it could be equal or non-equal or less than less than time times values okay and accordingly a particular condition is definitely time set so one more if you look at in detail the alternate conditional slag or you know they give you the alternate condition one is that is clear eq is that is clear set and not equal to z is clear so like that every flag is alternating the conditions are alternating between the codes that is the way they have ordered okay there is nothing about it just any information for you okay now what are the benefits of execution I mentioned it to you is better than using conditional branches because configuration branches take the control of execution to a different instruction by changing the value of pc and describing the execution pipeline and it needs to crash at least minimum two instructions which are in the pipeline and one two instruction because I am talking about arm seven which is three-stage pipeline okay so always whenever you talk about instructions please remember the pipeline is that should be in your back of your mind so that you you understand that when an instruction is executed it is in the execution stage of the pipeline and the next two instructions in the memory are already into the pipeline one in the decode stage and the other one is in the six stage inside the pipeline okay so whenever that particular branch condition is true when the those two instruction result in the pipeline needs to be flashed and the new instruction has to be flashed which will involve more time and and I told you that how having conditional execution improves the performance because no there is no question of pipeline and the density is better so density is better because this particular condition is encoded within the force based on the instruction itself let us take an example I want you to when you are listening to the lecture I want you to read the lecture and try to understand yourself what is happening here all of you are aware of a deep programming convention here but how is it mapped and what does it mean because if you try to understand yourself then my explanation will add to that and in case if you have any misunderstanding that is it gets clear okay good so you have talk about it and I hope you have understood what is happening but I will explain you what is happening here assume the R5 is mapped to the the valuable value this value could be a local variable or a global variable it should have been in the memory either in the stack area or a data area now how has it come to R5 some instructions before it has already copied using a load instruction from this value from memory to a register which happens to be R5 and where does this 100 come from it has come from the instruction itself because when the assembler or the compiler is because it has to be a compiler because it is supposed to be a C code so the C compiler has seen this content and then it has generated the compare instruction with 100 embedded interval because there are some restrictions in how big this constant could be and what are the values it could have so those things let us not bother now but assume that it has been interpreted and this constant is here in the instruction now what does it do it compares the value with the 100 if it happens to be equal 0 class would have been set if it is not this compare instruction would have made the 0 class to be clear now will this impact R5 content no compare instruction that is a that is a subtraction of this value with the either immediate or another registered value and then only takes the result of that and impacts the CPSR and doesn't change the value of any of the operands so R5 value is not impacted anyway you will know more about this but just for a continuity sake i am saying that it by executing this instruction it has impacted the CPSR values conditional class values not other values now it comes here add so add is there only when 0 class is set because we have set add equal so it will perform this doubt now what are the R1 and R2 they are supposed to be have been mapped to this variables and it gets added and then the result is put into R0 which is i now suppose 0 class is not set now this will not be executed it will fall through but this instruction says it needs to be executed only when they are not equal that means when the 0 class is clear i want this instruction to be executed so the else what will be executed so based on the 0 class set in this situation instruction these two instruction one of them will be executed okay so it is implicit in the instruction which are generated by the compiler now let me ask you another question here suppose if i put a s here this is correct suppose if i put s what does it mean we want this instruction to be executed when eq when 0 class is already set i want this to be executed but i want this instruction also to impact the values of CPSR now what happens it will override the value which was there because of this instruction it may change the 0 class now because of that this may also be executed if this was having an s here so which would be different from what was intended by the programmer so here you have to remember that suppose you are putting a sequence of instruction which are based on some conditions of CPSR these instructions will not impact the CPSR values see execution of this instruction is controlled by the CPSR and the decision on whether this instruction can impact the CPSR is based on where s you put here or not so you have to make sure that they do not impact the CPSR values because they are not intended here in this particular situation so you should remember that whenever if you are writing an assembly program but compiler may not do that job okay now let us see another example i again expect you to please the lecturer and look at what is the code here and what is being generated here try to understand what is happening which will give a better clarity on how to understand this conditional execution of ARM processor okay welcome back you hope you have already discussed among yourself or with your neighbor what is happening now you see there is no as per the three convention then this is true suppose then only the Boolean and as per the instruction and the standard this will be evaluated okay that is the way the compiler is supposed to generate code for so if a is equal to b is true then evaluate this condition that means you compare c and b and if this also happens to be true then incrementally this is what the original C programmer intended to do now the compiler has generated this code is it doing the doing what the programmer wanted here see here compare r0 with r1 it is very obvious that r0 and r1 correspond to a and b now you see compare instruction it means that it is supposed to affect the cpsr so based on the outcome it will impact the cpsr now if they are saying 0 flag will have been set now it will come here this compare instruction is again one more compare instruction is coming but increase this is the conditional execution that means if the earlier comparison or earlier operation as the result is in 0 flag being set then you execute this instruction that is true right if it is resulting in a equal condition then only the comparison of c and b should be done so so far so good now in the previous slide i told you within this conditional execution you should not put any instruction which will impact the cpsr now we have used cmp here which is a compare instruction whether you put an s here or not this is going to impact the cpsr so whatever may be the state of the compare the cpsr values based on this instruction is going to be overwritten by this comparison now but is it true in this scenario is it correct in this scenario yes because you want this condition also to be available for deciding on whether the e plus plus should be done or not so compare eq will compare the c and b values and then set the which it may be set the 0 flag or it may clear the 0 flag and if it happens to be same then 0 flag would have been set that will make this add to execute because add eq is there so this is executed based on the cpsr contents of this compare instruction so that is what is entered in the C program 2 so this is the way it is very executed so if you understand this you must be very clear about where to use conditional execution and how to use and what are the precautions need to be taken because this is a very unique way of using it okay I will say any use of conditional execution so this is what is explained here sorry now how the first comparison point unequal happens the second is skip so if this is suppose this is false now this will be skipped now what happens when this is skipped this will also be skipped so if suppose a is not equal to b it will not go into this condition at all as the c programming convention right now you want to see whether it happens here compare it is not same so eq condition so this is not executed so now 0 flag continues to be clear so because of that even this will not be executed so it will go to the follow up instruction following instruction which is below the cpsr instruction okay so it satisfies both the condition whether both being same or only one being same or the first one being gone so everything is taken care of by this particular setup assembly instruction I hope you understand this because okay so some more details about condition execution so there is a general rule saying that whenever conditional sequence is there you should have three instructions are fewer why we say three instructions because where will you use a conditional execution only when you want to avoid using a branch based on the condition you you put the same condition in the subsequent instructions to take care of avoiding branch but if the instruction that you want to put more than three then the benefit of not using the branch is lost so you could as well use the branch instruction instead of more instructions being put with a conditional execution okay because I told you the execution advantage you get only when there are fewer instructions to be executed within the conditional so if you suppose entire if you have more instructions in the program then compiler would not generate the condition engine it would generate a branch because you do not get the benefit of the pipeline advantage so because typically a branch instruction takes three cycles effectively you do not want conditional execution instructions to be more than three and the advantage you get by avoiding branch is lost so you should go for using the branch instruction rather than going for conditional execution okay then you have to put too many instructions inside the for based on possible condition and one more thing also you should remember whatever instruction you put inside the condition they should not have a side effect though in the previous example we saw some comparison section within the conditional execution because intended but if suppose you put some instructions that are not intended to affect the CPSI you may get a different instruction so you have to be very careful when you are using the conditional execution in the assembly but you should understand what happens so that you fully understand how to write a assembly code here so apart from that one more point you should remember also that whether to use a conditional execution or not you can decide based on the dynamic code behavior what I mean by dynamic code behavior suppose when you are comparing two values if most of the time they are supposed to be not same or they are supposed to be equal based on that you can take a decision because you know which part of the control code is going to be executed more often and then you can try to optimize that part of the code so these are all the algorithms or optimization techniques the compiler always do based on the different history or you know based on the program as input but if you are writing assembly code you need to keep that in mind because you know the way the assembly flow is going to be and accordingly you can choose whether to use the conditional execution or not so with this we have come to an end of what we learn from conditional execution and what are the advantages of them now let us see how the data processing section flow through the data class data class of the ARM 7 code now you remember this diagram value we have seen okay you should remember the registered files have this number of codes because if you have it in your back of the mind you will be able to appreciate very well what is happening when operating between the various code so what I mean by these two you can always read two parameters operands or the same time you could write the processor could write R15 also in the registered file okay in the same way let us see an example before that I want to just give you a what is the barrel shift you do where that the barrel shift appears in the original pipeline it is here so RN the operand that you pass or that you mention in the instruction when you say add or 0 comma or 1 comma or 2 what is RN the the second the first operand that is R1 which is coming on this bus and R2 will be coming on DBET so in add instruction R0 R1 comma R2 when you say R0 will be read from the register time directly but R2 will be read through this and then the R2 can come through the barrel shift now you can mention some barrel shifted operation what I mean by barrel shift right or whatever you could do it on the second operand before that just added with the first operand so in a simple R0 comma R1 comma R2 the R2 does not have any barrel shift operation associated with that so it just pass through it otherwise it will be getting modified here and then coming into all that happening in a single cycle which I explained to you in the previous lecture okay now what does the barrel shift to do RM it takes in if that the barrel shifting operation if it has to be done based on the instruction and then it also start the AMU as to parameter so both are 32 bit wide that is to view all the register parameters and all the operands are 32 bit wide and barrel shifter can perform any of the automatic operation and remember that it is it all happens within the single cycle so if this improves the performance of the ARM processor now let us see what are move instruction move instruction is basically to move from laser between two registers or an immediate value into register that means you have one operand which is always a destination register and other one okay being already called operand as only the operation that you often want to know so here in this case it is a single operand because destination is not considered to be an option so it has to move in the destination register either the value can come from the register or it could be a textbook input or a textbook value which is coming from the instruction okay now what is the difference between move and move and move ngm is that means whatever may be the value which is coming here it could be from register or immediate value it will be reverse that means you know you will do a bit reverse operation on all the bits and then copy that value so you will be copying the bit from the operand and then copying into a destination register that is what is this move ngm that okay so these two are the simple move operator move instruction that will be an r instruction one just directly copies the value into a register register other one that is a a totaling of all the bit position if it is 0 it makes 1 r1 it makes 0 and then it reverses the bit and then copies so this is the similar operand instruction as mentioned to you the n could be either an operand or the ngm value what is ngm instruction it could be a register or immediate value it gets copied okay it will rd do not worry about this set of logical operations it varies with that in the next session i will be going into details of maybe one of them so i thought of showing you few examples see suppose before this instruction gets executed the pre condition the condition of the values of these registers left assume they were 5 and 8 some more r7 comma r5 that is r5 is moved into r7 okay that is equal to r7 equal to r3 now what is the value of r5 it is 5 so that is moving to r7 so that is what happens after this input means now one more example this this is the way you can mention the barrage system operation that is this shift this lsn means logical shift left it actually means you are moving the bit positions of r5 okay it always replace the next register here to this operand so r5 is contents that is a little value content in the r5 is shifted left and if it is done logical shift means in the msv part it will be filled with 0 and how many bits it is shifted to whose position so um um so because of that what happens is this value gets changed and you get the maybe actually when you are shifting it to left what happens is the bit positions i will give you an example so that you understand what i mean suppose you have 1 0 1 okay this is the 1 0 1 sorry about the writing and the rest of the bits are 0 now you are doing a left shift that means you are moving in this direction the bits in the r5 now what will happen this bits this will become 1 0 1 0 1 0 and 0 now what happens this was originally 4 this means you were 4 and then this one is 5 so 4 plus 1 this is a 5 value 5 becomes this is 16 plus 4 20 so effectively the shifted value r5 that is you know after this 5 is shifted you will have 20 in it and that is written into r7 so you get 20 as r7 here okay so this is the way um you can do it so if you map this with the diagram you see that the second parameter of when this r5 is coming on the beam bus and then it goes through the virus filter and then i told you that move operation also does from logical operations with the data so it gets done and then that value is copy easily so move also does some processing with the data one of the operands is operator upon using the virus filter okay so now some more examples using this nvn assume that r1 was having a 0 value after mvn what happens i told you that the 32 bit value in this operand is all always that means all zeros will become 1 and that that value gets written into r1 so you will get this value in r1 so who does this struggling of this immediate value the virus filter because one of the operands can come through the virus filter so it gets changed and then that value goes into r1 now another example suppose if you have mvn with the no immediate value 0 1 is getting into r1 this when it is started the lsd bit will become 0 that when you get a e here 1110 and then that is what there will be 1 so this instruction i what i showed you was with the immediate value okay immediate means this constant this value is coming along with the instruction itself not comma another register it is only written into this register r1 okay now let us see this is the mvn operation how the toggling will happen okay let us see now how can you map this instruction with the data flow happening here suppose a register to register move was happening now this is one of the register which is move you know that is to be move to another rg when you say move rn comma rg a simple example where this rn comes directly and there is no shift operation on that so this particular thing will not be happening so this rn will directly fall to the a and u and goes into rd this value is actually write from rg suppose move r0 comma r1 r1 is written is read from the register 5 and then it is written into r0 back so this all happening now one is good cycle now what is happening on this side this is the pc the r15 getting incremental and then the next instruction getting executed so if you remember the pipeline when a particular instruction getting executed there is a parallel accessing of instructions from the memory also is happening so for that a new address has to be generated and then put on the data bus sorry address bus and then the instruction will come through data bus and get written into the pc or the address will be written into pc and the instruction will come in and then gets decoded by the pipeline so this is the way a register to register transfer happens and if there is a LL LNOS this operation is done then the barrel shifter will come into play and that will go through this and then the data will be written back into the register so move operation or any the data for activity is always where the operands are always from register or it could be in immediate value suppose if immediate value is coming it has to come through the instruction pipeline I will show you that right so this is the way instruction gets executed inside the code now assume that there is an immediate value coming what I may I if you remember the previous example I showed you you have move in the end and then you are saying LSL hash to some shift operation with a your hash 02 that 0x2 is an immediate constant which has come with an instruction now how it gets entered into the instruction here because if you remember different status have instruction pipeline register which pass on the values so when this move instruction with the constant was fetched it was along with the instruction that constant also came so it pass on through the decode stage and it is available and it is required for the execution stage because that constant has to flow through this barrel shifter to be operating on the operands or that to be written back into the register so how is it may available through the instruction pipeline register because I told you that control and data information of instruction when they pass from one pipeline stage to other pipeline they pass through the pipeline register and they come into the execution stage at the appropriate time when it is required for the instruction execution so that immediate constant comes through this which happens to be a 8 bit value which is encoded into the instruction and it is required for the barrel shifter and another operand is also taken from the register and then the shift operation is performed on it and then it is moved back into rd register which is mentioned in the register in the instruction so how this control signal and choosing a particular registers are done it is based on the decode stage it generates some control signal which are also coming through the pipeline register and the data part is set up based on the particular type of instruction okay so I hope you understand this before we end the session let us see few examples so that you this concept of conditional execution and the yes flag gets into your mind here analyze this move yes please remember move also can impact the cps values because it is doing some asr operation and then the value what is written into r1 is a result of this instruction so if it suppose if it is moving here a zero content which is stored in r2 is moved into r1 and you will mention it as move yes r1 happens to be all zeros so zero flag will be set so this instruction is supposed to impact the cps value so conditional flags will be affected based on this instruction okay now what is move eq this instruction is suppose you this instruction follows this instruction and you will allow this move as move instruction to impact the cps so based on that value of zero flag this will be executed if that happens to be zero flag is set then it will be executed otherwise it will not be executed at all that means what this move of r2 to r1 will not happen the r2 value will will be the same irrespective of whether moving happens or not r2 is not impacted but r1 will remain the same if this was not executed and this execution depends on what has happened in the previous instruction if the flag was there so remember it may not be the impact of the previous instruction whichever instruction executed earlier if there was whatever the status of the zero flag or the whatever you know conditional flag based on that condition this instruction is executed so if at this moment when this instruction is you know end of the execution stage if zero flag was set this will be executed otherwise it will be ignored now move here in the end also can be appended with any that means this will be executing only when the zero flag is here at this moment okay when you say at this moment when this instruction gets executed in the execution stage of the pipeline if zero flag happens to be here then it will know negate the values in r4 and move it into r otherwise it will not do enough now it is an interesting combination okay move yes is used sometimes this this combines two things together that means for the for a moment here only see in here this whole instruction will be executed when zero flag is set at this time okay now okay the decision is taken okay zero assume that zero flag is set and this instruction has to be executed now it has the option when this instruction is executed at the end of this instruction execution whether can it impact the cpsr flags or not that decision is taken based on this presence of s now because s is here if zero flag was set prior to the execution of this instruction this will be executed and based on the outcome of this instruction the cpsr flag will be set now so you are combining both here okay so you have a flexibility and freedom to put any combinations to achieve what you want in your code so this is the beauty of ARM instruction set and when you start writing code and when you see the behavior of the different cpsr values and the register content you will start enjoying writing more and more of actual code i want you people to try these kinds of instructions now having learned move and move and i want you to use the ARM simulator and try different combinations and understand what happens to the register because that simulator gives you a clear way of showing which are the registers or cpsr impacted because of a particular execution of instruction so whenever you see some values in red that means that because of the execution of the instruction these values are impacted or changed so you can understand this whole lot of thing by trying more different instructions in the assembly simulator instruction simulator what you have please try out and enjoy writing assembly okay so with this we are coming to the end of this session and we covered these are following features condition execution and move and family and in particular i want you people to try out these instructions and understand it fully so that when some more complex instructions are introduced you are already familiar with this and you will be able to understand them so spending a lot of time with the simulator so much and i tell you once you start understanding what is happening at the register level under a flag you will start enjoying writing more and more assembly and this is a very niche area where you can get into any job where you are expected to write operating system code or any of the embedded applications and a very efficient assembly code which is working very close to the processor assembly instruction execution and writing assembly instructions is a must so if you are familiar with ARM instruction set and you are able to write a very good assembly program of ARM code you will be able to understand any other processor and you will be able to write very good assembly code and you will become an expert to the embedded so we show all the best and these are the books as we shall refer and see you in the next class and after i have tried all the impressions that we thought in the class i hope you enjoyed this session see you in the next session have a nice day bye bye