 Hello everyone, myself Prithviraj Thambe working as an assistant professor in the Department of Electronics Engineering at Valgin Institute of Technology-Solopor. Let us today learn programmable array logic. So at the end of this video, students can examine the general structure of programmable array logic and they can also implement simple Boolean functions using PAL. So what is PAL? PAL is a combinational programmable logic device and integrated circuit with a programmable AND array and a fixed OR array. So PAL provides AND OR SOP implementation. Now let us learn the structure of PAL. So you have input lines which are connected to programmable AND array through buffer and inverter stage. So output of AND arrays which are the product terms are again connected to fixed OR arrays and output of these OR arrays are again made available for the final usage through these last stage of buffer and inverters. So the point to be noted here is AND array is programmable whereas OR array is fixed. Inputs to the OR array are fixed you cannot modify them but whereas in AND array you can program the inputs which you can apply to the AND array. So let us recall so with the programmable AND array with N number of input variables and their complements multi-input AND gates can produce a maximum yes 2 raise to N number of AND terms. The point here you can note down which is important in PLDs the number of AND terms or the number of AND gates in the AND array stage is far less than the N variable mean terms that is 2 raise to N. So the output of these programmable AND arrays are again applied or connected to fixed OR arrays and you can use the outputs of these OR arrays as a realization of set of outputs in the form of SOP. So here you will see that inputs to the OR arrays are fixed you cannot modify them. So how to use this PL for the implementation of simple Boolean functions. So here are some points you can note down as discussed in the previous slides the number of product terms that is AND gates are limited those are not always 2 to the N. So a set of Boolean expressions need to be minimized so that the number of product terms never exceeds the limit set by these AND gates which are in the AND array of PL. So the realization of a set of Boolean function is totally based on product terms not necessarily mean terms and fuses are then programmed depending upon these product terms. So basically realization is purely SOP expressions. Now let us implement a simple Boolean function through this example. So here we have 3 variable function f1 and the mean terms are provided here are 1 4 5 and 7. So here instead of using mean terms as it is I will first minimize these mean terms minimize this function using one of the minimization method which is KMAP. So after placing these mean terms in the KMAP I have formed 3 groups G1, G2, G3 and I can write the function f1 is equal to AC plus B bar C plus AB bar. So AC is the group 1 term, B bar C is group 2 term and AB bar is group 3 term. Let us take again one more function f2 which is again a 3 variable function which is summation of the mean terms 0 1 3 5 and 7. Again I am using here KMAP for the minimization. So after putting the mean terms in the KMAP I found 2 groups G1 and G2 for group 1 the expression is C and for group 2 the AND term or product term is A bar B bar. So let us implement these 2 functions using PAL. So this is the implementation diagram where you can observe the connections. So first of all observe here AND arrays are programmable. So you will see here cross at each section where you want connection. Whereas in the OR array you will observe these connections are fixed. So dark dot is drawn at the section meaning is you cannot modify these connections these are fixed connections. Now to implement f1 which is AC plus B bar C plus AB bar so you required 3 AND gates. So I will use these first 3 AND gates for f1. So for the first AND gate inputs are A and C so I will keep fuses of buffer A and buffer C and I will blow all the other fuses corresponding to A bar B bar and C bar. So after programming I am having only here 2 connections for A and C. So this first AND gate output is nothing but AC. Next second AND gate the second AND term is here B bar C. So here I will keep the fuses of B bar and C as it is where I will blow all the remaining fuses corresponding to the remaining input. So the output of the second AND gate is nothing but B bar C. Third AND term AB bar so for AB bar I am connecting output of a buffer and output of inverter for inputs AB respectively. I will blow all the fuses corresponding to the remaining inputs. So these 2 fuses are intact so the inputs to this third AND gate are AB bar. So these 3 AND terms are ordered together to form function f1. Similarly for function 2 which is C plus A bar B. So here first AND term is nothing but this C variable. So for the first AND gate for f2 I am going to keep C buffer output as it is or fuse as it is and I will blow all the remaining fuses corresponding to remaining input terminals. So the output of this fourth AND gate is C. The second AND term is A bar B bar. So for this term I am using fifth AND gate. So only 2 fuses will remain intact and all other fuses will be blown to achieve output of this fifth AND gate as A bar B bar. So you can observe here for the last AND gate sixth all the fuses are blown because we are not using this gate. So for f2 we are going to only OR 2 AND gates outputs which is C plus A bar B bar. So this is how you can implement simple Boolean functions using programmable array logic devices. To read further you can refer these textbooks. Thank you.