 So, we now look at the, what is the last part. So, in the last section we saw the compile command and its option, how do we have a different compile strategy, how do we need to compile multiple instances and so on. So, now, synthesis is done, now our job is going to show that the results are in line with our expectation, we will see how to report, how to take for some design problem although this step may not be the last one, it should be somewhere between, so that too two things to reporting and checking, first is to check whether the design is good for system, it will come somewhere yes. So, just after reading the design, we should build some steps, we should do some reporting, how to make sure that the line is good for system, it does not have multiple firewalls and any unconnected input, so and so on. Then after synthesis, we should again check the design for system, we will look at how to report area, how to report time, how to report the complete summary of the design, so we will see all those commands that we will also see how to save the design database and what does this design database contain and what are the different format supported and so on. So, let us look at the slope, the analysis of slope, so before even going to the optimization, now optimization we mean reporting between the high command, we should verify constraints and attributes, constraints comprise of the clock definition, input delay, output delay, attributes are the max transition, max cap and so on. We should check design consistency, we will see what we can do. Then during optimization, design compiler will throw up some messages, it will tell at, it will iteratively tell us that what is the cost function of each of the steps it will do, design will optimization, it will do design optimization, it will do design based system, it will do some media optimization, so at least in every stage of tools, it will tell us what is the cost function of attributes working. For example, if it is working in the area figure, you will see the area figure inducing, now that is a very good metric of how good area constraints will be for the design, we will see that how to customize that and how to deal with that on that. Then after optimization, we have to make sure that our timing and first of all the deactivation constraints are there, then we have to verify timing. There is a design compiler user guide which has a lot of, so it lays down all the commands, it is not possible to power all the commands on top for doing this course. So we will focus on the more important one, the more famous commands that are more effective, and there are a lot of other commands which you can go through in the day. So first thing is, we have already talked about the reportless command, so we should use that reportless command to make sure that the library we are using is good. It has, if you are planning to use all the commands, if not then what is your source of all the commands? Does it have max function in that? So this is one way of doing that, but then there is one more good way, one more effective way of doing it, is by using the compiler, so the compiler command will use a lot of attributes that are present in the library. Now what happens if it doesn't find some more? Does it make some assumptions? So it will make some assumptions and it will move ahead. So this command compile is the only option. It will report the potential problem that could cause compiler to be stopped or to make some assumptions which might not be achieved. So this command is more useful for some advanced features of the design compiler, like design compiler, graphical design compiler, the tool feature for design compiler, which meets in the flow plan also. So it does taking some physical data. So this command is very useful for that. Somewhat less useful for the normal compiler So but still you could try and run that it will move to max 50W report. So I will just list down the most obvious thing that it reports. It will tell if there are any multiple logic libraries there is a problem in this category. Let us say you have biometrics loaded libraries from two different versions or two different connection libraries from different windows or whatever and what is the name class? Nothing. There are two versions of an end to send to input end gate. What happens? Now design compiler, they are not moving. Design compiler would want to make sure that it is using the correct one. So it will only point to the relevant some of the variables. So it will report that if you have such a problem. It will report some discrepancy if you have multiple physical libraries don't worry about physical libraries physical library is that it is related to the physical. So the physical library apart from the language it will also have the external governance and so on. So it is not in the scope of this course. It will tell again it will tell about don't have any particular model don't worry about this also. It will tell about don't have any information it will be don't have any information. So again most of the checks it will do are with respect to the physical data the don't have any data which will be used in physical scope but still it will give some information about if there is some other attribute system in the library you could try running that and you will be able to do that. So the recommendation is to execute the compiler with the same set of options that were used when we used the check only commands. So for example as I mentioned that you could do a basic you could start synthesis to do a trial synthesis you could work on the synthesis without scan and without boundary optimization. The command would be compile itra manuscript boundary optimization etc. So if the same set of options we should do the check only. So that because the checks are formed are with respect to those options. So just try doing that I haven't myself tried a lot of I remember only I don't use it very often but it's a good thing that we could start it. Then now we talked about checking the design for problem even before going to compile check design is a command that will help us in doing that it will do to check the consistency consistency means a lot of things combination of a lot of things it means that there are no intentionally unconnected code there could be intentionally unconnected code but then you should know so it will give you a report and duty of the designer to make sure that whatever it shows that you understand import of output code are actually by design and not by design so many times what designers will do they will enforce some code and not do them for the first version they may be used in the other world in the subsequent versions of design so either they will leave it unconnected or they will file it off so they will file it on the output or run on the output so it gives you a report of those codes no search with input or output and this is more than this which for which the inputs and outputs and outputs it is not it is highly it is incorrect in fact let's say I am using a standard set directly in my design I am using an AND gate or an OR gate leave one of the input it is a problem it is an error in no scenario I should do that design compiler will use some assumption to tie off this code either it will tie off this code or it will remove this gate so for example in AND gate if the input is tied to 0 then the output is always 0 so the gate in fact is not required you could drive the output net directly so the design compiler might remove set them if they are not don't touch so it could be a problem for the input it will also tell if there is a mismatch between a standard set it will tell the mismatch between a module and its instantiation so maybe you instantiated some some module but probably there is some output some kind of problem that you report or there is a 5 bit bus 4 bit multiple driver nets very very important ideally you should implement the multiple program logic you should not let DC input you should design it you should use the client state inverter or corresponding logic process ideally you should not let DC input multiple technology recursive hierarchy means that it is more related to the function of the device tell you about that so the best practice is to always ensure although it is true that a good verification simulation is normal we catch most of them but many times synthesis is a very popular in the design you would use synthesis a lot more time during the whole design cycle to gate load as a performance of the design so it is a very good practice to make sure that so many times the RPL the design is not common it is in development phase and you are doing something it is a good practice to check the consistency on feedback into the design then this was developed before the before going to compile stage now during the compile stage DC with print compiled off and what are the information will give you by default here is the list of that it is very much as a last time so this is the left most part of the last time so I will see the how it takes during each of these steps it tells you about the area versus negative slack the slack is the difference between let us say for the register to register path we will come to it in the example timing before so if a signal is expected by some time but if the signal arrives later so the expectation is set according to the design so the block you define will tell you see that at this time the signal should arrive because the register to register path by default should complete the timing transaction should complete within one job cycle so this takes a restriction on the data arrival time so data at the chapter block should arrive at some time this this bold time the difference between this bold time and the actual arrival time is called slack that means that path is not meeting time so this will tell you what is the this column tells what is the worst negative slack among all the critical path so it will also tell you about the total negative slack total negative slack is the sum of all the critical path it will tell you what is the design root cost design root cost if it is positive means there are some development policies in the end point that has the worst negative slack so it is considerable there are additional fees these are the fees additional fees and this variable can be used to customize it but the first step is you should be able to understand what does which of these three means and so for example in this in this log file we see that as the time progresses the worst negative slack it will step from going from step 1 to step 2 comes down so this is where the design compiler is optimizing the design for time or performance the total negative slack also gets reduced although the worst negative the end point of the worst negative slack will remain free so it means that DC is optimizing for timing that a lot of these logs during your labs so please pay attention to those if you find that it is taking a large amount of time in some of the tests in the design load or fixing timing it will go back and take the function so this is the good this log is the good integration of how good are your constraints and how realistic are your performance so this is the summary of all the commands that will help you get gather more information now we are talking about this page where compiler is done and now you want to report area all the figures you want to get all the reports related to the design the compile design or the map design so these are the this is the summary of commands so please notice this talks about the design object we talked about what the objects are the objects are design instances, references, spin scores, net, plot these are all kind of design object and these are the commands that work on these design objects to give the description tells what it actually does for example let's talk about the design the object design so when you talk about design we are giving the current design the scope of the current design so report design we will see what report design does report hierarchy, report resources so these are all the source commands even report design characteristics if you tell us what is the area and the object counts we will see exactly report report hierarchy we will tell what is the hierarchy, how many centres are there report resource specific to we design by the proposal the adder has multiple items we will see in detail we talk about instances and references there are commands reports and reports the same information about instance then we talk about pins so there is the command some of the commands work on multiple design of this so report transacted time and time out work on indepence or port if you do not understand the difference between pins and port please refer to the earlier slide the pins are reports only refer to the popular input and output pins are inputs and outputs of internal hierarchical design so these commands report the time and time out of a respective port pin or net report bus tells us about the bus ports report port command is very very useful it tells us about the somebody about input delay, output delay output report port gives us the summary of the capital systems that you applied and outputs using set load you might have applied any foundation of the input input formation it will tell all those information single report the command is report port again report might will give tell us about the net characteristics similarly report clock works on clock that we declared it tells somebody about clock let see some reports so report area these are the important reports that you should use after the compilation the report area works on current design it tells us so this this is telling us what is the design mean this tells us that this this tells us that what are the libraries that I use this tells us about the design of number of ports please note that all this information is specific to current design number of ports, number of net, number of 10, number of combination cells number of system design number of macros this means so we see that from library report we see that only some sort of standard cell library is being used so the number of macros is zero if you let see there was a memory here the number of macros will reflect the number of instances of memory it tells us what are the number of buffers and then it tells us this is the area combination area non combination area includes frequency cells less memory if the biode area has below net area then the net and technical area will be defined total cell area is sum of combination and non-communist area total area is sum of total cell area less net and technical area since net and technical area is defined total area is also in fact I remember that in the lab the net and technical area is not built so the total area is sum of cell area and net and technical area now in my opinion net and technical area is not a good scenario since viral model is just an estimate so the viral the area of the net is also an estimate so the area in fact is not a good is not even chose to the physical the viral model is very important from time of model from getting the performance because you cannot ignore the timing of the net but the area figure is more misleading so I would it is a good thing nowadays all viral models have zero interconnect area it does not mean the area is really zero it means that the estimates are not good they are also from timing but often they are now let us take some of the commands the report design is one such command which gives us a good summary of the whole design so it lists the operating condition it tells us the for example again it goes on a current design it tells us what is the design name it tells us in the the library is being used it tells us what is the operating condition so it is the operating condition from this library it tells us the process value we connect so on so viral model it tells us that it is collected normally by the user so this is the viral model it tells us what are the input delays what are the output delays we will talk about disabled timing arc so we will not so unit 5 we will discuss more about there is something called timing expression so we will talk about disabled timing arc by discussing those things so these two commands report area report design we will tell you everything we will teach you about the area if you let say your design is hierarchical in most of the cases you could change the design by using the command current design and you could report area as that if you want to the total shape design total area of the complete design you could change the current design and you could report this metric this data at any level now let us look at the commands we saw how to report area how to report timing again there are a lot of commands report design does give you some insight by reporting the viral model by reporting the input and so on but the most famous command is this one check timing then there is a command called check timing now check design told us if your design is good from the connectivity point of view from the transparency point of view that is if your inputs and outputs are unconnected check timing on the other hand works on the design constraints if you have some problems related to timing constraint report code we talked about I haven't used report timing so this is a more famous version of the command so I used most of the time we went to the R10 unit type report log will report the document then we will see report time and report constraint and so on this is the check timing so check timing will be in design compiler check timing will tell you why I say design compiler because same command works in time time but it gives much more data than design compiler so many commands are common between design compiler and time time but some commands are very some commands will give you more data in design compiler if they are related but all the commands that are related to timing because they are check timing report time and report constraint if in most of the cases there is more data there will be more data when it comes to time time because time time is the static timing of the tool it is a tool that deals in timing so everything time time is superior to the things that help us in the time in design compiler design compiler is more of an optimizer it is not a timing analysis time time is a timing analysis so all commands related to timing analysis this is analysis right we are talking about the reporting time these are all analysis commands all these analysis commands are much more powerful in time time so we will see a lot of data so check timing inside design compiler about unconstrained timing path so if you go back to basic and move down what are the timing path input to register register to output input to output from the combination path there are other type of books also again unit 5 will be coming in but for design compiler purpose there are 4 kind of timing paths if any of the timing path is unconstrained due to some reason then design compiler is one of the problems now what could be the reason for example you have an input at which you have not applied any input to it it means that from that input to the first law that captures the input the project captures the input the project captures the input there is no goal so DC will not know about this will it stop doing synthesis no it will not stop so this is what you do after synthesis after the first part synthesis what happens if it is unconstrained DC will go ahead just fine but that path will be slow it will not make any effort to optimize timing it will make any effort to optimize it if the input is registered that means, there is no combination of this input and clock there is no area to operate right. So, it will tell you what is if your design has multiple clocks and you forgot some clock to forget any clock to define any one clock the registers in that clock domain will be inconsistent. So, it will tell you about that then it will tell you about the clock gating logic that any if any clock is gated by any input thing clock means clock gating logic refers to the gating of clock. So, it is what you could have you could be using an input and ending on ordering this an input clock. So, it means you are gating the clock. So, gating clock gating logic you should be careful about it means you see more of clock gating in power compiler and you talk about power the dynamic power and how clock gating can reduce dynamic power we will talk about that in next few sessions, but you should review your clock gating logic in your design because if you have it by mistake and it can be written to have. So, it will give you warning about those it will tell you whether your design contains unmapped cells when what is the case you might have unmapped unmapped means that DC has not mapped from g-tech to now please remember as soon as you do an elaborate DC will create a g-tech access it will map the design to g-tech that is always the case, but it might find some logic where it is not able to map from g-tech to power gating and in that case it will leave the logic in the form of g-tech. Do you want that obviously not ultimately our agents to get a network that contains only the mapped components. An example let us say your standard cell that it does not contain absolute clock to g-tech and in your ideas you have inserted and integrated. Now g-tech reset is a logic that cannot be exercised by any combination logic. If the clock with g-tech reset is not proven in standard cell algorithm it will cannot be used. So, it will leave the clock as it is in g-tech format so it will have a section instance corresponding to that all this clock with g-tech reset and it will leave it as it is and the check timing command will tell you that the design contains unmapped cell. So, it is a very useful check it will always do this check for unmapped logic and make sure that it is correct either your design or make sure you have a correct level. Now there is a command for report clock it will tell you about all the clock in your design. So, this report shows that there are three clocks in the design it tells you about the period the waveform the source means at which pin the clock is there at which pin the clock is created. For example, this off chip clock it tells us the period that the source is empty empty source means it is a virtual clock we will see later how virtual clock are useful. Then for each of the non-virtual clock it will tell what is the right delay, wrong delay or latency defined. It tells us about the uncertainty it tells us about the objects the clocks are reaching. So, I do for example, between the clock and so on. So, this has happened the clock see in the pin of the clock. The report clock it will simply do a report clock it will just report till this part it will do if you say minus q and minus altitude it will pass between more than that. Again any command you could do a man or you could do a minus altitude more of movement about the option. Then report qr qr means quality of the words it gives the good overall status of design timing. It gives the timing summary for all path group what is the path group path group can be path group is defined by also by the capture clock. So, register for which it is a capture clock is x the path group by default is x. We could create different path group by using the commands of group path we come to that later. But for now we can understand that for example, let us say there is a register path. Now the path group for that would be the clock name of the clock that captures data on the clock. Here we see for example, there are 2 groups clock 1 clock 2. Now it tells us what is the levels of logic levels of what is the how many combinations of the regions are there for the worst path. It tells us what is the critical path path means critical path means that what is the maximum amount of time taken by a path in this clock group. The critical path that is violating that has a slack of minus 2.64 the total amount of time that it takes for data to arrive is 3.64. It tells us what is the critical path clock period the clock period is 11.62 for this clock 1. Total negative slack that means it will sum up the worst negative slack for all the volatile path in this clock group that is the total negative slack. It tells us that total number of volatile path is 50 m, total number of old volition is 1. Similarly it will give the summary for the clock 2 it will also give the high excel cell count and high excel port count. It will tell us what is the lead cell count. I have already discussed what is the lead cell. If you do not remember please refer to the earlier to the last session. So, reports you are in the clearance it tells us it gives us a good overall status of the design time right. Now this is the summary. What is now I know that okay minus 2.64 is the worst negative slack in the clock group clock 1. Now how do I go into specific problem? I had to summary but now I would want to know what path are volatile? Why are they volatile? This information once you get this information it will help you in exterior design right. So, now a second level of summary is provided by report constraint. Report constraint as the name suggests tells everything about the constraint. What are the constraints? Constraints can be tiny or designing right. The report constraints as order options and as soon as you do report constraint without any option it gives you a difference between user constraint and option design time. So, it tells us it has so many checks max transition, max run out, max delay, critical range, wind delay, leakage power, area and so on. So, it has so many checks all the checks that your design have. If you design it off automatically max delay or setup check will be in place. Wind delay or board check will be in place. The library has max transition and max capacitance and maximum number all these three mean that they are design constraints. So, it will give you a summary of all the design constraints. If you say report constraint minus all, minus all this for all variables it will tell you all the versions that I am going to design right. So, for example, this report report constraint for all variables. Now, it is reporting for max delay or setup check for this clock 1 group that means all the power that I captured at clock 1. Now, it starts giving us end points. These are these should be the should be the output points. So, it tells us that at these output points where the required part delay is 1 actually 3.6 volts for the clock 1 is 3.6 volts and the status is valid. What it means is that according to design constraints the required part delay should be 1 nevertheless. This is the goal. So, you are validating by minus 2.6 volts. So, this report minus the option minus all the variables will give you a list of all the variables. Now, it told us what is the end point. So, report QR gave us summary how many parts are validating. Report constraints minus all the variables this is down each and every end point that point. The start point what about what is I want to see a complete part. So, please remember for example, a register to register part will have a start point register it will have the combination logic in between it will have the capture register. So, I want to see the end all the variables. So, the command is report timing report timing on the most famous commands report timing report extremely flexible it has lot of options from 2 minus max parts minus max it should tell you minus combination we will see lot more of it in the lab but I will just give a summary of it. So, report timing report typically as other options are other other is very obvious the design may be validable so, it starts with a start point so, it has a start point it is an end point it tells us what is the path group path group can be will be usually the capture plot in this case it is mine so, that means there is no plot that is capturing the group we will see this is a the example is of an unconstrained report unconstrained means there is no goal as we capture so, either it is an output port or it might be the claim that it is a plot which does not have any plot so, in this case it is an output port. So, the start point is an input port end point is an output port there is an input delay which is denoted so, input is seen it goes to an answer so, z is the output it reports on the output it goes to any other input and carry out of those the carry out is a thing the cell is probably a full adder the c o is the carry out pin so, this path goes from the input to output to a lot of cells a lot of combination cells it goes to c out now c out has no output delay defined if there is no output delay defined there will not be any path group so, therefore, the path group is now data arrives at 12.38 the left column the INCR is the incremental delay for each so, this is the delay attributed to each cell so, for example, 2.27 is the delay of this full adder and the path is the cumulative delay so, each of the cell delay is this total path delay is this so, the path delay is 12.38 and there is no output there is no goal there is no concept of path any time if the delay is we cannot just if the delay is more or less because we know how to go this is the summary of the very basic so, this is only what we just 1 or 2 percent of what report timing can do report timing can do much much more this is the command we have to recommend each and everybody to read the map we read the map page we will have some information with the the data page we have but then when you start using it you will start remembering what you read in the map again when we go to prime time this command is much much more powerful and it has some more options and it is the command that is used it is a very important command we do read more about it please understand what is actually the both so the last command so, we have gone through the summary part to reporting the points which are validating to looking using report timing to tell what part so, report constraints that what in point is validating report timing further tells that what is the start point and what are the what is the delay of the moving in the part so, we have gone from summary to more specifics now let us say now this for example, this full adder is taking 2.27 nanoseconds but the other full adders that are following it each of them is taking just 1.1 time so, there is a difference a big difference in the delay between this full adder and the rest of the full adders that come now as an engineer I want to know that what is following what is the calculation that is important here how will we see calculating the delay of 2.27 I can use the command called report delay calculation I can say that so, here the example is like this right add a new one month now I say report delay calculation I ask you see how did you calculate delay from input is of the same so, the same add a new one month from the input a to the cell c open now DC will tell me that from this pin input pin to this output pin the input net transition time is there the influence it is so, it will tell you the calculation the formula it used to calculate the timing and it also depends on the ladle so, if your ladle is non-linear delay model the calculation will be different please remember we have very very good slides in the ladle session that we discussed it discussed the non-linear delay model it also discussed the linear model so, from this calculation I can say it is the number that is talking about rise time input and rise resistance if you remember non-linear delay model in the look of table based model this calculation it tells us that how did it compute the rise delay as we output how did it compute the spot delay so, it is telling us that for rise delay reduce the rise influence it 1.5 time plus rise slope into dt rise into something some factor it calculates the rise resistance so, it will give you all the calculation it is it helps us to know however it is you will not do it for lot of things you will do it for only due sense of which you want to understand first of all in any decent design decent things in a big enough design there are 1000s and 1000s of formula will you look at all no you only look at the ones that matter what matters the critical part of the model now in that critical part do you look at the delay calculation for each and every no you look at the timing report timing you figure out what are the sites which have worse delays and most probably you will know the reason if you have some experience you will know that it has a bad function or it is driving a lot of cells as a bad and so also the reasons are thing well common but report delay calculation will help you in debugging more or more so you can again try this command in the lab the report delay calculation in the lab will not mark this the one in the slide because the the lab will have non-digital model this example is from the the linear digital model so just see if you understand the delay calculation of one cell in more time before this this this slide will tell that let us say now I am doing a performance evaluation I do not know beforehand that what clock frequency can I operate on so one of the useful thing is what you could do is now let us say each technology has some data available on what is the percentage of cell delay versus memory for example in 90 nanometer if I remember correctly the percentage of cell delay to memory delay for the statistics is collected over lot of designs of large industries so in 90 nanometer probably the cell delay is more like 40% of the design and memory delay is probably 30% as we shrink the cells are becoming the technology shrinking the rest are getting thinner and thinner the cell delay is improving but interconnect delays are not improving as a result in technology like 45 nanometer I guess the cell delay will be 50% and memory delay will be 50% now what I can do is I can set a value for the 0 and the delay to be proved such as 0 and the delay to be proved I do a report to you what this you will do it will make all the interconnected as 0 and it will report timing based on the cell delay now let us say if 45 nanometer I know that the ballpark figure is 50% if I know only the cell delay and so I can judge what is the clock frequency I can operate on this method setting the 0, interconnect delay to be 0 it helps us in assessing the designing constraint please note we are discussing about the map design map design means after atleast 1 part of synthesis so this is the flow you do compile first you set this variable to prove and report to you and again set this variable to false so this is just a reporting amount so this if you want to do any more combination you have to set this to false just remember write out in the last this is a good way to see that what is my cell delay part and what is my biode model to separate the model so so you would you could find that my design with the 0 interconnect delay it works as 200 megahertz but then I switch on the biode model it works at 300 megahertz so it will give you some some figures with respect to what frequency is in power there are 2 attributes what I want to talk about one is the don't touch that is high volume so what would happen let's say I have instantiated a cell in my design very specific cell or let's say I have instantiated a cell in my design and I do not want design compiler to optimize I can set a cell design compiler and set don't touch on the cell so design compiler will not optimize them so many times you get a design from some part 2 you get some things and you find that some of this it might be due to a don't touch but don't touch might be set in the design how do you debug so first of all if DC doesn't optimize the removal cell on it it is often due to a don't touch explicit don't touch is straight forward to debug you can debug for don't touch in your design and cell file you can also report don't touch by saying you do a command for report don't touch command so you should know that you should know that there is such a thing called don't touch and it is mostly used to make sure that some of the cells or some of the nets that you don't want to optimize for some reason and how to debug this so this is the command again there is a second attribute called query room now let's say I instantiate a buffer and I want that okay fine the buffer should not be removed but I say tell DC that yes do not remove it but you may upside it or downsize it may be to solve design new problems so let's say I have buffer and I know that it might have a last form after being mapped let's say it is driving the last one but I do not know for sure that what is the drive unit on it I am not too sure about it so I can choose a lower drive in my instantiation and tell DC that it is a size only attribute set a size only on it by using a command set size only now DC what you do is it will keep the buffer but it can upside it to solve design new problems so size only tells DC that this is not to be removed but it's drive can be changed so for such for reporting such instance you can use report size only command it will tell you if you have any size only attribute set so you can read more about it by doing the math so this was all about analyzing reports and analyzing reports so we saw so this is the so this is the list of commands that you could use to report on design of it to report on area again this is the list of commands you can use to report on timing so there are two reports period reports and timing reports so I listed down the more famous commands there so then let's look at now you specify design with analyze reports analyze timing everything is fine for the next step next step is you have to write out the design database and in most and in the chip design so little design so the backend will now take over now this design should be laid out, laid them out and then it will go to fabrication if they are working on a real chip so the next step is to write out the design data and what are the formats available to us there is a format called DDT it is a synopsis internal database format the landlord these are the two most important formats we will work on you could read about if there is VLB also it will be more of you there is a milky way milky way is again specific to synopsis welcome to it so most popular are DDT in the box DDT can only be read by synopsis tools and DDT contains netlist plus constraint so if you say write minus format it will write out even the constraints and so for example we will see in the lab I will write out the DDT and we will see that all the constraints are added it will have the so when I apply a clause all this information will be written out in the database where loss, where loss is the plain netlist it does not contain constraints so what is the use now let us say the backend version is working on synopsis tool so I can directly give DDT because that is it I do not need the data file but if the backend version is working on a backend tool from some other company it is from KDNC those tools will not read DDT they need to be given verlaw so I need to write out the verlaw plus I need to write out the constraints separately so there are different formats for constraints now I need to give the verlaw plus the constraints both of them is a backend right this is the right command you could choose the format to be DDT or verlaw minus hierarchy without this design compiler will only write out the current design not the complete hierarchy so you should always use minus hierarchy minus output tells what is the name if you do not use the minus output option why they call it write out the file design now when we write out verlaw for the backend engineer and if he is using let us say he might be using any tool for doing backend there might be issues in the naming the method so before I think in at least within this shell we have to make sure that all net and port means can form tools some names can mention that is used by the layout tool usually in most of the cases every tool will determine them it is safe to give a verlaw syntax to the backend tool but we have to make sure that the verlaw netlist conforms to the verlaw naming now the design inside design compiler when the design compiler is working on the design it will not follow the complete verlaw the whole verlaw so we have to make sure that before writing out we should then make sure that we should make sure that the names are corresponding to the verlaw how do we do that first step no change we need in the rvl second step no change we compile the design now before writing out there is one more step we use the command chain names for example we can use something like chain names whenever we want to write a verlaw we use this name so we issue this command chain names and then use the write style command name is format verlaw so it will also list when we issue change names command it will tell us what all names it is changing so what i will tell you i will recommend in your lab write out the netlist and then again write out the netlist it will change i will probably include this in my lab we will write out both the netlist before name names and after change name and see what will be the change that will give you some idea into what kind of name change appearance and then we can use change name and use again the command write style and then deliver this netlist and thus constraints to the back energy these are some of the additional commands some of these we have discussed some of these we see in the labs and for more information you could you can go to this you already know how to use it thank you