 Hello, and welcome to this presentation of the STM32 Serial Peripheral Interface. The internal serial peripheral interface or SPI provides a simple communication interface allowing the microcontroller to communicate with external devices. This interface is highly configurable to support many standard protocols. Applications benefit from the simple and direct connection to components which only requires a few pins. Thanks to the highly configurable capabilities of the SPI, many devices can be simply accommodated in the existing project. The STM32 SPI offers various operating modes that are explained in more detail in this presentation. The communication speed can't exceed half of the internal bus frequency and a minimum of two wires is required to provide the serial data flow synchronized by clock signal in a single direction. An optional hardware slave select control signal can be added. The data size and transmit shift order are configurable as well as the clock signal polarity and phase or polarity and timing adjustment of the slave select signal. The crucial configuration and settings can be protected by locking. At the protocol level the user can use specific data buffers with an optional automatic cyclic redundancy check or CRC calculation and transfers through the DMA controller. There are a wide range of SPI events that can generate interrupt requests. The simplified SPI block diagram shows the peripherals basic control mechanisms and functions. The separated clock domains are highlighted by areas with different colors. All the interconnection signals between the domains are synchronized. The PCLK clock domain has to be clocked when any access of the SPI registers is needed via the peripheral bus interface. The SPI master needs at least an active kernel clock as it has to output the clock signal for the slave. The SPI slave can transfer data without any internal clock signal as the serial interface domain is fully clocked externally via the SCK PIN. All of the data passes through receive and transmit buffers via their specific interfaces. The available features can be enabled or disabled depending on the peripherals configuration. There are four IO signals associated with the SPI peripheral. If required the peripheral can keep control over the associated IO signals even when it is disabled to prevent any unexpected glitches. The SPI master always controls the bus traffic and provides the clock signal to the dedicated slave through the SCK line. The master can select the slave it wants to communicate with through the optional slave select or NSS signal. Data stored in the dedicated shift registers can be exchanged synchronously between the master and slave through the MOSI master output slave input and the MISO master input slave output data lines. In full duplex mode both data lines are used and synchronous data flows in both directions. In simplex mode one node transmits data while the other receives the data. Data only flows in one direction depending on the communication direction only one data line is used. Unused SPI pins can be used for other purposes. Half duplex mode integrates the previous two modes by sharing a single line for data exchanges and data flows in a single direction at a time. There is a cross-connection between the master MOSI and the slave MISO pins in this mode. The master and slave have to alternate their transmitter and receiver roles synchronously when having a common data line. It is common to add a serial resistor on the half duplex data line to prevent possible temporary short circuit connection since master and slave nodes are not usually synchronized. When the SPI network includes more than one slave a star topology is commonly used. The master communicates with one slave at a time since you can only have one slave transmit data back to the master through the common MISO pin. In this topology a separated slave select signal from the master has to be provided to each slave node so the master can select which slave to communicate with. Thanks to separate slave select signals SPI data and clock format can be adapted for each slave if the multiple slave nodes do not have a common configuration. Another multi-slave configuration is the circular topology where the inputs and outputs of all the nodes are connected together in a closed serial chain. A common slave select signal is used for all the nodes as communication occurs at the same time. All nodes must have the same data and clock format configuration. Micro controller SPI nodes typically use separate internal transmit and receive shift registers so the data transferred between them has to be handled by software in a circular mode. A specific underrun feature can be selected during the slave configuration to automatically handle these transfers by hardware. SPI networks can operate in a multi-master environment. This mode is used to connect two master nodes exclusively. When neither node is active they are by default in a slave mode. When one node wants to take control of the bus it switches itself into master mode and asserts the slave select signal on the other node through a GPIO pin. Both slave select or SS pins work as a hardware input to detect potential bus collisions between nodes as only one can master the SPI bus at a single time. After the session is completed the active node master releases the slave select signal and returns back to passive slave mode waiting for the next session to start. Several parameters are used to set up the data format. Users can define the data frame size and the transmit order of the shift register. The clock can be set to one of four basic configurations defined in the Motorola SPI specifications. The combination of two bits controls the polarity and phase of the clock signal. When the phase control bit is cleared data bits are sampled on the odd clock edges and the even clock edges synchronize the shifting of the next bit onto the data line. This is the opposite when the phase control bit is set. The clock polarity bit defines the idle state of the clock signal and which clock edge is used for data sampling or shifting. The slave select signal can be used with both polarities and the functionality of the MOSI and MISO signals can be swapped. Several parameters can be used to optionally adjust the timing of the master transaction flow. Signal timings for the master node can be adjusted when needed. This is the case when a slave node needs a longer time to wake up from sleep mode following the setup of the SS active edge or when the slave is not able to handle a data flow that is too fast. Up to 15 additional serial clock signal period delays can be inserted by MIDI or MISI parameters. Data frames can be optionally interleaved by SS pulses. All SPI data transactions pass through the embedded FIFOs organized by bytes. A write access to the SPI write data register stores the written data in the transmit FIFO at the end of a send queue. A read access to the SPI read data register returns the oldest values stored in receive FIFO that has not been read yet. When the communication speed is fast and data frames too short it can be a demanding task to ensure correct data flows especially when the clock signal becomes continuous and full duplex mode is used. Slave nodes are more critical as they have to properly follow all the transaction timings provided by the master to prevent any data overrun or underrun conditions. The user can organize data into wider packets and handle multiple data read or write events by minimizing access to the data registers. The services are based on FIFO threshold events signaling packet ready operations. If FIFO thresholds are properly set multiple data packet services can be performed upon minimum FIFO occupancy events. Read and write events can even be serviced together based on common dual events. These features efficiently decrease the number of services and so minimize the load of the microcontroller when handling data flows. This can be especially useful in low power modes when data is sent while the microcontroller is sleeping. When the DMA is applied additionally it helps to significantly reduce overall loading on the system in run mode. In the figure shown you can see the principle of how four short data frames can be written and read by a single 32-bit or 16-bit access of the dedicated data registers associated with the FIFOs in accordance with the FIFO capacity and maximum configurable data size of the SPI instance. The SPI peripheral features two FIFOs to handle the data flow. The capacity of the FIFOs and maximum data frame size depends on the product and the peripheral instance. The frequency of the FIFO occupancy events depends on the FIFO threshold setting which organizes data into packets. A single packet can include up to 16 data frames but its size may not exceed half of the FIFO size. Possible combinations of data and packet size to fit into available FIFO space are listed in the table. Once room for a single packet is available in the transmit FIFO to store a new complete packet of data or a single complete data packet is ready to read in the receive FIFO the corresponding TXP or RXP occupancy flag is set. The user can then perform proper write or read service of data registers corresponding to a single packet size. Both packets to be transmitted and received can be serviced by a common handling procedure when the dual occupancy DXP flag is set. The occupancy flags are evaluated dynamically in relation to the bus traffic and the current FIFO content so they have to be checked exclusively once the associated packet service is fully completed. Both the master and slave can apply either endless data transfers or handle a defined number of data to be sent within a single session. The number of data is practically unlimited as it can be extended on the fly as long as the transaction is ongoing. A cyclic redundancy check can be implemented automatically or the slave select signal can be handled by hardware on the master side during the session. The master can start or suspend ongoing communication at any time. The current data frame is finished when the transaction is suspended. A specific CT size counter counts the number of data frames remaining in the current session, end of transaction or EOT and the transmission complete TXC flags indicate the end of session and bus idle while an additional specific TXTF flag indicates all data submitted for transmission and its event disables interrupts from transmission occupancy events. Transmissions automatically stop when the session is completed at the master side even if there is additional data in the transmit FIFO. All the FIFO's content is flushed when the SPI is disabled. The user has to read out all the received data before the SPI is disabled. Except for occasional errors the software has to take care of FIFO occupancy events only while the session is ongoing. Once the session is finished and the remaining received data is not aligned with the packet size, the last RxP occupancy flag is not set but the RxWNE flag is active and the level of the current FIFO occupancy is signaled by the specific RxP LVL level counter that depends on the data size. The counter value signals how many data frames remain to handle at the received FIFO. Nevertheless application software can still perform full packet reads without any drawbacks as the only consistent data will be popped from the FIFO. Similarly full packet writes to the transmit FIFO can be applied in this case as only the consistent data will be pushed into the FIFO while redundant writes will be discarded. When the DMA is applied such non-aligned data is handled automatically. To prevent overrun conditions and the loss of any data the master can temporarily suspend ongoing transactions when its received FIFO is full. The slave can be configured to detect and react to underrun conditions when no data is ready to be sent in its transmit FIFO and when the master continues or starts a new session. During protocol level communications the DMA controller can be used to automatically handle the data flow events the CRC calculations and the updating of the FIFO threshold. In case of threshold control the last odd data frame is correctly applied in packed mode when the number of frames is not aligned with the packet size. If the CRC is enabled separate CRC calculators are used for the transmitter and receiver. The CRC calculation result is automatically appended at the end of each transfer by the DMA controller or by software control. Both CRC polynomial pattern and CRC frame length are programmable. The size of the polynomial is defined by its most significant non-zero bit and it always has to be longer than the data size. The CRC frame length has to be equal or a multiple of the data size. The CRC calculation is frozen during the CRC pattern transaction. Results from the transmitter CRC calculator register are loaded directly into the shift register and the received CRC value is stored in the FIFO and compared with the receiver CRC result. Redundance CRC information are automatically flushed from the FIFOs. As the CRC registers are automatically initialized the CRC can be used in DMA circular mode. Initialization patterns for the receiver and transmitter can be configured either to zero or to all ones. By this flexibility a wide range of protocols is covered. The slave select signal is commonly used by the master node to select the slave node for communication. The signal implementation is mandatory in multi master and multi slave topologies. Though it is not mandatory at a single master slave pair it could be helpful for data flow synchronization regardless of the topology case. The slave select signal can operate as an input or as an output depending on the SSIOP control bit. The SS input can be managed by hardware or software depending on the SSM and SSI control bits in either master or slave modes. As an input slave it is used to identify itself as the active slave for communication. As a master input it signalizes a potential conflict between masters in a multi master system. The SS only works as an output in master mode and is managed by hardware in a standard or specific control mode. Additional slave select outputs can be provided by the GPIOs under software control. There are a few enhanced modes when the slave select signal is under specific hardware control. The slave select signal can operate in a pulse mode where the master generates pulses on the signal between data frames. The duration of the pulses is programmable in steps of SPI clock periods. The clock phase and polarity are configurable in this mode. Another enhanced mode is the TI mode where the data flow is synchronized by the SS pulses provided by the master on the last bit of data. The clock polarity and phase configuration is fixed and the slave data output is automatically switched into high impedance when the bus traffic stops and on a specific configurable timeout. Here is an overview of the SPI interrupt events. There are FIFO and error detection events to handle data flows. DMA requests are triggered internally by FIFO threshold events. The EOT event raises automatic control of the last incomplete packet when the overall number of data sent is not aligned with data packet size. Here is an overview of the SPI status in specific low power modes. The relevant system power domain depends on the peripheral instance. Every instance is divided and handled by three separated clock domains. The PCLK clock domain has to be clocked when any access of the SPI registers is needed via the peripheral bus interface. If the bus matrix clock is stalled, the peripheral registers content is retained. If the peripheral kernel clock is enabled, the clock generator can control the SPI master operation too. Otherwise, the peripheral is able to operate in slave mode only because the peripheral serial interface is then clocked by the external clock signal via SCK PIN exclusively. A peripheral event can be configured to wake up the system. The device cannot operate when its domain is in standby or shutdown mode. That is why it is important to ensure that all SPI traffic is completed before the peripheral domain enters standby or shutdown mode. The application acknowledges all pending interrupts before switching the SPI to low power mode. The SPI performance depends mainly on the applied clock. At a minimum, the clock frequency should be twice the required communication frequency. The actual rate of communication can be decreased by application factors. The user has to consider SPI bus loads such as the number of nodes, the connection distance, the input capacitance, as well as the GPIO settings. Fast GPI mode should be applied on the data and clock signals. Lower power supply voltage and extreme ambient temperatures slow down edges. Sometimes slower data hold or setup time requirements have to be respected between nodes. Applications can't always manage the fast data flow due to frequent servicing of exceptions. The DMA capacity has to be considered as well as the number of DMA channels used by the system, frequent interrupt services, or execution of non-interruptible instructions. The SPI can be used in a wide range of applications where a simple data transfer is required without the need for a complex communication protocol. Secured transfers are also supported when used with smart cards. Here are some helpful tips. The user should be aware that traffic on the bus may still be ongoing even if the DMA transaction is completed or the transmit FIFO becomes empty. That is why the user has to carefully check the peripheral status and follow the suggested procedures before disabling the SPI or placing it in standby or shutdown mode. Use the data size control if you need specific control like CRC or slave select signal handling by hardware. The use of the DMA, data packing, or handling dual event at full duplex mode can increase the system's overall performance. These features can help especially when data frames are short and a fast continuous communication flow is required. Hardware management of the slave select signal is not quite necessary in a single master single slave pair, but it can help synchronize the data flow and prevent conflicts in a multi-master system. When the SPI master has to be disabled temporarily for any reason, the user can prevent any glitches on the associated outputs working at alternate function mode by keeping them at forced under control. Then the GPIOs are kept at the state corresponding to the SPI idle configuration. The user should keep all the configuration and settings locked to prevent any accidental changes. There are some additional specific aspects which should be taken into account when designing an SPI network. Evaluation of FIFO occupancy flags is dynamic and depends on the bus flow. That is why the event service has to be applied when the complete data packet which corresponds to the FIFO threshold is finished. Once the complete packet service is finished, either read from or written in the FIFO, the occupancy flag can be tested again. Slave internal logic is clocked from an external SCK pin. Certain flags need a few periods of SCK signal cycling to be evaluated and can't be evaluated as long as the SCK signal stays at idle. There are six SPI instances within the STM32H7 and each support all the features presented so far. SPI2S1, SPI2S2, and SPI2S3 are multiplexed with I2S interface and have double extended FIFOs and data size registers. Refer to these other trainings which are linked directly to the SPI. Users should be familiar with all the peripherals that can affect the behavior of the SPI. There are some dedicated SPI application notes. To learn more about general SPI connections and interface issues there are many web pages as well as SPI bus monitoring tools available. Many digital oscilloscopes support direct reading and analysis of data and clock signals on the SPI bus.