 Okay, it looks like it's time to get started. So my name is Drew Festini, and this is a Purpose of a Feather Discussion, or BOF, or Risk Five in Open Hardware. So if you're not familiar with the format, this is meant to be more of a discussion than just me up here talking. I have some slides to kind of guide the conversation, but it really depends on what all of you out there want to talk about. So a little bit about Risk Five, a little bit about Open Hardware in general. So I'm a Linux kernel developer at Bay Libra, but I'm also part of several organizations that are involved in Open Hardware, one of which is BeagleBoard.org Foundation, and they're here. We have a booth out in the front, and all of the boards that BeagleBoard.org produces are Open Hardware, so you can check that out. Of several people who have been giving talks, I think Jason had one earlier, and there might be more later in the conference. So show of hands, who's heard of Risk Five? I'm guessing it's probably most people. Okay, so for people that haven't heard of Risk Five before, it's a free and open instruction set, or ISA. It started back in 2010 at Berkeley. There was researchers doing work there on accelerators, and they needed an instruction set to base their designs on, and they decided to create a new one. The five, or V is a Roman numeral for five, so that's what the V is. So most people say risk five instead of risk V, but if you say risk V, people will know what you're talking about as well. And why is it free and open? It's free and open because the specifications for the instruction set are published under a Creative Commons license, and there's two different volumes, one for unprivileged, which is kind of like your lower level, sort of like non, you would not be running an operating system, like Linux on that, and then privilege where you have like a machine mode and then a supervisor mode, and you'd be running a full operating system on it. So we're not gonna go too deep into risk five since there's been a lot of talks about it in the past at the embedded Linux conference, but there's this book that's only about 100 pages, and it goes through risk five in depth, so I recommend checking this out. You can get the print edition, there's also an ebook available in a bunch of different languages, so it's a good way to get up to speed with risk five if you've not learned about it before. So the specifications that I mentioned are stewarded by an organization called Risk Five International. Used to be called Risk Five Foundation, but they reincorporated in Switzerland a few years ago to be kind of neutral geopolitically, and they're at riskfiveorriskfee.org. So it's a nonprofit composed of companies and universities, and it keeps on going up, it's several thousands of members at this point, but anyone can join. So as an individual, like I joined originally as an individual myself, you can join free of cost, or if you're a nonprofit organization, you can also join. Is anyone here a member of risk five or part of a member organization? Like if your company's a member, you would also be a member, but if you're not and you want to get involved, you can just go and sign up as yourself free of cost. And then once you're a member, you can participate in the mailing list, and there's lots of meetings that happen on like bi-weekly and monthly basis. So since it's the embedded linus conference, a lot of us probably like dev boards, so there is a program from Risk Five International called Risk Five Developer Boards, and the goal here is to get dev boards out into open source developers' hands. So this is what we can go on for, I think about two years now, and there are two exciting things that you can apply for right now. So one of which is a 64 core board, which is very exciting, and the other one is the four core board called the Vision 5-2 board. Yep. Any more questions? Any more questions about the cancellation of Beagle 5? Yeah, so we did beta with some people about two years ago. Unfortunately, we weren't able to get chips to go to production for that, but we are continuing to work on designs for Risk Five Boards, so there are things in the work, but essentially when we announce it, you will be able to buy it from distributors. So we're gonna wait until things are ready and distributors and you can actually order it. So there is things happening there, but nothing we'll share right now. Any other questions or comments? It's meant to be kind of a discussion, so if anyone has comments or anything you wanna share, we have a hand back there. So for a newcomer, what board would you suggest to buy? I just watched the Risk Five from outside, but if I want to start, what should I buy to run Linux? Okay, so the question was, what Risk Five board is good if you wanna run Linux? So that's my interest, Linux. If you wanna do microcontrollers, there's a lot of options, less so when it comes to Linux because you've only recently got an application, as we'll see, that can run Linux. So let me jump forward. So the two, this is the Milk Five or Milk V Pioneer box. This is the one that's kind of more like a server. I'm gonna skip ahead because this was the other one that I think right now is quite interesting. So this does start as shipping. I think I got mine in April or May. So this one's very interesting because, now this is from their website. I don't know how true these are, but I've seen other people report that it's maybe two thirds the performance of a Raspberry Pi 4 for some benchmarks. So pretty good, because traditionally in Risk Five, we were very low in terms of performance to compare to other architectures like ARM in terms of the SOCs that existed. So this one's actually, I think, performs well enough that you could do some interesting things with it, and it's relatively affordable. So it's $120, I mean, with shipping, it'll be a little bit more. But a lot cheaper compared to like the PSI-5 dev boards that were always quite expensive. So I think this one's quite exciting, and it's actually a module that goes into a carrier board. So it has a lot of IO, so I would recommend picking up this one. I just got it. Now, you know, the story in terms of upstream is not there, but it's cheap, and I think there's people already working on it. So I think by the end of the year, it'll probably be in a much better position. But yeah, this is one I would recommend taking a look at. And then the other one here, which you can actually apply for right now, and I guess one thing, so let's say you maintain a certain software project and you want to port it to Risk Five. So when you fill out the application, you mention what your area of interest is or what your project is. So let's say, oh, I maintain, like I was talking to someone who does open mandrake, so let's say you want to work on the Risk Five port of a Linux distro. You can put that in the description. That's probably a pretty good one. So if it's a project like that, you might get picked. So you fill out the form and then they pick certain number of people. I think they have 50 of the 64 core Pioneer board that they're going to give out. And this one I'm very excited about. So traditionally with Risk Five, like we didn't have any sort of high performance compute, nothing that you could do native builds on. So everyone's either cross compiling natively in QEMU on a x86 machine. So this one I think will finally make it possible to start doing native builds, which for example, like Fedora needs to do that for Risk Five to become official architecture. Any other questions or comments? Yeah, back there. Oh, can we get the microphone? So short supply and not as cheap as some of those, but if you are really looking for something, we have a number of things in the work. So see me after the session and get my contact info and we can talk about, you know, and keep you in mind and sync people up on boards that are going to start coming available in the summertime here. Yes, so I didn't actually have a slide for it. There's actually like, I mean there's a lot of dev boards out there right now. One of which has been announced at the Risk Five Summit back in December in California was the upcoming sci-fi board, the high-five P550, which is a much higher performance core than what's currently in the sci-fi boards. And that's actually being fabbed by Intel. So it's quite interesting that this one will be made on a modern Intel process and it will have PCI Express and DDR5 using like proper Intel files. So that one's pretty exciting. Glass I heard was sometime summer. So well, you can talk to that gentleman over there, maybe. I just picked up a Pine 64 Star 64 for $89 US and plus shipping. So it was pretty reasonable. It was in my playground price budget. So it was fun board just arrived two weeks ago. Yeah, yeah, definitely. So that one has a SOC from Star Five. So very similar to this Star Five Vision 5 II, same SOC, but different form factors, some different peripherals. So actually like I would say right now is quite an interesting time. I gave this talk or I think we did a similar boss back in Dublin and there was much less options back a year ago. So I think it's seen quite interesting now for Linus capable SOCs in risk five. And I think going into the end of this year and going into next year, I think there's going to be more and more options. Hopefully ones that actually have things like the vector extension and the hypervisor extension. So like from having talked to SOC vendors, it typically takes about like two years from when risk five extension gets ratified to when we see it in like production silicon. So like the vector and the hypervisor are ratified at the end of 2021. So maybe towards the end of this year we might see SOCs that have those. So I think that'll be quite interesting. Yeah, and if you go on the developers board's website, I just put the two that they're accepting applications for right now, but they've done a bunch in the past, including sci-fi and star five and a bunch of other ones as well. And also if you go to risk five.org, there's a place on the website where they like talk about all the different dev kits. Cause in addition to like Linux capable stuff, there's also lots of microcontroller boards as well. So yeah, I gave a talk about Linux on risk five last year. Most of that's still current, but of course there's been additional capabilities and some of these newer SOCs have come out. But what just happened at the beginning of June was the risk five summit Europe in Barcelona. So there was a lot of interesting talks there. Unfortunately they've not been posted yet, but if you keep an eye on the risk five YouTube channel, they should be going up there hopefully soon. There was a lot of interesting stuff that happened at the summit. And then there will be a summit coming up in China, I think soon this summer, and then there'll be the traditional risk five summit in November in California. So I think one thing that is important to understand with a risk five is that risk five is not an open source processor itself, it's just a specification for an instruction set, but under an open source license. But to me the thing that makes me excited about risk five is the fact that if we have an open instructions that are an open specification, then you can make open source implementations or an open source processor. So that's the thing that I find really exciting that someday we could have processors that we're using on our single board computers where the core is actually open source. So with risk five, there's a lot of open source cores that are available. Some of them coming out of academia, like rock and a boom from Berkeley, at ETH Surge, they have a team there called Pulp and they've produced a lot of open source cores, some low power, tiny ones, and also some larger ones that are capable of running Linux. Any other questions or comments? Yeah, we have one in the back. Yeah, so risk five sounds pretty exciting and what concerns me, however, it's, as you mentioned, it allows to be open source processors. However, if you look at the SOC market on risk five, it's more or less similar to what's in the arms space only with different cores and I'm concerned that we will run into the same issues with IP blocks still being closed and upstream support being less than a priority for SOC manufacturers. So what's your feeling about that and do you feel any progress regarding what the situation we had in the arms space previously? Yeah, I mean, it's definitely a good point that is risk five that much different than ARM given that a lot of the cores that are being shipped, a lot of the risk five chips that exist right now, most of them have proprietary cores. All the peripheral IP is also proprietary and depending on the market that the SOC vendor sells into, there may not be like public technical reference manuals but I would say the big difference with risk five is that it is an open standard so it is possible to make open source implementations even if that's not the thing that's common right now that we see in the market. In terms of peripheral IPS, I think this is very important as a kernel developer, like it would be wonderful if more SOCs could use open source controllers because then we would have the register definitions and we wouldn't have to go through these levels of obfuscation, right? I think that's still a ways off but there are groups I'll show in a little bit that are working on trying to do various controllers that you would need in open source. Now, it's kind of like 10 to 15 years ago technology at this point but hopefully it'll improve and it'd be awesome if these things that everyone needs like PCI controllers, why don't we have an open source PCI controller? I mean, it costs money but also licensing these over and over again from IP vendors is also expensive too so I think we'll start to see some movement in that area and actually open hardware group or open HW group, right now they're working on taking the designs from each search and making them into like verifiable IP that you can use with confidence. They're focusing right now on cores but long-term mission is to also do controller IP as well so all the things that you would need in SOC but it takes time and they're working incrementally on that. Similar thing with OpenTitan which is a looking root of trust. Several different companies including Google have been involved in that and they're trying to do as much as they can with that as open source as well. Of course, if you wanna make something that's high performance, you tend to have to use search and proprietary bits but I think there'll be progress there over time. Mm-hmm. I have a question from a remote participant. What FPGA have you personally tried for RISV cores? Which combos did you like best and why? Okay. Same question for the participants. Yeah. So one thing that reminded me of at the beginning here is a tiny URL that'll take you to these slides and there's lots of links in them. I also have lots of slides because they didn't know what we wanted to talk about necessarily so if you download the slides there's a lot of stuff in there so I'm gonna jump forward to the FPGA part right now. I also uploaded them to the SCED page so you can find them there as well. So I actually had a bonus FPGA section. So one of the things that's important to know this is different from when I learned FPGAs in like the late 2000s is there are now open source tool chains for certain FPGAs. So the one that I've used personally a lot is the ECP5. It's good enough to have a soft core that can run Linux so I thought that was interesting. And now even some of this High Link Series 7 also has an open flow. There is a project called F4PGA that kind of tries to pull all these things together so that's a good resource to check out if you want to kind of know what's happening in the role of open source FPGA tool chains. The other thing that's nice is that Python is becoming a popular language for doing hardware descriptions. So instead of using Verilog or VHDL you can now use Python. There's a project that was called Megan which has now been replaced by a project called Amaranth but the idea is doing your hardware definition language or HDL in Python. And for me I thought that was quite neat and the way I was able to run Linux on FPGA on the ECP5 from Lattice using an open source flow was with Litex. So Litex is a framework that's built on that Python language that allows you to pull together all the components you need to make an SOC that would get put into the FPGA. So specifically there's a project called Linux on Litex Vest 5 that puts a 32-bit Linux capable core into an FPGA along with all the other things that you might need. And the DevBoard I used was a conference batch from the Hackaday conference. So that's not very useful if you weren't at that conference but there is a couple open source hardware DevBoards with that FPGA. So one comes out of, I think it's Croatia called the Radiona and you can get that on Crown Supply or on Mouser now. And the other one is called the Orange Crab and I think that's available from a company called Group Gents. So both of these could run Linux on a soft core on an FPGA and using all open source tools. Any other questions? All right, let me go back to the, where we were talking about RISC 5. So yeah, one of the things I was talking about was the fact that because RISC 5 is an open standard you can have open source implementations, open source cores. There's ones that are FPGA friendly as well. I talked about Vex RISC 5, Nax RISC 5 is similar but a lot of higher performance is out of order, so higher performance core design. Now one of the things that's quite interesting so I talked about like that Milk 5 board had an SOC from Sofco and it actually has a core from Alibaba Teahead. So Alibaba Teahead is an IP vendor. They design mostly cores and they release the RTL or like the Harbor Scription Language for some of their cores. Now it's not necessarily the exact same RTL that was shipped in like those commercial SOCs but it's quite interesting and it's on GitHub. Whether or not you can take that and synthesize it. I think some people have actually been able to run it on FPGA as a soft core but regardless I think it's kind of interesting and hopefully we see more of this in the future. There was another project that's a high performance open source core coming out of the Chinese Academy of Sciences and Dr. Bao actually gave a talk at Barcelona which is not online yet but the talk from two years ago is. So it's quite interesting, they're targeting like pretty high performance with this open source core so like there's nothing you can buy yet but hopefully this will be used by industry and you might show up in an SOC that you could then purchase. Now one of the things I think is super interesting is the idea of doing open source all the way down to the transistor level. So the actual like physical transistor cells and one of the organizations that's kind of driving this is the Free and Open Source Silicon Foundation or Fawzi Foundation and they have a monthly newsletter. Has anyone heard of Fawzi? Okay, a couple of people. So if you're wondering how to keep up with like what's happening, this monthly newsletter is super useful so I recommend checking that out and kind of big news that happened back in 2020 was that Google and a company called eFabless got together with a fab in the US called Skywater and open sourced the PDK or Process Design Kit. Now this is actually like all the information of how like the transistors are actually constructed, all the data that normally is proprietary so even if your Viralog or RTL design for your core is open source, which you actually get fab is always proprietary because you have these, this proprietary information from the fab about how they lay out their transistors. So this was the first time where that information was open source. Was anyone done anything with the Skywater? Last time I gave this someone actually had designed a chip on the project but had anyone heard of the open source PDK before? Okay, two people, okay. So and then this has progressed, there's now 90 nanometer. So this is like probably like 15, 10 to 15 or more year old technology, but it's exciting because I think we'll see more of it in global fondries, which is a very big fab. They do like IBM and AMD I think and they have opened up 180 nanometer, which is quite old, but I think we'll see it continue to get smaller if they see the benefit of it. So I think that's quite interesting. Any questions or comments? All right, and then, you know, I don't have any background in chip design. So if you don't either, there's a course called Zero to ASIC that it's kind of targeted to our software engineers that want to learn how to design chips. And that's a great course that can take you through the full process. So you could actually design your own chip and get it taped out or fabricated with this open source process that they have at Skywater. And if you don't want to go that in depth, there's actually a program called Tiny Tape Out that allows you to design your own simple chip in your web browser and get it made. And it's relatively, not a very large number of gates, but it's enough to do like a little interesting kind of toy project. And for $100, you get a dev board with the chip put on it. So I might try that. The next one is September. Any questions or comments? Anyone want to design their own chip? You got a question there? You know what platform is it teaching on? The Zero to ASIC. Which platform? Yeah, for the actual design. So they use, actually there's a kind of, they call it a flow, a design flow of tools that they use to do open source chip design. So let me actually skip ahead here. Oh, this is a good slide. So the overall flow for the open PDK with the SkyWaterFab that eFabless does through that program that Google has been sponsoring is called Open Lane. So that's a collection of tools from like the thing that synthesizes your RTL, like your Verilog code. And the thing that does like the place and route and the physical layout. So it's kind of a suite of tools or a continuum of tools. So there's kind of like this, actually I don't know if you can read it there but that table on the left is kind of the list of the open source tools. So for synthesis, like we have YOSIS and then there's a couple different options for place and route. And then for like the physical layout, there's a tool called Magic and there's another tool called K-Layout. So these are kind of like the, for each category there's an open source project that's starting to gain a lot of momentum. So yeah, sorry, it's a little small there but if you download the slides you can see a little bit closer I think. But actually I think I have one here later on. Oh yeah. So this is actually a pretty good, yeah so I was telling you it's called OpenLane. So yes, there's a couple different tools that people use. So in terms of the synthesis, how it turns your code or your HDL into logical like kind of a circuits that it can then place and route is called YOSIS, which stands for Yet Another Synthesis Program. And then there's another suite of tools that's part of another flow called OpenRoad. So it does things like floor planning and placement and routing and there's several other levels there of things you have to go through. So those are in the parentheses or like the names of the programs that are used for that. And then that finally outputs a file called a GDS2 file and this is actually like the geometry or the actually like the graphics for the lithography mass for all the different layers. So did that kind of answer your question? So the thing that's I think really unique here is that eFabless and Google got together and convinced the Fab to open up that information. So actually last weekend there was a hardware conference in Portland, Oregon in the U.S. where I live and Mohamed Kassem from eFabless, he even talked there about how design and fun you're custom-asic in three months. And I like how he used an AND gate here to talk about all the things that needed to happen for you to build like useful open source chips. And a big part of that was having both the EDA tools that were replaced the proprietary tools and then also having IP blocks. So we talked about that earlier like beyond the cores are there other groups are working on things like controllers and things like that and there are but it's still pretty early days. And then also the process development kits or the PDK which is the thing that actually has all the specific physical information and the design rules for how you design transistors for that Fab. And the original SkyWater back in 2020 and now Global Foundries has joined and just recently IHP which is a Fab in Germany also has opened up PDK as well. And if you download the slides the conference last weekend that Mohamed spoke at was live streamed so you can go check out the video there. And this is kind of like the most up-to-date thing in terms of the open silicon thing because it just happened last weekend. One of the things I thought was interesting here let me go ahead is from this open MPW or the multi-project way for that it was been sponsoring. 60% were first time designers and they said one third people identified as software devs so it's been getting a lot of people that don't come from a chip design background to actually start doing chip designs for the first time. And the MPW stands for multi-project way first. The idea is that they take all these submissions they do like 40 designs every quarter and they put them together, group them together like you can see here like I think this is like 40 projects that were put together and then that becomes something that gets image on a wafer to produce the chips for the people that were accepted into the quarterly run that Google was sponsoring. And you can see how it's gone up a lot over time. So the first one, they have basically capacity for 40 so the first one they had 37 but very quickly they started getting like way more submissions than they had capacity for so it's become like quite popular which is pretty cool. So I think when they launched this there was skepticism that there would be 40 designs every quarter that people wanted to get fabbed with the caveat being they had to be open source and they had to be done with these open source tool flow. So actually from the Linux angle one of the things I thought was really interesting on this second multi-project wafer run that they did was the E5. And the interesting with this is it actually has a SD RAM memory controller. If you click on, if you go to the slides and click on it you can find out more information about the project so it's just an 8-bit SD RAM but to me it's quite interesting and I think with further process nodes you could probably do more higher performance but with this we can have DRAM which means we can run Linux. The core that he implemented on this was a more basic core but you could see especially on the 90 nanometer with SkyWater you could do a more advanced core and have DRAM so you could actually do like your own Linux computer which I think would be pretty cool. Going back to the previous slide. Yeah. Do you know how many silicon chips they actually manufacture for you when they do it? Like you really get just the one? Yeah, no it's not just the one it's on an order of like a couple hundred. Oh okay so they really do the whole silicon for you? Yeah so that with the open MPW so when they accept like the 40 projects every quarter I think you get like on an order of a couple hundred chips. Okay. But then there's some kind of smaller versions which is like another one which further subdivides it so it takes like would normally be one project in the MPW and then divides into a bunch of smaller projects so with that one I think you only get one chip but it kind of depends and then because they were getting way more than 40 designs eFabless started a new service called Chipping Night so this one's not free of cost but it's really cheap compared to what you normally would be doing for prototyping chips and the advantage here is you don't have to hope that you get accepted because there's a lot of designs now so there's been like universities and companies that are doing like design classes they wanna make sure everyone in the class gets the tape out then you can do this and really it's not that expensive if you have like a group of people you're doing it with or if you're a company like I know $10,000 seems pretty expensive but it's actually super cheap and you don't have to pay for any CAD tools because this is open source flow and then so yeah you can see here that you get in this case you get either 100QFN or 300 chip scale packages and then you get five debt boards where those are actually put down on and then I guess the rest is for you if you wanna do your own packaging and last weekend I was talking with Mohammed and they've been thinking about other ways of doing this to make it cheaper like for example taking the chips and having them like chip down on the PCB or something like that or like wire bonded directly to the PCB or something like lower the cost and make it quicker because actually the packaging adds a lot of time to this process so they're trying to think of ways to make it quicker and then the other thing I wanted to talk about was so not everyone has like several months they wanna spend on designing something that would get selected out of the 40 available slots right you know we don't all have something that's like novel enough that it might get accepted so Matt Van who's the person that was teaching that zero ASIC course he realized there's an opportunity there to like take what would normally be one slot on the NPW and subdivide it into smaller projects so he created this thing called plenty tape out and there's a great website behind it that takes you through like all the kind of basics behind out chips get made how transistor cells are designed and that sort of stuff and the coolest thing about it is actually runs in your web browser because it uses this sort of graphical system called walk we see you actually you'll see like graphically in your web browser you'll see like the transistor cells like that sort of like physical layout and you can design it and you see like the cross section as well and then it's actually gonna run a simulation software spice to be able to show you like what's happening as you draw different shapes make them different sizes and stuff like that like this is super cool and it's all happening inside your web browser though if you want to do it in HDL like Vera Lager or something like that you can also do that but it's only about a thousand gates so but there's still I think interesting things you can do with a thousand gates and there's really like it's cheap it's a good way to kind of experiment especially if you just want to spend a weekend instead of like three months on the project it's like these are some examples of things and you can see here an 8-bit counter takes up some space but there's still like a lot more space to do stuff so I think people of you and like put a little risk five core into a thousand gates so there's ways to do that if you want to get clever so for this one it's $100 you get your one ship on a PCB and then you can pay more to like get more if you want and yeah the idea here is I guess they divide it by you know they take what would normally be like one spot on the MPW and then they divide it up and comes out to be you know something that might do is like your hobby project for the month or something like that and then this is what it looks like so it would be the footprint there would be the wafer scale package would be put down on that so you get a dev board with all the IO broken out so you can experiment with your design and the way it works because all the designs around this chip is that they have a way of muxing it so you select you know you'll have information you select these pins to get your project right but the cool thing is because they're all open source you actually get a data book that has all the projects in it so you might you have your design but you also have all the other designs they were part of that tiny tape out as well so there might be an alert design on that chip that you want to play around with too so I think this is super cool it takes it from like a year long process to like a weekend you know we had a workshop after the RISC 5 Summit in Barcelona and several people designed and it takes a while but I think it takes about a year for this process because it's so inexpensive but you know you spend a weekend design a chip and then a year later you get a board with your chip on it so pretty cool any questions, comments? we have one back here I was wondering what's the state of low power RISC associates and RISC processors? yeah, yeah, let me go to the one where I had about the cores so a lot of the primary work was actually done by ETH Zurich so this pulp team there it actually stands for parallel ultra low power so they are really specifically focusing on doing super low power designs even like energy harvesting and stuff like that and I think one company took some of their work I think they're called green waves I think there are so I think their processor is the GIP8 or GAP8 and that's a super low power RISC 5 core that's now being used in industry but a lot of the research they do there ETH Zurich on the pulp team is based on low power and I didn't focus on it too much because I was thinking about Linux but there's a lot of RISC 5 microcontrollers out there and I think power is one of the areas that some companies are hoping to differentiate in any other questions? We have three minutes three minutes for any other questions or comments I think we have another one back there so I wanted to put in a plug for the RISE project that launched about a month ago so a bunch of member companies that are working on upstream improvements to the stack to improve open source software so Linux, the copilers and so forth so the Wiki is now publicly available you can go to wiki.RISEproject.org Awesome, cool I had a meeting with Andre Workington who's the chair of the technical steering committee he told me that they had voted to make the Wiki public so I'm excited for that It just went live yesterday It's RISEproject.dev, right? Yeah, so this is what we were talking about, yeah So Wiki. Oh, Wiki. Okay, here we go A live Wiki demo Any other... I can't type here Well, Google saved me there They've got a whole number of working groups underway now Yeah, so check this out I think one of the ideas there was there's a lot of gaps still to be able to have a fully functioning RISE 5 server, let's say and the idea with RISE to try and have vendors work together more closely so you don't end up re-implementing the same thing multiple times So I will check out this Wiki after my talk Oh, here it is, yeah So there's like compilers and tool chains and the one I thought was quite interesting was firmware because I know there's now a lot of people that are looking at full UEFI and ACPI implementations on RISE 5 and there's still I think a lot of gaps there so it'll be interesting to see what comes out of that Any other... I mean, we have like one or two minutes left Any other questions? So I have a question So we have CPUs now Yeah Are there any GPUs planned? Graphic units? There is a working group or I should say a special interest group in RISE 5 International for GPUs and I think they have like monthly meetings So I think it's still pretty early days but there is a group within RISE 5 and National is working on that So yeah, check that out You can just go to RISE 5 Actually, you go to the RISE 5 Wiki Wiki.RISC5 or RISCV.ORG and you... probably if we search for GPU let's see what happens here Not much, but... The other thing you could do is there's a groups.io for RISC 5 That's where all the... Sorry, it's the list.RISCV.ORG So all the different task groups and working groups and everything at RISE 5 they all have pages on here So if you go on here and look at the topics I think you might find... Let's see, subgroups GPU I thought there was one Anyways... Oh, there's a graphic sig Yeah, okay So there's siggraphics So if you go to list.RISCV.ORG and check out siggraphics I think there's some information about GPUs in there Otherwise, what you can always do is email help at RISCV.ORG and they'll try and find you and they'll be directed to the right place We have one minute left or maybe no time left if there's one last question or comment Alright, it looks like we're all clear So thanks for coming and have a good day