 Ie, yna'r ysgrifennu, yna'n gwneud o'r horddweithio ar y dyfodol. Felly mae'n gynnwys ar y dyfodol. Felly mae'n gynnwys ar y dyfodol ar y architektur. A'n ddweud o'r ddweud o'r ddweud o'r ddweud, o'r ddweud o'r ddweud o'r ddweud o'r ddweud, o fewn y cyfrif. Felly, yr horddweith yw... ...rhywbeth ystodol MCUs, yma sy'n teithing a'n creadu i ni fyddion oswn. Erdych chi, mae arbennigwn i'r cyfrif. Felly, mae'n cyfrif o gwneud i ddweud i â'r cyfrif, doedd y cwylio ar gyfrif o'r du. Yei fod adroddau i'r cwrw, sydd wedi gweld angen, mae'n cyfrif o'r cyfrif o'r cyfrif. Felly yn cyfrif, mae'n ddweud o'r ddweudio ar gyfrif, yw y fflashau wrthyn nhw, yw ymdegwr wrthyn nhw, mae'n gwelwch ar bobl yw errwyntfyr hynno. dyna'r ffordd, ac mae'r cyfnodd cyfnodd rhai i'r iawn, y PIMIC. Mae'r archwcheg yw'r cyfnodd yn fawr yn ymddiadau ymddiadau'r MCU yw'r cyfnodd yn ystod yn yr ST. Yn y dyfodol, mae'n gyfnodd yma, mae'n cyrchaw ar gyfer ymgyrch, Dyna dwi'n ddweud y Pwg 157, dwi'n ddweud y gwaith gweithio. Dyna dwi'n ddweud y Ddweud Yma, yma'r Gwyrdwyr A7, gyda'r 2 tympau cyllid, mae'n cyflwynt cyllid yma, ac mae'n cyflwynt cyllid yma. Mae'n cyflwynt cyllid yma, ac yn cyflwynt cyllid yma'r Cortex M4. Dyna dwi'n ddweud yma, mae'n ddweud yma'r unid mewn mewn gwirioneddol ac yw'r unid mewn gwirioneddol. Felly mae'r m4 Cortex yw'r rhan o'r ddaeth gyda'n ddysgu'r architektur yng Nghymru, mae'r FFWM. Rwy'r gwaith mae'r m4 Cortex yn rhan o'r rhan o'r ffunctiwnolau ystod i ddod. A yna'r gweithio, rwy'n ddigonwch ar y fflegol. Wrth gyd y meddwl i fod o'r ddaeth yn y ddiagramaeth. Felly mae'n ddiddio'r freisi, mae'n ddiddio'r freisi o LPDDR. A dyna'r ddiddio'r mefyrdd o fewn. Felly y system S-RAM, y MCUS-RAM, y back-up S-RAM, dwi'n meddwl. Felly ydych chi'n mynd i'r sgwrs internol i'r sgwrs yn y dyfodol sy'n cymryd i'r ffordd o'r ffordd. Felly ydych chi'n meddwl i'r sgwrs yn y dyfodol i'r sgwrs. Felly mae'r sgwrs yn S-T, mae'r sgwrs yn S-T M32. Mae'r cymryd i'r cymryd i'r cymryd i'r cymryd i'r sgwrs yn S-T M32 yn y dyfodol i'r sgwrs. Felly mae'r gymhyfodol. Felly mae'r sgwrs yn S-T M32, 16-bit, mae'r cymryd i gwaith motor, mae'r cymryd i'r sgwrs yn y dyfodol. Felly mae'r cymryd i'r cymryd i'r cymryd i'r sgwrs, mae'r omor, rydyn ni'n gael tro hwnnw o ddweud y gerd painu i 22 sefydlu, fel ydych yn fydd y fyddiol o'r ffordd o aelodion. Felly mae'r ddaxx ynddud i'r cymryd i'r cymryd i'r sgwrs. fel y cyd-dweud yma. Mae'r cyd-dweud yn ystod y gwasanaeth yn ddechrau'r bryhau yn ystod yng nghyrch i'w ddoch chi. Felly mae'n gwybod, L-32 cyd-dweud yn ystod, i ddechrau'r cyd-dweud, i ddechrau'r cyd-dweud, E-FANET, U-SBs. Mae'r perfforolio yn adrodd oherwydd mae'n gwneud yn ddechrau'r cyd-dweud. Felly mae'n nesaf ei ddweud efo'r E-FANET yw'r cyd-dweud, yn ystod y 10-100 o'ch ddechrau E-FANET. port there as hosts. You've still got the standard OTG device inside there, so the full speed and high speed, but you've got the hosting abilities inside there. And you've got a lot a few more over higher speed, higher performance peripherals, so the MIPI DSIs, the camera interface, the HDMI controllers, all those extra pieces are inside the device. Connecting all this together, as you can probably gather, is quite a bit of a task internally inside the device. So we have two different memory busses inside. So we've got a high speed Axie bus, which is the pink line. And then we've got a slightly slower speed AHB bus. Let's say there's not much difference in the speeds. As Chris highlighted earlier, each peripheral can work with both cores. The reason we've segmented it like that is certain peripherals are more optimised to work with the A7 and some are more optimised to work with the M4, due to the nature of each peripheral. So it's been separated out a bit. But as you can see, there is two connections at the top here. So if you do want the ethernet working with the M4, you can do. So it can be routed through the connections there into the M4. All right, you won't get gigabit ethernet, but you can still have standard 10100 ethernet running with the Cortex M4 inside the device. For system and security, these are the two sections I missed out on the block diagram earlier on. You've got all your standard clock control that you'd expect. So you've got internal RCs and the ability to put external crystals or modules inside the device. You've got the different power modes that you can put the device into. So there's a lot of power control still going on inside the device. And you can still have external interrupts. So it'll be either onto the A7 or the M4. You can have external physical interrupt pins going into the device. So that part is pretty much the same as the M4 side available to the A7 as well. DMA-wise. So there's multiple DMAs. So we have a master DMA, which is more associated to the A7, and then we've still got the standard DMA1, DMA2, which is more familiar if you've done anything with Cortex M-based devices. OTP fuses. So if you want to store MAC addresses, serial numbers, version numbers, things like that. So we have some OTP fuses available for you. They are used for other features as well. So some of them are for user functionality. So we'll highlight some of those later on, where you can put certain items in to configure part of the system. But other parts of the OTP fuses available for you to programme. And on the security side, first one is the extended trust zone, which is part of the A7 and provides the protection and access to certain peripherals only, and a particular method of accessing those peripherals. So if anyone tries to hack into your system, tries to jump into somewhere that's secure in the memory, then if you've not followed the correct entry procedure and things like that, it'll generate a reset or an error message inside the system. So for the basic security, you've got the OTP fuses where you can secure items. You've got the electronic signatures and things like that. Tampa pins. So I think you've got the free tamper pins on this device. The tamper pins will protect what you store in the backup registers, and you can also generate in arrays for the backup SRAM, which I think is the 64K part, I think. No, that's retention RAM. Sorry, retention RAM is 64K, backup RAM is 4K, and there are some backup registers that are dedicated. So if you've got cryptography keys installed, you will save them in the backup registers, which are automatically erased when a tamper happens. And other vital information you will store in the backup RAM, which can be erased. It's your choice. You set it up to erase the backup RAM if a tamper detection goes off. And then if you send in outbound transmissions, you've still got the standard cryptographer AS128256 available inside the device. So the memories. So as I said, there's a section of internal memory, and most items happen in the external memory. So the boot ROM is programmed by ST in the factory. So you can't influence that at all. It's hardcoded inside the chip. This is 128K and will get your device up and running. So it does some basic functionality to configure the device. In association with the boot pins, which we'll show you later, I'll show you what the boot ROM is capable of doing. Then you've got the SRAMs. As I said, it's all segmented into different areas. So we've got the backup SRAM, which is the 4K, which can be maintained if you want to have a low power base system on a V-BAT pin. You've got the retention RAM. This is 64K. This is primarily used for the message buffers for the intercommunications between the two cores. So between the M4 and the A7 side. So all these message buffers when you're transferring messages up are set up inside this retention RAM. Then we've got the system RAM, which is 256K. So that's for the use of the A7 side. And then you've got the rest of the SRAM, the 384K. That's for the use of the Cortex M4 for your code and your data. So the M4 has no flash. It's all run out of SRAM. So that's all part of the 384K inside there. So you can see there that all these memories can be accessed by all the cores, with the exception of the M4 has no access to the boot ROM. So the A7 has to boot first, not the M4. Then off-chip memories. So you've got your DDR, which is your standard interface. We highlighted that you can connect it to the M4, but we're highlighting that it's not recommended. You will get a performance penalty on your A7 if you try and use your M4 to read things from the DDR interface. Mainly because you have to slow it down so much for the M4 to actually do the read. So it runs too fast. Then you've got all the other memory interfaces. So MMC, quad SPI, and external memory bus. So FMC for NOR and NAND flash. So all of these can be used for any of the cores. Again, we don't recommend doing executes in place for things like the quad SPI for the M4 again, because again it will slow the performance down of the A7 if the A7 is using the quad SPI interface as well. But it can be used, but not really for executing place. For the DDR, depending on which package will depend on which type of memory you can use. So if you're on the two larger PIN packages, you can have a 32-bit interface DDR. If you're on the two smaller PIN count packages, then you will be limited to a 16-bit DDR interface. So again, as Chris highlighted, depending on which sales type you use, which board layout you use will also govern which TAB or DDR chip interface you can use as well. Memory map for the MP1. It's ARM standard layout. You've got to, what's it? X amount of gigabytes. So FFFFFFF. All the peripherals are dotted around. SRAM is down at the bottom around 2 million hex, or 20 million hex. The boot's right down at zero. And then each of the peripherals are in their normal defined areas that ARM have quantified of where certain types of memories have to sit in the address range. So there's no different there. It's all uniform addressing for all the areas. So there's no remapping going on. There's just a split there between which core can see what down at the bottom, but everything else is in uniform mapped and mapped. So the power side. So for the power side of the micro, there's a lot of power pins on the MP1. All of them powering different parts of the circuitry. We've got three real mandatory supplies. So you've got to provide a power for your VDD to DDR. So this is internal chip, not to the memory. This is the voltage that your DDR is going to be running at. The micro also needs to know what voltage that memory is running at. So the same voltage to your DDR chips has to also come inside the micro controller. Then we have the voltage for the core and it's providing all the power to all the core domain. And then we have the main voltage which is providing the rest of the device, like the IO rings or the peripherals and things like that. So they're the three particular voltages that you have to specify into the device. As I said, there's lots of other voltage pins. So there's analog pins as well that will need the voltages. Most of those were the same as the standard VDD, but you have the option of changing Vref plus depending on what type of analog signals you want to try and measure externally with the device. And inside you've also got different power domains. So we have the core domain, the main VDD domain, the switching domain. So when you switch them from VBAT to battery backup and back domains again, and all the analog side of things. So these are all the elements that you have to worry about when it comes to powering the MP1. So you've got two solutions. A lot of the time it'll be application dependent on which of these solutions you're going to go for. So if you're on a very simple project that's just got a Norflash, DRAM and the micro, you might decide discrete power is probably still the most efficient, most cost-sensitive way to go. So you've only got to generate three rails for the device. You don't have to do much playing around. You're not plugging in lots of other items into your target board. So discrete will be the way around. There are pretty much all other applications where you've got USBs, displays, other heavier interfaces like ethernet, Wi-Fi, things like that. Then the PMIC will save you a lot of time. So inside the PMIC we have all the different power controllers for the MP1, and then we've got lots of other LDO to power all your periphery devices. So if you're plugging lots of USB devices in and powering those USB devices, you'll need some power switches, things like that. If you've got the DDR memory, which is power in there, you also power the DDR. And then if you want to power the ethernet 5, things like that, you've got lots of other LDOs down there to power different items on your target board. And all you do is put in a 3.3 to 5 volt supply into this PMIC, and it will manage the rest. When it comes to low power modes, remember you have a communications channel between the micro and the PMIC, so you can shut things down inside the PMIC if you do need to go into power saving modes. So you've got nice flexibility and control over what the PMIC's doing. So internally you have all your power regulators powering the device, so powering the supply into the DDR, and then also powering the physical DDR chips externally. And then inside here you've got the power management, which is powering all the particular cores inside, and then sending some control information back to the PMIC to balance things out, switch things off as you see fit inside. So for power modes, there are multiple things to think about. So this is the system power mode, so this is everything. You'll see things also called C run, C stop. So that's the core one, so that's individual for each of the cores. There'll be a C run and C stop for the A7 and the M4. So this is for the whole system, so you can run, stop, and stand by and then pretty much go on to V-bat inside the system. Clocks will only ever go in run, and stop mode means you've stopped all the clocks to both the cores, not just one of the two cores. Stand by means you've switched off your voltage to your cores completely, and then V-bat will give you the lowest power modes that we've got available on the device. So the power consumption figures, so if you're in run mode with both cores running and the M4 running, you're about 350 milliwatts, then if you switch off one of the two A7s, or you're on the 151, you'll be about 275, and as I say, you can then drop your two A7s into sleep mode or stop mode and just keep your M4 running and you're down to 92 milliwatts. So again, depending on what you're doing in your application, you've got control over this on the fly, it's your decision to switch the power modes. Then if you drop down into standby, you're down about 36 microwatts. Remember this is the chip only, not including the DR in self-refresh, this is just the chip. And then if you drop into V-bat, you're about four and a half microwatts. So it can do a proper low power-based application, even though you've got that high performance when you're fully powered, you can go into some low power modes inside here. So we have a dedicated application note for power consumption, so that's on the web, and that'll help you with the power management side of things. As well as the power management one and the low power modes, we've also got the standard hardware getting started guide, so how you're connecting all the clocks, the reset side, and the power information. So we've got a dedicated hardware getting started manual, exactly the same as we have for every STM32. We've got the low power modes one, we've got the discrete power supply hardware integration, so if you're not using the PMIC, we've got an application note on how to do a discrete one, because again, the power rails have to come up at the right speeds, so there is a bit of power management needed to be going on inside discrete. And there's lots of information in this reference manual, I think it's about 4,000 pages long the reference manual. So there's a lot in there, as I say, we'll keep referring you to the wiki, because it's a lot easier to work with, but you do have that hard copy if you don't want to go reading through the reference manual. If you need some bedtime reading, go for the reference manual. So there's some of the other power consumption numbers that we've got, and then on which of the different modes you're in for the MP1 chip.