 Hello and welcome to this presentation of the STM32 system window watchdog. It will cover the main features of this peripheral used to detect software faults. The window watchdog is used to detect the occurrence of software faults. The window watchdog can be programmed to detect abnormally late or early application behavior. It is best suited for applications required to react within an accurate timing window. Once enabled, it can only be disabled by a device reset. An early wake-up interrupt can be generated before a reset happens to perform a system recovery or manage certain actions before a system restart. The window watchdog offers several features. The user can program the timeout value and the window width according to application needs. It can generate a reset under two conditions. When the down counter value becomes less or equal to 0x3f or when the watchdog is refreshed outside the time window. It can generate an early wake-up interrupt when the down counter reaches 0x40. The early wake-up interrupt can be used to reload the down counter in order to avoid a reset generation or to manage system recovery and context backup operations. As shown in the figure, the window watchdog uses the APB clock, or PCLK, as reference clock for its time base. The PCLK is provided by the RCC block. This clock is divided by 4096 and by a value programmed by the application. The application can also program the reload value of the down counter bits t6 to 0. The window width is controlled by bits w6 to 0. The WWDG is connected to the APV1 bus and clocked by the APB1 clock. The WWDG early interrupt output is connected to the position 0 of the NVIC. It is possible to select the hardware or software start via an option byte. In the hardware mode, the WWDG can be automatically enabled after reset. The window watchdog is frozen when the system is in one of the stop modes, but can remain active when the product is in sleep mode. The WWDG performs a system reset handled by the RCC block when a timeout occurs or when the WWDG is refreshed outside the allowed window. This diagram illustrates how the WWDG operates. When the 7-bit down counter rolls over from 0x40 to 0x3F, it initiates a reset. This happens if the application software does not refresh the WWDG on time. The early interrupt, if enabled, can be generated when the down counter reaches 0x40. If the software refreshes the WWDG while the down counter is greater than the value stored in bits W, 6 to 0, a reset is generated. This happens when the application refreshes the WWDG too early. No interrupt is generated in this case. To prevent a window WWDG reset, the WWDG refresh must happen while the down counter value is lower than the time value window and greater than 0x3F. This is illustrated by the green area. The refresh operation consists on reloading the down counter with bits T, 6 to 0. The WWDG can work either in hardware or software mode. In software mode, the application needs to enable the APB-1 watchdog clocks via the RCC. And set the bit WDGA to 1 in the WWDG in order to enable the watchdog. Note that once the watchdog is enabled, the application cannot disable it. Only a system reset can disable the watchdog clock. The low power enable bit can be set as well if the application wishes to keep the window watchdog activated even if the product is in sleep mode. In hardware mode, there is no need to enable the watchdog. The WWDG is counting down when the product is in run or sleep. The bits WWDGEN and WWDGSMEN are forced to 1 by the hardware. The down counter uses the APB-1 clock divided by 4096 and again divided by a division ratio selected by the application. This division ratio can be 1, 2, 4, or 8 as defined in the WWDG CFR register. The formula shown in this slide lets you determine the watchdog timeout value. When a system reset occurs, it is possible to identify which parts cause the reset thanks to status flags provided by the RCC block. The window watchdogs can be one of the sources. The early wake-up interrupt can be used in order to perform emergency tasks before the reset occurs such as data logging, data protection, watchdog refresh in order to prevent the reset or other emergency tasks. The EWI interrupt occurs whenever the down counter value reaches 0x40. It is enabled by setting EWI bit in the WWDG CFR register. The EWI interrupt is cleared by writing 0 to the EWIF bit in the WWDGSR register. The window watchdog is active when the device is in run or sleep modes. It is not available in stop or standby modes. In sleep mode, the window watchdog clock can be disabled by clearing the corresponding low-power enabled bit located in the RCC block.