 చాన్ చáisటిందారూ మారcknow겠 Scientists చి వాల్. టిసంటిందం క్లుటి ナింా 分. In this session of time-time, we will talk about RL-discourse to concepts that are a bit advance. And it would be, it wouldoute you well if you take your, get yourself some experiences working for గిలతోతోమో ఁన్తర్వుచ౔దువ్లతోచొ వినోమిన ny వనోడకిసిసి ప్భనైలి చర్తకి不好意思 . పయి మిలిల్, గావాయ౜ రౚల్డిల౔ మాలిల్చి పౌడ్. మిట్లాయాట్ మిపాస్ందూధా. సి. అంర్చేiggling�ామి సకేపృ ఇదారికారిహంను మాస్ట్ం. and using attributes we can write very powerful procedures to almost any kind of data that we want for the program, right. So, I will first discuss deeply about what do we need to need to check before fixing timing. So, the regular flow is that once the net list will go to the post layout stage to the layout stage where it will go to all the steps, placement, plot 3 synthesis, routing and so on. And at the end of the all the back end of the topic what you will get as an ST engineer. So, I am talking from the perspective of an ST engineer, the person who is now this person this engineer can also work in back end can also work in the front end design, but I will focus on the ST apart. So, I am assuming that may be either you yourself or somebody else is giving you the post layout data, post layout data is net list plus scale. Now in the industry many times it may happen that the back end tool used for post layout that is called placement and routing plus is not is different than it is not this an offset tool, it can be any other company like this tool can be magma, this tool can be a talk tag, this tool can be a cadence encounter anything else or it can be synopsis IP. So, these back end tools are geared towards implementing the design tool from the net list stage. So, the input to them is the output is again the post layout and the parasitic data, but these tools are not geared for sign off. By sign off I mean checking that you are meeting your time in time frame in every corner and every mode that is part of this protocol. So, prime time or gold time for example or your STA tool will be the sign off tool. So, all these checking ultimately will have to be done in this tool. So, it may happen that the back end tool is not same timing violation, but you are same time violation. It happens like that this is the problem is called the correlation issue between the your STA tool and the back end tool plus prime times timing engine is much more conservative it lets you lose so many things to make sure that you are on the conservative side when it comes to time in some frame. So, all the timing reports that you will see will be in the prime time you will make sure that all set up and hold timings all recovery in the world will also be perfect or they are meeting in prime time that is a sign off code. Now, so after the routing is done after you that the task will be perfect. So, the back end with the any back end tool they will try and fix most of the violation, but even after the first round of it you will be left with few hundred of even few thousand violations and now there are tools there are tools that are there are people have written or fit of scripts every industry is something industry will have its own fit of script or its own fit of script may be it may be it may be they will purchase a tool from so, they will have a set of tools which will write out timing issue to generate timing issue based on the compound on the STA tool is all and these timing issues will be again applied in back end and a new version of the database will be put out for timing. So, this is an iterative analysis obviously doing for solving all these timing operations normally is not possible. So, there will always be some tool or some productive that will do the job, but in the end you might be left with few parts which you will have to fix manually and analyze those reports in time. So, this so before checking before even going to the timing if you fix this whether few thousand parts are left or few hundred parts are left you have to make sure that the clock network is good to begin with. If the clock network is not good your timing does not make sense right because if you have clock clock skew issues if you have clock little bit too then the the violation that you are seeing will not be real. First the clock network has to be fixed make sure that you must make sure that clock relationships are well defined the clock skew is not high is within limits the clock divided logic for example should not be the clock they are just noted down as an important thing whether this is not a complete exhaustive list obviously. So, there are so all such such cases can create issues for you for example if the clock divided logic is part of the clock frame it is planning it will have a large way of doing things resulting to lot of violations. So, we have to make sure that clock network is good to begin with how do we do that we recheck are going to use the report clock timing command we do a good pre-layout STO and so on. Secondly we should check all the settings if the design is indeed in the desired mode you have to set some probably you have to set some pre-form it is supposed to be normal constant mode or if you are doing it. So, you will have separate set up constraint for function mode for scan shift for scan capture for memory business mode. So, for each and every mode you will have separate set up function then before even going to analyze set up and hold timing you should call most of the violation why because any DRC violation means that timing calculation is not possible. Now, let us see if there is a DRC violation on a particular set it would mean that any set up or hold violation through that set could not be relied upon because that DRC violation has to be fixed. So, thus more important are the DRC violations. So, then you can start fixing your set up and hold timing without solving a DRC violation, but first priority is DRC violation on clock network. If there are DRC problem on clock network you have to solve them first because any such fixes will again change your clocks to your latest and will have data at different time. So, first idea is to make sure that your constraints are 100 percent correct. Okay, yes you might be missing a few except whom the small things are okay to have, but not the big things like clock relationships, clock definitions are single most important factor in timing analysis. So, you should make sure that all your clocks are of correct frequency have proper relationship difference and then it comes to constraints. So, many times it may happen that during the fixing process you will come to know from the design analysis or something like that that your the path that you are fixing might be false. So, having one or two paths like that it is alright, but having a bunch which are false and which you are trying to fix will damage your data. So, first informas first informas spend a lot of time on your constraints. Now, let us say now you are left with few you are left with some violation set up a board. So, I will list down the steps that we can take to solve the how can you solve the set up violation if you are doing stuff manually. Obviously the inputs or the user tools will take care of that. So, what does it have what we automated ECOS engine would do with if we take all the reports all the modes it will take it will ask for the input will be the reports for all the modes and for all the panels. It needs to know reports or sessions whatever it needs to know what the violation looks like in different formats and does the path has enough margin to fix it so, but let us say if you are left with you are left with few paths that are not solving that you cannot solve by or that this software is not able to solve it happens all the time. So, there are few paths left which you have to fix normally and how do you do that. So, let us say if you are working on a set up in the path that is valid in set up first priority is always fixing the data path what is the set up path is the max delay problem what means is that part delay is more than the maximum permissible delay what do you do you try to reduce the part delay now the part delay total part delay comprises of the data part delay plus the launch of network delay first priority is always to speed up the data path so, you should look out for slower cells and replace them with the faster so, an example is that you can have a slower cell which is a higher duty which has a high duty and if you have a library which has a high duty you can choose to replace the cell by its SVP variant and the cell will become faster or choose a higher drive let us say you have a X1 drive of buffer which is giving you high delay you can choose to swap it out with a X4 X4 drive from buffer this will improve your part delay and you might meet the time so, again obvious so one thing to know about this is that some swapping can be would be put in some pattern in the sense that you take the same area like SVT to SVT swap a duty same area but when you swap from X1 to X4 the area will increase because the X4 buffer is of a larger area so, again any so also so, the timing that you so, this is the analysis that you can do within PT but the real results will only come when these ECOs are implemented in back end and new parameters are made so, whatever analysis I am talking about it is at best it is an estimation although most of the times it will work as it is you will not have so, if time time shows that the path delay has improved in majority of the cases the delay would improve very well actual at this point second the self driving the capture pin for example, S3 over X2 as wallet and setter policy and the these capture plots data pin on which there is a setter collision if it has a bad transition then it might be a problem because bad transition means even because the setter check of data depends on the transition of the data pin the data if your bad transition and data pin even the setter check constraints will improve so, it is you can again upside the driver or make the driver bit stronger or faster so, that the transition and the capture pin is good it will help the it will help into two aspects it will help to reduce the delay for that particular element then plus it will make the transition faster which would in turn make the setter constraint smaller the whole constraint will also become smaller because the setter constraints both are dependent on the clock transition plus the constraint transition this is the data pin second this technique is slightly more advanced you will understand this with some experience maybe let us say a buffer is driving a buffer has a maximum price term in the data part then it is driving less than 15 or 20 minutes so, now you cannot upside this because that is another maximum price term so, up sizing is when I talk when I say up sizing it means that buffer should be replaced only by a buffer it cannot be replaced by some other element because you have to maintain logical equivalency so, up sizing means the logic function remains same the drive or the VT typing so, here let us say you have a it is driving of 20 minutes this particular person and it is at its maximum price term you do not have more than drive term more than this available in the lab so, what do you do and it has more than because it is driving 15 minutes back end something back end can do load splitting you can do load splitting you can recommend the back end to the load splitting how the load splitting is done now this buffer will drive let us say so, we will add more buffers and this buffer was driving 20 earlier now let us say this buffer will drive 5 and among the 5 fan outs one of the fan outs will again drive 5 and so on so, you can add a buffer network there to split the load this will help speed up the data path so, the principle here is that if there is a long there or if there is a high fan out case like a buffer driving 20 hence so, if you add buffers at regular interval this since depends on the technology or the fan out number also depends on the technology your total delay would improve or yes you are adding a buffer a new buffer but the combined delay of this buffer network the idea is the combined delay of this buffer network would be less than should be less than the case where a single buffer is driving 25 so, this is a more advanced case the load splitting second more advanced technique is called logic loaning logic loaning is something where you have a cell which it has a green multiple form out and then this fan out this let us say AND gate it is driving with the 2 or 3 or even 5 minutes and one of the next is going to your critical clock to your to your software clock and now this AND gate will have more delay so, what you can do you can create one more AND gate a copy of it with the same logic and you can split the load so, splitting the load and logic loaning is somewhat similar in nature but logic loaning can involve more than one cell loaning of more than one you can involve loaning even the even the clock so, it is again as it is an advanced technique it is not done easily you have to do lot of checking in your in your time time you have to check a lot of reports report even attempting this third is do path days analysis if the number of violating parts are small you know let us say 5 violating parts in a particular program you can do PDA on that we saw an example in the lab and the WNS is less let us say if the WNS is 50 px minus 50 px and you are hoping that it will you can do PDA the longer the path with multiple input cells be probably the more advantage you will get out of PDA lastly you can play with the clock's view so, we were talking about the first priority the last priority is stretching the clock at the touching the clock network is not easy you have to do lot of checking before playing with the clock's view so, the concept is that you delay either delay the touch the clock or may be launch clock come earlier whatever you do it is going to affect let us say if you make the launch clock here it is going to affect the setup at this launch clock so, this launch clock if it has a critical path for setup it will affect the data of this clock if you are making the launch clock earlier it will affect the setup there if you are delaying the touch the clock it will affect the hold there so, you have to open up the session in the best case check setup in the worst case on the launch clock and so on you have to do lot of reporting before you attempt this and this is not a simple issue for even back end the back end probably have to do so, be careful if you are playing with the clock's view it should be the last resort the downside is that the faster you make the data path it might start affecting your hold which is expecting so, because the path delay has to be between an optimum and minimum limit and if you may start making it faster it will affect you and it will affect your hold it might it is not necessary that it will affect hold but depending on how the path is what is the path end how many smartphones are there and so on depending on these things it can affect negatively on hold now hold timing is can on some base on some cases it can be very easy in some cases this can be very very easy majority of hold violations are because of clock speed this is why in synthesis you do not worry about hold time let us say you are considering a single clock domain you do not have multiple clocks you have a single clock pre-layout you will not see any hold violations probably you will see very small very few hold violations maybe on memory page but when you go to back end when you go to the posterior database the number of hold violations will increase by a lot because now for all the smaller parts for part like chip processor such parts have virtually no combination logic between register to register such parts because of the clock skew because of the difference in the arrival timing in the clock latencies of the two clocks the hold violations will increase so this is again the reason why in synthesis you do not worry about the hold timing because you are not synthesizing for hold you are synthesizing for performance it will set up and there is no clock tree there is no clock skew in place there so we do not need to worry and such hold violations that will be a success simply you have to add some kind of a delay element which is either a buffer or a delay cell delay cell is just a point of a buffer with more delay and so the first thing that should be checked before fixing any hold is that whether the first priority is adding the delay at the end point so if you add the delay on the end point let's say if you add if you insert a buffer at the data point of the violating clock then you are made sure if you can add then you are made sure that even if there are multiple start points multiple clocks driving this logic then also the hold timing will remain fixed because we are fixing the end point probably this will not make sense now but when you start fixing when you start working on some real project so adding a delay cell or a buffer at an end point is the most preferred option obviously before that you should check whether the end point has enough slack for setup and how will you check it you will load the worst case session you will have to load the worst case session because setup is more difficult there you have to check whether there is enough slack before adding the delay cell for example let's say I am trying to fix the whole violation of 10 ps 10 people sitting and I know that a buffer of let's say some type x type will give me 10 ps also let's say 15 ps of delay so I know that okay fine I am with buffer and so this violation is in the past one let's say now you have to pass on or the best one at the worst case form I have a violation in the worst case form I see that the buffer will give me 15 ps the violation to be fixed with 10 ps I am good I can add this buffer but now I have to go and open up my worst corner session and report the setup timing to this now what is the margin I am looking for I am adding 15 ps delay in fast form but when this delay stays 15 ps in slow form no this delay will be more in slow form it can be 2x it can be 3x depending on the cell type depending on the technology now let's say so there is a factor by which the delay changes from best case form to worst case form so let's say the best case form is x and depending on the technology then you can work out the process you can start doing fixes so let's say I am the technology I am working on has a factor of 3 15 ps delay in fast form will give me 45 ps of delay in slow form so now in slow form I should be very careful if the path has atleast 45 ps of margin otherwise if I will add the 15 ps and if this the worst case corner margin let's say 20 ps and if I wrongly assume that the 15 ps is going to state the 3 ps in worst case form it will not work it will start violating so these are the three things be careful about multiple start points if you are not able to fix two violations of the end point if you are fixing if you are adding the buffer so the idea to fix hold is to add delay in the path you might add if you are not able to add at the end point you will add somewhere in the middle or at the start point that might not fix the violation because let's say there are five start points and one end point end point is violating in that case fixing at one start point will not help solve the violation the other start point can also be violated so be careful about what you want to fix and how you want to fix by checking before timing by using the minus inverse option that's the best option and use inverse option to make sure that how many start points are violating for a particular end point by default client time reports only one start point per end point so you have to be very careful in the usage of max pass and inverse you should understand the difference and use it always check set up margin in the worst corner this is the bottom line don't check set up margin in the best corner doesn't help you if the set up slack is what happens now what will happen if the set up slack is not sufficient what can you do what you could do is when the set up slack will not be sufficient when the set up slack is not sufficient but you need to be very careful because when the set up slack is not sufficient and you want to be very careful so you must make sure that the set up slack is not too strict and very careful that all these type of set up slack will not be sufficient because all the set up slack are very low the hold timing obviously the hold ocen the date will get worse might get worse than a small norm but you will get more margin on this. Again it is the idea here is that the delay in off-phoner width in compared to the slow-phoner. So here also the ratio of the delay first by the divided by the delay in fast corner. This is better for high drive and for low VT cells. This ratio becomes of the worst the ratio. So, the ratio is delay in worst corner divided by delay in fast corner. The worst the ratio is the more difficult to look on in fixing. Why because a small delay in fast corner will give you large delay in worst corner and you cannot fix the timing. So, the worst this ratio is the more difficult it is to fix time. The better the ratio is more easier is to fix time. So, this ratio is better for low VT and for low VT cells and not so good for high VT cells. Similarly, this ratio is bad for low drive cells it is good for high drive cells. So, by making the pass faster you are improving this ratio and you are giving yourself more time to fix time. Again, PVA can be used but for pass with less logic depth where the logic depth is less you will hold pass like that. Very rarely you will find a hold pass in a single plot domain which has more than 3 or 4 logic depth usually it will be smaller. So, the logic the smaller the logic depth the less margin you have in PVA. The PVA will not give you lot of advantage and sometimes it will not give you advantage. Again lastly you can play with the clock skew but be careful about it this is the last result right. So, prime time gives you commands gives you tools to resolve violations by manually editing the template and analyzing how the changes are found. This obviously this is only useful later in the design type it when only small you have only small violations to play with. That is whatever commands you apply you can write out an LCO file from prime time which the back end tool can read and perform the LCO for you. Whatever it is command time discuss I will be discussing now. In this lab they are used to only analyze the time use you try and emphasize the silence what effect does it have you can add as a currency what effect does it have it is not actually changing the net list you are not writing out the net list then you can probably assemble these commands whatever you applied or automatically you can enable ECO mode in prime time. So, the prime time will write an ECO file for you which the back end tool can automatically use. We will not go into a lot of operation details because this is a long process again I will just only explain in the concept here. So, this is these set of commands are used to manually edit the net list only temporarily in the prime time session you do not write out the net list and you can analyze time in the session system. So, this is a set of command you can the idea is you can the object here is buffer the task is you can add a buffer to solve the whole problem you can remove a buffer to solve the whole problem you can change the dry strength of a cell it is called high cell you can even create in a a new cell you can create a new instance of a particular cell you can rename or remove a cell you can create an edge you can connect it. So, these commands are similar to the net list editing commands in business but the idea here is to analyze the time you will see some example in the lab in the same session. So, this command so, to before doing a high cell you should know that what all dry strength are available what cell types are similar. So, when you with when you want to replace for each cell you need to know the alternative library cell that you can use. So, this is the library cell base case you can use this command get alternative with cell and in a base name command is an example. So, if we want the alternative lip cells of this particular instance you want so, it gives us this complete list. So, this is the list it gives us this is the list so, this is the list it tells us that there are two cells called a n 2 and a n 2 are it. So, this was the theory of what is analysis we will have some examples in the lab. Now, let us talk about a more powerful feature of time time called object attributes and read it from the slide. An attribute is a string or value associated with an object in the design. What is an object in the design the object can be anything port, pin, cell, instance, net these are all objects clause all these are objects. If you remember we discussed a figure in which I showed you the different objects in the design. Now, an attribute is a string or a value associated with an object in the design that carries some information about it also. For example, the number of pins attribute attached to the object cell indicate the number of pins in the cell. How does how do these attributes help us we can write now we have some attributes defined there are also something called user defined attributes where you can define attributes yourself we can write programs and tickles to get attribute information if we use it to write proper program. We will I will write some snippets of code I will give you some examples also we will try this out in the lab also. Now, report attribute here for example, report attribute minus application and you tell what is the object you give it the object and it will report the attributes for you we will try this in the lab. So, this is the example tells that get cells particular cell clock slash clock month slash this clock buffer and I am giving this this particular object which is of a cell type. So, every object has a type the object this is this is a get cells command the type will be a cell I give this argument to report attributes minus application which will give me what all attributes are applicable available for this particular object. Example 2 let us say I am I want to know the count of count and instance name of all the SVP test in the designer. So, size of collection I have shown you the example here so, get cells by a hierarchical minus filter this particular command do not worry too much if you do not understand this amount you will understand from all of it obviously. Get cells with get reader list of cells hierarchical means go down the hierarchy complete design filter means that again this is using the attribute rest name is an attribute on cells which will give me the value of the reference name of the cell name right. So, if it matches SVP start let us say assuming the library has cells which are starting with the name starts with SVP this will give me a count of all the SVP cells I can write a for each command of a for loop on this and I can write out this echo echo get attribute myself full name will write out these full name of this cell it will write out the full instance path the second get attribute is the writing the rest name it will write the rest name for this means an example of attributes. So, using attributes the idea is attributes will help us in writing powerful prime time procedures usually so, even design compiler supports attribute some attributes may be different between design compiler and time type in some of it because the aim of these two tools is this bus, but you can use it number one. Now, I will move on to the last and we will discuss some examples. So, I will restore a session on which is on the same design that we discussed last time orka I have saved a session already I just to remind you there are these clocks I change the frequency of some of the clocks to get more set up volition which will so we can analyze the set up volition. So, these are the clocks if you remember from the last class in P clock SBI clock this clock this clock 2S. Now, let us let me look at the let me look at the what is the worst case in one of the clock domain I will do report timing minus most bit when we look P clock let us say let us say this is a set up volition right. Now, set up volition I am assuming that my constraints are correct I am assuming that my clock definition everything is correct I will now try and do a what if analysis on this. So, I will look for cell I will just expand this minus input points. So, if I look at the data path I start from the start this is the register now there is a delay cell here I you can you know by experience this is a delay cell DL something 2DL the delay is 2.26 again there are some some cells AN 0 and ND 2 and all that, but in this report I can see easily that this delay cell is the one that is taking more delay it is taking 2.26 now usually delay cells are not part of synthesis synthesis DC they are usually do not use so DC will never use it delay cell so this delay cell as the name suggests I am just saying from experience it is not it was not part of this synthesis it is it was inserted during PNR and probably most probably it was inserted to solve the whole time. So, that means there might be a whole timing path through this let me just verify it I will do report time so I am planning to play with it so I will do a report time through this particular cell this particular pin and I say minus delay menu ideally you should do this in a best corner not the worst corner itself if I want to use see the whole margin you should try and see it in the you should see it in the best corner session not the worst case form you should see it in the fast corner but just for since I am showing you as an example we will look in the same corner but I hope you get the contract now see from the same start point here the start point is same count interest 0 here the start point is same there is one more path through this which goes to memory and there is some whole thing here now see 1.74 here and now the slack is 1.57 in the fast corner this delay will reduce by a lot this delay will probably be 500-600 pf 0.5-0.6 and there might be a violation or a small positive slack in the hold report so now consider I remove this consider you remove this then there will be a hold timing violation here so this is where you should be careful in deciding if you are doing a fix you should think about hold if you are doing hold fix you should think about set it is not straight forward that you will speed up any cell or remove any cell or add any loss or any loss so see that this delay cell is here for a reason see that the fan out here is fine that means this is going whenever you see fan out more than 1 there are alternate paths available I see that this was inserted to solve a hold problem on the memory I see that if I remove this then here the problem there will be a violation here but let me assume let me just change the state to something else and show you an example so ultimately you should understand that what you should check for when you are fixing that up what you should take for when you are fixing hold so as an example what I will do I will just size this I will resize this now a delay cell so this is command size cell and I give the new cell time now usually delay cell and buffer size cell only works between similar between the same function so a buffer and a delay cell will only be compatible if they have same function you cannot size a buffer into an inverter let us try this command which was suggested in the flight get alternate lib cells minus l get alternate lib cells minus base names and I will give this delay cell sorry I will give this so it gave me a big list that all these cells are compatible see delay cell here dl is compatible with buffer so this is for the experiment I will size this let us show you the usage of the command I will size this I am sizing this to let us say I am sizing it to both bd now I have changed the net list I have to do update timing it will do something some time in time and now I do again the report timing through the same cell now this cell is both bd1 and c I have size this to buffer and now it is violating hold but it will solve the second it will solve the second so this is how you use the size that I have to do but I have size a particular cell which I should not have done but I hope you will be more careful when you do finding all of this this was the example of size cell this is how you do water analysis let us try and solve this whole violation now let us try and solve it now what I could do is I know that this if I so what I will do is so here the problem is something here this is some problem now I see it is the fan out here is size now what I will do the hold violation is here I want to see the set of slack here because there is a 110th hold there is a yeah 110th is minus 0.11 is the slack here I have one before fixing this so the first priority is to fix the end point before fixing at the end point I will see what is the set of slack again the set of slack you should always see in the worst corner we are already working in the worst corner this hold violation will be more the WS will be more in the best corner let us do a report timing minus I will do this particular end point because I am planning to add delay so there is lot of slack here atleast this session is concerned there is lot of slack so I will add a buffer here how do I add a buffer I say insert buffer I will do minus help so this buffer has a delay of 0.15 and the violation here see now the delay here is 0.15 put it at report but the delay is 0.12 for the hold report because of the delay set of report it will shoot more delay more report it will show less delay so whenever you are trying to identify which self to add or which self to swap we should take into account the margin so let us say I want to add X amount of delay so if I add X amount of delay if I am able to add X amount of delay for nominal case the delay in the set of report will become 0.1X if the delay is 1.1 for later it will become 0.9X if the delay is for hold part if the delay is 0.9 so usually you will have to take some margin into consideration there are so many things like that which we can discuss but again this will come from here but you should first and foremost you should know that I am trying to support this kind of what if anything what are the commands what are the basic set of rules that you should be able to know and rest will come with experience so let me add one more buffer here it gives 0.1 to delay in hold so it will probably solve this one I want to add the buffer here at this point so I do insert buffer by itself so I insert buffer you can also add an inverter here so I you can give new net name, new cell name but if you do not give it a sign a default some default name so let me just I will buffer this pin particular pin I see that you know portless is an option here I give this pin and I will give what lip cell what buffer to use I will use it in buffer so it entered a buffer U1 at this it named a buffer U1 that is why it is a good idea to have kind of a prefix of suffix after in the name to make sure that you can identify this buffer easily this type of U2 and U2 which is from this library it fit this buffer and now let us do update timing and now I will do a report timing delaying I will do report timing to the whole violation is solved yes the whole violation is solved but this is where you have to be careful it is not giving any percent it is giving H means it is a hybrid timing calculation because we added a new buffer a new net was created there are no parasitic for this unit the parasitic can only come we focus on this listen carefully on this statement any such issue is not legalized yet what it means is that the real issue will be implemented when this change goes to the back end netlist in case of size error it was comparatively better because okay yes the dry strength has increased or decreased but the net there is no new net created although there might be some displacement when it goes to the back end too but in case of insert buffer the new net is created I will give minus net and we will see what is the new net this is the new net that is created there is no parasitic for this so for the input of this cell what prime time will do it will use the earlier net so for example this net here whatever that was driving this buffer earlier prime time will use it to drive now the new buffer it will do timing calculation here which it tells the hybrid timing calculation that means it is using whatever was the earlier net plus it is probably using a by load model or a zero delay model so that therefore it tells give spaces that it is H it is not one person it is not stress everything is not coming from stress some part is coming from stress some part is coming from by load model so this is not yet legalized it is only that slack is met yes but it has to go to back end so all such water analysis you do you can write out in an issue file from prime time in that issue file you can give it to the back end engineer and get the issue implemented legalized so this was the so we could see again the setup slack minus through this particular tell that we have added and yeah that is okay we can we have added this particular then we will do this so fine setup slack is also fine now that here since we added the cell at the end point directly at the end point timing end point there will not be any through paths I mean there is only one path unique path it will not affect any other path it will only affect this particular path so this was all about water analysis again I would request you to get hands on experience before attempting this this unit will make most when you have had some experience now I will do some give some examples of attributes now let us do a report attribute on some objects so as I told you the objects are cells like poles, spin and so on let us see which is a particular cell and reports an attribute let us say I report attribute on so report attribute has this thing so you can give class also class is not compulsory if it cannot register what is the class object it will ask you to give class minus application means what all attributes are defined via .lib or via application so you should always give minus application what all attributes are I do a get cells let us say I do what is on this this particular menu now it is listing all these attributes for this particular menu so it tells us that design is orca object is this particular cell obviously in this complete reported object itself the type of the attribute is float here the attribute name is area so this is the area of this cell and the value is this again the attribute is base name the value is P C I W C quran this is the base name base name means the name of the instance without the hierarchy right there will be something called it has disabled timing the type is boolean it can be the bit viewer called disabled timing is true I am not sure some some timing might be disabled here do not touch is true do not touch is true means now front time will synthesis can use these attributes early is fall cell check the rate factor early fall clock cell check these are the rates whatever we have given these are check the rates we have not given any check the rates so check the rate are all one cell the rate is 0.9 for early and late the rate will come later full name is black box true here because time time does not have functionality and so on so these are the complete list of attributes that is available for you to play this let us do some attributes on some net let us do report time first let us do report attribute minus application on some net let us say I give and now report timing report name application net I give let us say this particular minus no split will not split the line so these are so many attributes on this net capacitance is and so on capacitance is names has detail parasitic so the has detail parasitic for example if you want to write your own procedure to check whether the all the net has parasitic you can use such kind of attribute you can check whether you can make a collection of all the nets and for each net check whether each net has detail parasitic and has valid parasitic and so on this is now I will write a small snippet of code and I will show you how we can use this attribute use these attributes first I will use let us give an example of let us do a report timing for application data group pclk minus no split yeah now let us say I want to find out the area for this particular cell now I am just giving some examples they may be useful or they may be weird but at least they will show you the and how to use attribute let us say I want to know the area of this cell so I know that area has an attribute I say get attribute get attribute you give first what is the object name I say get cells this is the object and I know that the attribute name is area so this is the area of this cell I want to know what all pins are there let us say I want to know I think number of pins is let me do a so to know how what all attributes are there you can do report attribute this will give you a detail factor this will give you a detail thing so number of pins it is number of pins so if you do a get attribute on this number of pins then it will give you the number of pins here right so now let us give you an example of a slightly more elaborate code let us say again I will do a report timing now we did we saw that there is a delay cell here this is now a different part this is not a delay cell that means size of size these are different now let us say I want to know I see that if we add this delay cell this delay cell is given so much delay now let us say I want to find out a list of all the cells that are of this particular type that are of the type dl dl type and of any drive string they can be of any drive string and I want to find out where they are what is the complete list so let me write out the code what are the ideas first we have to get I will build the code I will make the way that you will probably think and start building the code first I need a list of cells of this particular type how do I do that I know that if I do get cell I do get attribute on this particular cell I will use this example I will use this particular cell and if I do a rest name I know that it will give me the rest name now I have to build a collection of all such cells which with this rest name so there are two commands you can use you can use a filter correction or you can use minus filter option in the get cell so I will use the minus filter option get cells minus hierarchical keys when you want to go through the complete hierarchy now I want all cells for which the rest name is let us say dl102d1 I say minus filter and here you can give rest name this is how you can use the minus filter option of get cells or get nets anything with the get you can use this particular filter attribute this filter it has a minus option you can check minus health first it has a filter option so rest name is equal to this filter this will give me a list of all the cells a collection in fact it will return a collection collection is an array it will return a collection with all the cells with the same rest name so this is the collection now if I want to know the number I can do a size of collection so 16 there are 16 delays of this particular nation but I have not still got the list where I have you get delays of all the drives I do not want just even I want all the drives other thing so if you try to do something like this something like this then it will give something underscore cell something this is just a pointer so this get cells is not printable this is not a string it is a collection if you want to echo it something like this you can do a query object so what I can do I can store this collection in let us say my collection I can do something like this so my collection is but if I later I want to see what is my collection and if I do echo then it will not tell me it will just give me some pointer you can use a query objects to query objects to print the value this will print the value now I have what I will do is I now do not want the single drive step so I can do something like this start enclose it within double course and use a similarity operator so if the ref name I know that drive step is the last with it so any delay cell delay 1 0 2 whatever restart it will give me so probably the list is same is it same is it both so I will do a size I will do a collection to see if there are now there are 17 so there is one more of another now here I want not even of different drive step I want all DL cells so usually DL cells are depicted by two things one is the what delay they provide so probably 0 2 is the measure of the delay and D star is the drive step so I can do D L star and let me see this okay 17 so these are the total delay steps so now let me store this in in I will again store this in one of the collection just to make it easier later so now I have a I have a list of some objects I have arranged a collection based on some filtering criteria and remember I use the attribute this is the attribute ref name is the attribute that is why I could use the filter option of get cells now I want to let us say print it and I also want to know now so see there are different kind of drive strength there and there can be different type of delay cells this collection represents different types of delay cells with different drives right that was a problem specification now I want to print the instance name and I want to sprint the reference name I want to see what type of delay cell is what is the drive step of the so I will use a for each in collection I have a correction already this is a for loop that runs on a collection I give any variable here anything let us say x y I have already made a collection called my call it will run through my call as you write a procedure and close it within early places now I have to say echo get attribute dollar x y is the iterative iteration variable and I want the full name attribute again I want to write to know what is the reference name of each of these cells so this is a procedure it will give me for it will run through this particular collection this is iteration this is the loop variable x y and I want the full name this is the full name this is the reference name this is the file type this is the j2 type now let us say somebody asks me that what is the area what is the area impact of adding all this yes boss you have added so many delay cells to solve time variation but what is the area increase so you can do something like this again we will run through each of these collection and I will calculate the area by using get attribute of what I will do first I will do nothing I will set let us say dl underscore area to be 0 now what I will do is I will do for each of the collection I will do xy I will do dollar my dollar then I will what I will do I will set the area to be set a variable that attribute dollar x y and area so this will store the area value in way and then I will set dl area and so the command to simple plus and minus will move directly you have to call a function called expr to do all kind of mathematical operations so in the dl area I will add the value of a so this will sum up all the area and I can echo the dl area and it will give me the complete area so this is the complete area for each of the combining all the there is the area and part of adding all the variables so this is the way you can do lot of things attributes and so this was about the object now one of the most interesting object is a timing path so timing path is a special kind of object so what you could do let's say you want something like you want to check the slack on of particular memories address fields now let's do a report timing minus this is the last example that I discussed obviously these examples are not exhausted they are just to show you that what can be accomplished in time time using attributes and using tickle command so that you know this is after the starting point for you this is a good starting point for you to start exploring the applications of attributes in time so let's do a delay min and let's do a group on PCM so we saw memory this is a memory so I want to know what is the slack on so this is the address field of the memory I want to know first let me see what all are the address fields of this how many are the address fields of this memory so usually in this case I know that address fields will start with a so I do a start so there are so many address fields now let's say somebody asks you get me the slack value the whole slack value of all the memory pins so I will do a size of collection to see how many pins are there now I want to report the slack of all the memory pins how do you do that and I am not sure guy will write out the report I mean report for all the memory pins and he will rep either use the rep command or do it normally note down the slack of each memory pin separately and then show it to the guy who is asking for it that is the engine of what you can do you can move through the property there is a very interesting attribute for it get timing path the report timing reports the text value get timing path will give you a collection of object of timing path so what I will do almost all the attributes almost all the options and report timing are supported in get timing path so what I will do is I will do something like so if you want to report time so the first thing if I want to report timing on these memory pins I will do report timing minus minus to all these pins I will let us say I will do path type summary I will do minus so it will give me it will give me only two it is giving me only two end points because they might be on different a1 and a2 are on different document now I know I have to increase the max path because they are about 20 pins so I will do it 20 so it will give me so it is giving me the whole timing for okay there are 10 invalid end points for constraint path it means that take off the path are not constrained they are unconstrained out of 20 10 are constrained now let us say I want to do this path on each of these I will use I will set a time collection I will set a collection if I have any and I will use the same options get my new path and I will give the same options only thing that will change is the path type because path type has path type and no spit are more for reporting so this is not a reporting this is making in the collection so I will do something with it and now I get a new collection which has which contains now if I do quality objects on this it would be interesting so it says it cannot be quality because it is a collection of timing path so report timing should be 10 paths and it says that 10 are unconstrained it is okay these 10 are contained in this this whole information about this that I are contained in this so what I could do is that let us do particular interest so let me show you how it happens on a single path so if I do not do a max path here it will report a single path and it will not report anything it will just say that it is form of collection now I can do a get attribute on so now it is reporting the slack values just like this minus 0.22 this is this is a this is a significant digit 2 this is a significant digit 6 this is the collection that I form now what I can do I can do for each in collection anything and $ $ this particular collection has 20 paths or 10 paths and then I will get attribute $ XY the attribute so timing path has lot of attributes one of them is slack then I get attribute let us say I think it is end point I am testing and $ the endpoint is not defined but see here it gives me the slack value so I just so this is the so for all such 10 timing paths it is reporting the slack value so this is how you play with the timing collection the timing path similar to the objects like next the timing path is a much more powerful object so what I can do I can say the code attributes minus attribution or let us say get timing path I can do anything I can say get timing path minus group let us say PCLK minus delay this will give you the worst path in PCLK as a code attribute these are all the attributes that are defined on this particular timing path you can actually build your own report time in command if you want if tells us what is the arrival capture clock path is a collection so this type can be collection now endpoint endpoint clock string and so on there are so many so many endpoint clock is inverted it gives you so many options it gives so many attributes so you can use this so require time see it has required time it has slack it has arrival time you can check what is the arrival time here you can report what is the arrival time here for example you can report arrival time here arrival time has not been defined for this timing path okay so arrival okay it is only arrival okay so this is visual arrival so you can do so many in time number of things which with get timing path on timing path so otherwise all the other all the other object classes cell net port pin will help you get the values such as area the cell type the capacitor types and all that get timing path on the other hand will give you complete data with respect to any timing path so get timing path is in fact the command that is mostly used that do automatic kind of fixing that suggest that do automatic timing these things because they work on the report they work on the timing paths and instead of writing out the report timing into a report pipe and doing text doing some text based operation on those it is more difficult when compared to get timing path doing getting extracting data from the get timing path using attribute so this was all about time time this is the end of unit pipe and I hope you enjoyed it hope you learned a lot of stuff a lot of new stuff so again this particular session please get your hand yourself a lot of practice on time time before attempting the attributes and what is analysis attributes are very very interesting you can do a lot of things with it you can make very nifty scripts to do stuff quickly in your job in your projects so all the best with that thank you