 Hello and welcome to this presentation of the STM32U5 power controller. The STM32U5's power management functions in all low power modes are also covered in this presentation. STM32U5 devices have several independent power supplies, which can be set at different voltages or tied together. The main power supply is VDD supplying almost all input outputs except for those related to the VBAT domain and port G-pads 15 down to 2. VDD also supplies the flash memory, the reset block, temperature sensor and all internal clock sources. In addition, it supplies the standby circuitry, which includes the wake-up logic and independent watchdog. The STM32U5 series microcontrollers only rely on integrated regulators. V-Core supplies most of the digital peripherals, SRAMs and flash memory controller. VDD A voltage supplies the analog peripherals. The Vref plus pin provides the reference voltage to the analog to digital and to digital to analog converters. It is also the output of the internal voltage reference buffer when enabled. Additionally, the USB transceiver, the DSI transceiver and port G-pins 15 down to 2 have their own independent power domains powered respectively by VDD USB, VDD DSI and VDD I02. A backup battery can be connected to VBAT pin to supply the backup domain. The built-in switched mode power supply, SMPS, step-down converter is a power efficient DC-DC non-linear switching regulator that improves low power performance. The SMPS generates the V-Core voltage on VDD 11, 2 or 3 pins. Only STM32U5XXXXQ support SMPS. STM32U5 devices feature a flexible power control which increases flexibility in power mode management and further reduces the overall application consumption. This slide details the consumption in some of the power modes for the STM32U545 and the related wake-up sources. The devices support dynamic voltage scaling to optimize their power consumption in run mode. The voltage from the main regulator that supplies the logic, V-Core, can be adjusted according to the system's maximum operating frequency. The consumption is even lower when frequency and voltage are decreased. STM32U5 devices support 7 main low power modes. Sleep, stop 0, stop 1, stop 2, stop 3, standby and shutdown modes. Each mode can be configured in many ways, providing several additional sub-modes. In addition, STM32U5 devices support a battery backup domain called V-BAT. The high flexibility in power management provides both high performance with a core mark score equal to 4.07 MHz, together with an outstanding power efficiency. A brown-out reset BOR is implemented to ensure safe device operation even during power-on and power-down. This unit resets all registers except those in the backup domain powered by V-BAT, which contain the RTC and temp blocks and the external low-speed oscillator LSE. When exiting standby mode, all registers powered by the main regulator are reset. When exiting shutdown mode, a power reset is generated. 5 BOR levels can be selected through option bytes. During power-on, the BOR keeps the device under reset until the supply voltage VDD reaches the specified V-BOR threshold. The brown-out reset circuit is always on except in shutdown mode. During standby modes, it is possible to set the BOR in ultra-low power mode to further reduce the current consumption by setting the ULP-MEN bit. V-BAT is the power supply for RTC, temp, external clock 32 kHz oscillator and backup registers through power switch when VDD is not present. Functionality is guaranteed down to the V-BOR V-BAT minimum value, which is 1.58 volts. A power voltage detector, or PVD, can generate an interrupt when VDD crosses the selected threshold. The PVD can be enabled in all modes except stop 3, standby and shutdown modes. The threshold is selected by software among 7 possible values. In addition, comparisons can be done between VREF-INT and PVD-IN external pin. The STM32U5 also supports two new features to enhance the power supply supervision. Temperature threshold monitor, upper VDD threshold monitor. Whenever these monitors detect an abnormal condition, they can generate an internal temper event. To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have an independent power supply that can be separately filtered and shielded from noise on the PCB. The VDD-A, VDD-USB and VDD-IO power supplies can be independent from VDD and can be monitored with dedicated peripheral voltage monitoring, or PVM. The VDD-A supply can be monitored by the analog voltage monitors, AVM, and compared with two thresholds. 1.6 volts for AVM-1 or 1.8 volts for AVM-2. The IO2 and USB have their own voltage monitors, respectively IO2-VM and UVM. Each PVM output is connected to an EXTI line and can generate an interrupt if enabled through the EXTI registers. After reset, these independent power domains are logically and electrically isolated and therefore are not available. The isolation must be removed before using the analog peripherals by setting a control bit when the related power supplies present. The devices embed two regulators, one LDO and one SMPS in parallel, to provide the V-core supply for digital peripherals, SRAMs, except backup SRAM and embedded flash memory. Both regulators can provide four different voltages in order to implement dynamic voltage scaling and can operate in stop modes. It is possible to switch from SMPS to LDO and from LDO to SMPS on the fly. The SMPS allows the power consumption to be reduced, but some applications can be perturbed by the noise generated by the SMPS, requiring the application to switch to LDO. The slow startup feature is selected to limit the inrush current after power on reset. This increases the wake-up time when exiting stop or standby modes. However, it is possible to configure a faster startup on the fly applicable for the next startup either after a system reset or wake-up from low power mode except for shutdown and VBAT modes. The fast startup is selected by setting the FSTN bit. Using an external regulator to generate the V-core power supply externally is not supported. This figure represents all power states and the transitions between them. The following regulators are implemented. LDO, SMPS and low power regulator, LP-REG. The LDO and the SMPS regulators have two modes, main regulator mode used when performance is needed and low power regulator mode. LDO or SMPS can be used in all voltage scaling ranges and in all stop modes. After reset, the regulator is the LDO in range 4. Switching to SMPS provides low power consumption, in particular at high VDD voltage. It is possible to switch from LDO to SMPS or from SMPS to LDO in any range by configuring the reg cell bit. When exiting the stop and standby modes, the regulator is the same as when entering low power modes. The voltage range is the range 4. Exit from shutdown is always done on LDO. Here are some tips to reduce the power consumption in run and sleep modes. By default, the instruction cache is a two-way set associative cache. For applications needing a very low power consumption profile, it can be reconfigured as direct map cache. In this case, no replacement algorithm is required. After reset, both flash banks are in normal mode. In order to reduce power consumption, each bank can independently be put into power down mode. The whole flash can be put in power down when the device enters sleep mode. Up to 6 SRAMs are embedded in the STM32U5 devices, each with specific features. SRAM 1, SRAM 2, SRAM 3, SRAM 5 and SRAM 6 are the main SRAMs. Availability depends on STM32U5 product. Refer to the datasheet of your product. SRAM 4 is in the SRAM used for low power background autonomous mode. LPBAM peripherals in stop-to mode. These SRAMs are made up of several blocks that can be powered down in stop mode to reduce consumption. Internal AHB and APB bus clocks can be gated off when the peripherals connected to these buses are all unused. Memories and some modules such as caches and independent watchdog remain clocked when the bus clock is stopped. Some peripherals support autonomous mode. These peripherals can generate a kernel clock request and an AHB APB bus clock request when needed in order to operate and update their status register even in stop mode. As a general recommendation, the voltage range should be adapted to the target performance level and any unused peripherals should be switched off. SMPS and LDO regulators provide, in a concurrent way, the V-Core supply depending on application requirements. However, only one of them is active at the same time. When SMPS is active, it feeds the V-Core on the VDD11 pins supplied by the filtered SMPS via Lex SMPS output pin. A 2.2 microhenrys and a 2.2 microfarad capacitor on two VDD11 pins are then required. When available, the third VDD11 pin must be connected to other VDD11 pins without any capacitor. On legacy packages, only one V-CAP pin is available and must be connected to a single 4.7 microfarad capacitor. In these legacy packages, only the LDO regulator is available and the SMPS regulator cannot be used. When LDO is active in SMPS packages, it supplies the V-Core and regulates it using the same decoupling capacitors on the VDD11 pins. The LDO and the SMPS regulators have two modes, main regulator mode used when performance is needed and low-power regulator mode. LDO or SMPS can be used in any voltage scaling ranges and in all stop modes. The smart-run domain SRD architecture relies on a DMA allowing autonomous operation during low-power modes down to stop too. This power domain features a 32-bit AHB bus matrix that interconnects two masters, the main AHB bus matrix and the LPDMA1 and two slaves, AHB3 peripherals including AHB to APB bridge connected to APB3 and internal SRAM4. After entering standby mode, SRAMs and register contents are lost except for registers and backup SRAM in the backup domain and standby circuitry. Optionally, the full SRAM2 or 8 kilobytes or 56 kilobytes can be retained in standby and stop three modes supplied by the low-power regulator, standby with RAM2 retention mode. The regulators are off in standby mode without SRAM retention and in shutdown mode. To retain the content of the backup registers and supply the RTC function when VDD is turned off, the VBAT pin can be connected to an optional backup voltage supplied by a battery or by another source. The VBAT pin powers the RTC unit, the LSE oscillator, the PC13 to PC15 and tamper input outputs allowing the RTC to operate even when the main power supply is turned off. The switch to the VBAT supply is controlled by the power down reset embedded in the reset block. VBAT also powers the backup SRAM when the main power supply is turned off. The devices support a low-power background autonomous mode, LPBAM, that allows peripherals to be functional and autonomous in stop zero, stop one and stop two modes. Autonomous means that no software runs to control these peripherals. The autonomous peripherals mapped on AHB1, AHB2, APB1 and APB2 belong to the CPU domain and are autonomous in stop zero and stop one thanks to GPDMA1 and SRAM1, SRAM2, SRAM3, SRAM4, SRAM5 or SRAM6. The autonomous peripherals mapped on AHB3 or APB3 belong to the smart run domain and are autonomous in stop zero, stop one and stop two thanks to the LPDMA1 and SRAM4. While in stop two mode, the CPU domain is not active. However, background tasks can be in progress in the smart run domain including data movement thanks to the low-power GMA. Stop mode achieves the lowest power consumption whilst retaining the content of the SRAM and registers. All clocks in the core domain are stopped. In stop zero mode, the regulator remains in main regulator mode allowing a very fast wake-up time but with much higher consumption. Stop three is the lowest power mode with full retention but the functional peripherals and sources of wake-up are reduced to the same as those in standby mode. Subblocks of full SRAM1, SRAM2, SRAM3, SRAM4, SRAM5 and SRAM6 can be totally or partially powered off to save power consumption. The contents of SRAMs embedded in caches and peripheral units can also be powered off through control bits. The system clock when exiting from stop mode can be either MSIS up to 24 MHz or HSI16 depending on software configuration. The voltage regulator is configured in main regulator mode. All clocks in the v-core domain are stopped. The PLL, MSIS, MSIK, HSI16 and HSC oscillators are disabled. The RTC clocked by the internal or external low-speed oscillator can remain active. The brownout reset is always enabled. Most of the peripheral clocks are gated off. The events from all input outputs can wake up from stop zero mode as well as the interrupt generated by the active peripherals. The system clock when exiting from stop zero can be either MSIS up to 24 MHz or HSI16 depending on the software configuration. Stop one mode is very similar to stop zero except that the power figures are much lower as the main regulator is stopped and replaced by the low power regulator. In stop two mode, most of the v-core domain is put into a lower leakage mode. All clocks in the core domain are stopped. The PLL, MSIS, MSIK, HSI16 and HSC oscillators are disabled. Some peripherals with LP-BAM capability can switch on HSI16, MSIS or MSIK for transferring data. All SRAMs and register contents are preserved but the SRAMs can be totally or partially switched off to further reduce consumption. The BOR is always available in stop two mode. The BOR is always available in stop three mode. In the stop three mode, the input outputs are in floating state by default. The input outputs can be configured with either a pull up or a pull down or can be kept in analog state. Some input outputs are used for JTAG, serial wire debug and can only be configured to their respective reset pull up or pull down state during stop three mode or configured to floating state. The RTC outputs on PC13 and PB2 are functional in stop three mode. PC14 and PC15 used for LSE are also functional. The 24 wake up pins, multiplexed on 8 events, wake up 1 to 8 and the 8 RTC tempers pins are available. When exiting the stop three mode, the microcontroller is in run mode, range 4. The low power background autonomous mode, LPBAM, is an important new feature of the STM32U5. While the Cortex M33 is asleep, some parts of the microcontroller remain active and can perform background tasks that do not require software assistance. The two DMA controllers, LPDMA and GPDMA, not only transfer data but can also be initialized to access control registers in order to implement complex sequences involving peripherals and memory. For example, a timer can trigger a periodic task that consists of acquiring samples from ADC, moving these samples to memory and monitoring the sampled signal to detect any abnormal condition. Some peripherals with autonomous mode and wake up from stop capability can request HSI16, MSIS or MSIK to be enabled. In this case, the oscillator is woken up by the peripheral and is automatically switched off when no peripheral needs it. The table indicates which peripherals are functional and autonomous in stop zero and stop one modes, and highlights those that remain functional in stop two mode. In stop mode, asynchronous triggers can be used to automatically start a communication transfer, a conversion sequence or a DMA transfer. These hardware triggers can be the low power timer timeout, a comparator output of the detection of an edge on an IO pad. This slide and the following ones provide some implementation examples of autonomous peripherals and LPBAM. These are background tasks involving modules that remain active, while the Cortex M33 processor is in stop zero, one or two low power states. In this first example, a communication module, such as Y square C, receives data that are written to a memory buffer through a DMA channel. Several peripherals support the autonomous mode, which allows to be functional and perform DMA transfers in stop zero, stop one and stop two modes without any CPU wake up. In addition, the low power background autonomous mode LPBAM is supported in stop two mode, allowing to build complex use cases with autonomous peripherals in the smart run domain thanks to LPGMA transfers. Only Y square C number three supports this capability in stop two mode. When the DMA channel completes the transfer, it wakes up the Cortex M33. The same approach can be used with SPI and new art reception. In this second example of autonomous peripherals and LPBAM, a low power timer periodically triggers a transmission of data from a communication module such as SPI. The data are transferred from a memory transmission buffer to the SPI FIFO by a DMA channel. When the DMA channel completes the transfer, it wakes up the Cortex M33. Asynchronous triggers can be other sources, such as an edge detection on a general purpose input or a voltage comparator output assertion. Only SPI number three supports this capability in stop two mode. In this scenario, the low power timer periodically triggers a sample acquisition. A DMA channel automatically transfers these samples to a memory buffer. A wake up of the Cortex M33 is requested on the condition that the ADC analog watchdog detects the conversion result exceeding program thresholds. Temperature sensor, V-BAT, V-CORE, internal reference voltage or external channels can be monitored sequentially. Up to three channels can be monitored in stop mode, thanks to three analog watchdogs. As long as the monitored voltages remain within the program thresholds, no wake up is requested, which enables periodic voltage monitoring while the microcontroller is in stop zero, one or two modes. Only ADC number four supports this capability in stop two modes. A DMA channel is triggered periodically by a low power timer. It transfers samples from memory to the digital to analog converter. This background task does not require the processor's intervention as long as the waveform to be generated does not change. Note that an ADC analog watchdog can be used to monitor the conversion result and wake up the Cortex M33 whenever the analog voltage is out of program thresholds. This is achieved through the interconnect matrix that internally loops back the output of the DAC to an analog input channel of the ADC. In this example, the audio digital filter connected to external Sigma Delta modulators processes voice samples and transfers the filtered stream to a memory buffer through a DMA channel. The audio digital filter can be programmed to wake up the Cortex M33 when voice activity is detected. An ultra low power comparator comp1 or comp2 triggers a DMA transfer from a memory buffer to an LPTIM register in order to change the duty cycle of a PWM output. This background task does not require software intervention so the Cortex M33 remains in stop two mode. The low power timer periodically requests a DMA transfer from a memory buffer to the low power general purpose input output module. For instance, a LED can blink while the Cortex M33 remains in stop two state. This last scenario demonstrates the collaboration of multiple units without involving the Cortex M33. The low power timer periodically triggers an acquisition sequence in the ADC that relies on a DMA channel to transfer the samples to a memory buffer. When a particular threshold is exceeded, an analog watchdog triggers another DMA channel that automatically transfers the latest samples to an SPI controller. For example, these samples can be stored in a non-volatile memory connected to the SPI controller. Another analog watchdog is programmed with a second threshold that, once exceeded, causes a wake up of the Cortex M33. This table summarizes the differences between the four stop modes. The main regulator is active in stop zero mode while the low power regulator is active in stop one, two and three. Functional peripherals in stop zero and one modes belong to the CPU and smart run domains. Only peripherals in the smart run domain remain active in stop two mode. Active peripherals in stop three are the same as in standby mode. All input outputs are active and can be used for wake up in stop zero, one and two modes. However, only 16 input outputs are accessible by LPDMA1 in stop two mode. In stop three, 24 pins can be used for wake up. The microcontroller consumption is drastically reduced when entering stop two and stop three modes, although the wake up time is hardly more than in stop one mode. In standby mode, both main and low power regulators are powered down. The PLL, HSI16, MSIS, MSIK and HSE oscillators are switched off. The RTC, clocked by the internal or external low speed oscillator, may remain active. The brownout reset is always enabled. The independent watchdog can also be enabled in standby mode. Reset, brownout reset, RTC and tamper detection, independent watchdog and any event on the wake up pins can exit the microcontroller from standby mode. Input outputs can be configured with internal pull up, pull down or floating in standby mode. The 24 wake up pins multiplexed on 8 events and the 8 RTC tamper pins are available. This slide describes the state of the microcontroller when standby mode without SRAM2 retention is active. SRAM2 content can be partially or fully preserved. In this case, the low power regulator is on and provides the supply to SRAM2 only. To reduce consumption, the brownout reset can be configured to operate in discontinuous ultra low power mode in standby modes. In shutdown mode, the main regulator and the low power regulator are powered down. The SRAMs and register contents are lost except for registers in the backup domain. The RTC can remain active. The brownout reset is deactivated. Only the external low speed clock can be enabled. The wake up events are the RTC and tamper events, the reset and the 24 wake up pins. Input outputs can be configured with internal pull up, pull down or floating in shutdown mode, but the configuration is lost when exiting the shutdown mode. The clock sources used to exit standby state is the MSI from 1 to 4 MHz. In standby state, two parts of the SRAM2 can be independently retained, one 8 kb part and one 56 kb part. The 2 kb backup SRAM can be preserved in standby mode, but not in shutdown mode. The table indicates which pins remain active when exiting standby or shutdown modes. 24 wake up pins and the 8 RTC tamper pins are multiplexed on 8 events. Wake up 1 to 8. The WUSCL bit fields select which pins and events can cause a wake up. WUSCL must be configured to binary 11 to wake up with RTC or external tamper detection. VBAT is the power supply for RTC, 32 kHz external clock oscillator, backup registers and optionally backup SRAM when VDD is not present. Typically, consumption in VBAT mode without RTC is 120 nA at 1.8V and 450 nA with RTC. In case VDD drops below a certain threshold, the backup domain power supply automatically switches to VBAT. When VDD is back to normal, the backup domain power supply automatically switches back to VDD. The VBAT voltage is internally connected to an ADC input channel in order to monitor the backup battery level. The battery charging feature enables the charging of a supercapacitor connected to VBAT pin through an internal resistor when VDD supply is present. The charging is enabled by software and is done either through a 5 kΩ or a 1.5 kΩ resistor depending on software. Battery charging is automatically disabled in VBAT mode. The VBAT power domain has a dedicated brownout reset circuit. Note that the RTC remains active using either the internal or external low speed oscillator. Temperature and backup domain voltage monitoring can lead to a tamper as well as LSE clock missing detection or over-frequency detection. These tamper events can be programmed to cause the erasure of the backup SRAM and backup registers. In order to help with debug, three signals are available as device pin alternate functions. C-sleep, CD-stop and SRD-stop. The corresponding 3-bit combination indicates the current microcontroller power mode. C-sleep, CD-stop and SRD-stop are generated in the core domain, consequently they are not driven in standby and shutdown modes. They can also be used by an external board level power management logic. The PWR is a trust zone aware module. Both the secure attribute and the privileged level of some PWR registers are programmable, enabling four partitions. Secure privileged, secure non-privileged, non-secure privileged and non-secure non-privileged. The PWR trust zone security secures the following features through the security configuration register. Low power mode, wake up, WKUP pins, voltage detection and monitoring, VBAT mode and input output pull-up pull-down configuration. The security of some features is based on an inheritance mechanism. When the system clock selection is secure in RCC, the voltage scaling, VOS, configuration and the regulator booster are secure. When a GPIO is configured as secure, its corresponding bit for pull-up pull-down configuration in standby mode is secure. When the UCPD1 is secure in the GTZC, the PWR UCPDR register is secure. In addition to this training, you can refer to the following presentations. Reset in clock control, real-time clock, tamper, STM32 cube MX, focusing on the description of the power consumption calculator.