 Hello and welcome to this presentation of the STM32L5 Extended Interrupts and Events Controller. We will be presenting the features of the XTI Controller. The Extended Interrupt and Event Controller, or EXTI, provides up to 42 independent events split into two categories, configurable events and direct events. Applications benefit from smarter use of low power modes, taking advantage of the STM32L5's capability to wake up via external communication or requests. This is a block diagram of the Extended Interrupt and Event Controller. Configurable peripheral events are generated by peripherals without interrupt capability, but which are able to issue a pulse. The EXTI Controller provides interrupt detection, masking and software trigger. Direct peripheral events are generated by peripherals supporting interrupt requests. In this case, the EXTI Controller is used to generate events to the CPU and to request system wakeups. Do not confuse peripheral events and the processor event. Peripheral events are used by peripherals to indicate that they require processor attention. The processor event is a pulse signal used by ARM CPUs to exit the wait for event low power state. The EXTI is trust zone aware. The access to control and configuration bits of secure input events can be made secure and or privileged. When a non-secure master attempts to access a secure resource, the EXTI Illegal Access is reported to the Global Trust Zone Controller or GTZC. The Extended Interrupt and Event Controller can generate interrupts and events as well as wake up the processor from stop modes. Configurable events are linked with external interrupts from GPIOs, PVD, Comparators and PWM modules. Direct events are linked with RTC secure and non-secure, TAMP secure and non-secure, I2C, USTART, LPUR1, LPTIM, USB and UCPD. The Cortex M33 supports two ways to enter a low power state. First way, executing the wait for event or WFE instruction. Second way, executing the wait for interrupt or WFI instruction. With WFE, the first instruction executed after a wake up event is the next sequential one, i.e. INSTN plus 1 in the sequence on the left. By implementing WFI, the processor jumps to the interrupt service routine when an enabled interrupt request is received. Note that an interrupt request is a WFE exit condition, but an event received on RxEV is not a WFI exit condition. Receiving an enabled interrupt request while the processor is in the WFE state causes the processor to wake up and execute the interrupt service routine. When the Cortex M33 control bit called SEV on PEND, which means send event on pending, is set to 1, receiving an interrupt request related to a must interrupt causes a wake up event. In this case, the processor executes the next sequential instruction. Software may later decide to enable the next interrupt to be served. This figure explains the various stages enabling the conversion of a configurable peripheral event active edge into an interrupt request. The first stage is the asynchronous edge detection circuit configured by two registers, EXTI-RTSR and EXTI-FTSR. Any edge possibly both can be chosen. The software can emulate a configurable event by setting the corresponding bit in the EXTI-SWIR register. The bit is autocleared by hardware. An end gate is used to mask or enable the generation of the interrupt to the NVIC. Finally, a flag is set in the EXTI-PR register when the interrupt is generated to the NVIC. This flag enables the software to determine the cause of the interrupt. This flag is expected to be cleared by the interrupt service routine. This figure explains the various stages enabling the conversion of a peripheral event active edge into a processor event. Both configurable and direct peripheral events can be configured to issue events to the CPU steered to its IX EV input. Configurable event active edge is programmable in the EXTI-RTSR and EXTI-FTSR registers while direct events are always sensitive to a rising edge. Software can emulate a configurable event by writing to the EXTI-SWIR register. Unlike interrupt requests, the CPU has a unique event input so all event requests are all together before entering the event pulse generator. The registers used to mask the generation of events are different from the ones used to mask the generation of interrupts. EXTI-EMR instead of EXTI-IMR. Note that unlike interrupt requests, the pending bit corresponding to the peripheral event line is not set. The CPU wake-up signals generated by the EXTI block are connected to the PWR block and are used to wake up the system and CPU subsystem bus clocks. Both configurable and direct peripheral events are able to request a wake-up. A wake-up occurs when an asynchronous edge detection circuit has detected an active edge or flag is set to 1 in the EXTI-RPR register. Consequently, software is expected to clear the flag in the EXTI-RPR register to disable the wake-up request when the source of the wake-up is a configurable event. For direct events, the flag is located in the peripheral unit. These flags enable the software to find the cause of the wake-up. The wake-up indication is asserted when either the interrupt or the event generation is enabled, see the ORGATE combining EXTI-IMR and EXTI-EMR registers. A direct event is able to generate a CPU event and trigger a system wake-up through the EXTI controller. The active edge of direct events is the rising edge. Direct events do not rely on the EXTI controller to assert interrupt requests because they have their dedicated lines to the NVIC. Otherwise, the same circuit as the one described in the previous slides is implemented. Direct events can be independently masked for event generation and interrupt generation. The interrupt mask is only used as a wake-up mask. The ESTM32L5 has 8 IO ports. Ports A to G are 16 pin-wide, Port H is 3 pin-wide. Each of the 16 EXTI configurable events related to GPIO ports has an independent multiplexer. The EXTI multiplexer outputs are available as output signals from the EXTI block to trigger other IPs. The EXTI multiplexer outputs are available independently from any mask defined in the EXTI-IMR and the EXTI-EMR registers. Two levels of protection are programmable per even source, security and privileged. At EXTI level, the protection consists in preventing unauthorized write access to change the settings of the secure and or privileged configurable events, change the masking of the secure and or privileged input events, clear pending status of the secure and or privileged input events. Security violations are reported to the Global Trust Zone Controller or GTCC. The security and privilege configuration can be globally locked after reset by setting the lock bit in the EXTI lock R register. This table provides all inputs of the EXTI block present in the ESTM32L5 microcontroller and indicates for each of them whether it's a configurable event input or a direct event input. For more details about the system configuration module, refer to the reference manual for STM32L5 microcontrollers. If needed, refer also to these trainings for more information. Arm Cortex M33 Core, Power Control or PWR, System Configuration or CIS CFG, Interconnect Matrix or IMX, Global Trust Zone Controller or GTCC.