 veland చురీిలి చుర్పి చాచులువ౦్మ్క్ onta�ురోవకానోదిమీ ఆదేషద౿ చఎిమ్పివ౦ Давай ఇడిస౐఑చ్రే మలిల�을� G is all about how memory is managed ok. We saw memory hierarchy and cache memory organization in detail so far. Now we are going to see two important functionalities related to memory one is memory protection other one is a virtual memory ok. So, let us worry about virtual memory and MMU later. Today's focus will be on memory protection units ok, let us talk about it. So, in this discussion we will be covering about little bit I will give you a overview of process and context which though I have touched upon this in subsequent earlier classes it is appropriate to just talk about it little bit before we get into processes and memory protection. So, then we will talk about what are protected systems and why do we need a system which has got protection built into it and then we will go into the detail of MPU ok and then we will see how MPU can be considered. Now, just to give you a overview ok let me choose a nice color see we saw ARM processor then I we touched upon co-processors ok and then we saw memory hierarchy and then some memory controller will remain in memory which which I am assuming to be outside of the SOC and memory controller connecting into that and then we have address bus going there and the data bus is coming to the co-processor here what we have to do is vote here ok an example. So, and then yesterday or you know the previous classes we talked about patch which came in between the memory controller and memory. Now, we have two topics to discuss one is memory protection unit and memory management unit. Now, this is not the focus now this is the focus memory protection unit. So, one thing what you should remember is memory protection unit functionalities are built into the MMU is MMU present in the system ok. So, there only a system with both MPU and MMU as a separate entities this functionality will be absorbed by MMU and MMU is actually having a MPU functionality also built into. So, if I say that system has an MMU that means you can implicitly MPU functionalities are there I have not told what is the functionalities of MPU, but this is this difference you should remember. Now, because in our discussion today we are going to talk about memory protection unit say MPU is not MMU is not there ok. Let me remove right now moment cache also to just know MPU is there ok only MPU that means there is no MMU in that case what happens is the address that goes into the MPU is also going into the memory ok. This is address this ok because there is no logical memory or physical memory whichever memory those concepts are not there when we are talking about MPU as a independent unit in the system ok. Again an option of having an MPU or MMU is a designerís choice ok. So, if the system what you build ok does not need virtual memory support, but it needs the memory protection unit support only then the choice will be to take only this module and do not bring in the virtual memory at all. In the case what happens the memory addresses what the processor gives out is directly going to the memory ok and accessing that. So, the physical memory is what processor needs ok processor or any processors running in the in the processor does not have any other virtual memory system in the in its execution. So, whatever is the memory it sees is the MM the memory management the main memory area. So, if suppose if it has got only you know 256 MB of main memory then the programs space also will be only limited to this. So, you have we may have to write everything only considering that there are there is only a 256 MB of space in the system and all the programs should call within that you know whatever we are deciding about code or data or stack what where it should go it should all be restricted to only the physical memory available in the system. There is no MMU to transfer it to another unit. So, that the virtual memory space may be bigger and the actual physical memory what you have in it will be smaller. So, that option is not there. So, do not keep in mind that when you are talking about only NPU in isolation we do not have a MMU present in the system and there is no virtual memory concept here ok. So, we can build a system like the concept. Now, we may wonder who is providing this NPU and MMU. Whatever I am discussing now it is all provided by ARM. See ARM does not only give you IP of the processor code ok. It also gives as we saw that cache controller and a cache we can code which we can build and configure using the controller and it also provides co-processor and VSP and it also has a bus standard which I will be talking about in subsequent characters. So, it also provides you the necessary you know IP along with all the you know text per testing purpose also it gives you so many support in the while providing IPs also. So, bus is there may it provides all the ingredients main ingredients for building your SPOT. So, NPU is also one of the co-processor ok. Now, when I say NPU it is a co-processor ok. You may immediately remember me saying that the co-processor will not have access to the address bus right I mentioned it earlier. Let me clarify what I meant by that ok may be this color is better. See in case of functionality when we want to build in a new functionality we want to add we have talked about vector floating pruning processor which is the co-processor. It needed some access to memory also because it has to keep its data here and then it will be doing a floating point arrangement. During that time I said that ARM only manages the memory space and it will only generate that and MMU also they are all co-processors ok. But the number is 15 it is specific to co-processor 15 whereas, here I said that it is 10 and 11 if I remember correctly. So, this co-co-processor 15 is reserved for MPU, MMU and cache controller also. So, what but I am also saying that MPU is connected to the address bus, but in the VHP page it was not connected to address bus, but only to the data bus whereas, in case of MPU or MMU they need to be connected to the address bus because they are something to do with the transfer of translation of the address that is MMU is done ok I will talk about that later. But the MPU's job is to protect the memory accesses ok different area of memory it wants to protect it. So, that is the functionality of MPU which I will go into detail now. So, if it has to perform a job of protecting the memory accesses it should know what the ARM processor is accessing ok. So, as I mentioned earlier the address generation is with the ARM processor, nobody is going to control that because our instructions which are getting executed in the ARM processor only controls how the addresses are generated by the processor. But the generated addresses can be seen by the MPU or for that matter MMU and then they can read it and do some translation and then then the security can be circulated that MMU means it will translate it address will be connected to main memory in this case the same address bus goes to MM main memory, but MPU also looks at the addresses ok. So, and if it requires that it needs to be connected to the data bus of course, yes because the MPU's controller are configured through the co-processor instructions ok. So, it may have to transfer some you know data that co-processor instructions should be you know transferring the contents from the register here to the some controller here and from here to here. So, this MPU and MMU are connected to both address and data bus and they may view the you know they may read the contents based on what is happening which instruction is getting executed by the co-processor. So, the ARM processor is executing a co-processor instruction which is saying it is 15 then MMU or MPU which is there in the system will become active and then try to understand what is what is that they ask by ARM ok. So, this is how the whole thing works in the case of MMU let us come back ok. So, let me change the colour. So, I think that is overviewer may you understand that it is not compressing that co-processor cannot look at the data bus, but if it is needed it can do it can be connected to both address and data bus ok. And driving the data bus is controlled if we if the co-processor has to drive the data bus means that means it has to write into something into the memory or back into the register something has to be transferred then that will be controlled by ARM. So, ARM will control what the co-processor will do ok. It is, but it can be seen sitting on both address and data bus to based on the functionality of the co-processor ok. In the case of BFP there was no meaning for it to know the address what is happening because it was interested only in knowing the instruction. So, it was looking at it ok, but there is no restriction that it needs to cannot be connected or something ok. That is that that you have it in your mind. So, that is known you when you look at the functionality of different co-processor you will know that ok. Let us see what are the processes ok. These processors are something which is running in the processor ok. Different context is maintained by the processor. So, if there is a single processor in the system ok. I am not talking about multi processor system. It is only a single processor then there can be only one process in the processor ok. Only one process can be activated. Just remember the word active. Only one process can be running at a time. But it can support multiple processors. So, if it has to support the processor has to support multiple processors running then there should be some some software functionality added to the system ok. It could be a OS or maybe we can have some other control system minimum scheduling system and minimum process generate creation and process shifting all that if it is there then it can be done. Let us assume for simplicity say a small kernel micro kernel may be is in the system in the system which is getting the control source and then it brings a set of processors in the system ok. So, this is the main memory. May be all the processors will be in the memory, but only one will be executed. That means for this process related code data and stack will become active. So, this part of the memory will become active and then the processor will execute the process P1 now. After that maybe I will tell you different reasons where this will go back ok and then new process will be loaded. So, this is you might have under known this if you have undergone operating system course, but I am not assuming that you have good understanding of this ok without the you know intricate understanding of OS, but as long as you know that what the process mean and how a process can be run on a say a process that that method knowledge is enough to understand the different features that are provided by the user name and you and whatever I am doing this today and even in subsequent classes ok. So, process is a programming solution. The components of processes are the code to be executed, the program to be executed. The data the program uses while executing the code ok and the resources required by the program such as heap or stack. See I am I am not maybe open about heap for a moment you know for maybe in the beginning of the class something I have mentioned. Maybe let me tell you what the heap and you know stack means. This is ok this is stack because going downward ok. This is some memory ok in the memory this is the heap. So, you might have come across you know if you have written a heap program MLOCK ok and you know this you would have come across this particular function call that means it is getting some dynamically allocated memory ok and then the program uses that memory which will be allocated from the stack sorry from the heap and then what happens it may release the pre the memory and then it goes back to the heap and then some other time and some other process or maybe same process ok. It is all depends on how it is maintained it is maintained by the wires or by individual it is maintained at the process level. In case what happens is the heap space will be given whenever it is required and then the program uses it and release it. So, this kind of heap and stack normally is managed by OS so they will also be there in the as a part of the resources for a process and state of the execution is maintaining the register and the CPSR values. So, so when a process needs to be and then a new process have to come has to come into the system into the processor for execution because I am talking about only single processor then what happens is all these things ok do not think that every time code is coming and sitting in the processor no no because code will be residing in the memory and then it is being accessed whenever it is needed. So, instructions are immediately accessed similarly data is also residing in the memory and whenever some data is accessed and something is written back. So, they as a as a know the whole chunk of the data code is residing in the main memory only but pieces of that will come to the program processor and then get executed and then based on the execution the data comes moves between these two. So, when we say during a process is saved some state is maintained here in terms of register values those things need to be saved ok. So, that may be a context ok which is maintained by the OS and then for each process there will be a process ID and then it maintains that particular context of a process in its own structure and then it makes no makes make sure that you know one process goes out and another process comes in. So, it will be very difficult to go into details of this because it will become another opportunity to compose. So, I am just talking with this I assume to assume that this much of instruction is enough for this particular course from this context of the course ok. So, these are the contents are to be go concerned with the particular process. So, based on event ok I will tell you what are the events possible even OS may say a state of the active process and may restore the state of a new process where it says it normally states in the OS system area where it is maintaining the context of each of the processes in the system. Because only OS knows which process is running and which process are residing in the memory as a background job and then which what state it is all those things ok. Now, what what is the context switch? That means a switching between one process to other. So, what must get saved on a context switch everything that the mix process may damage. That means if it is going to be modified then it is better to save them. So, program counter will be came by a new program which is coming into the SSW the program status word will be as well as general process and any floating point register. So, normally what happens is a floating point is we do not know suppose there are so many processes running in the system P1, P2 ok. The processor as such now ARM processor does not know or the OS running may not know whether a particular process ok is going to use the co-processor or not. So, normally what happens is only when a process needs the co-processor or you know floating point processors by you know to this this week then it may be having some co-processor instruction in it and that will be executed by the processor. So, normally co-processor is getting saved into the context only when a process wants it ok it is not always. But you are sure that every process needs the registers in the processor ARM. So, that has to be saved by default but co-processor may be saved only when it is needed ok. This keep in mind because I am mentioning here I thought I would discuss upon that. So, as well as memory and code needs to be not that it is saving from the processor it has to be. So, that needs to be taken care of ok it cannot access anything else other than its own area. So, that is where we need the function idea MPU ok. You may wonder why I am not coming to the MPU at all I am talking about process context which and all that. The reason behind is that you should know the intent ok we should know why we need an MPU before we start learning about what is inside. So, it is needed when we have multiple processors running in the system and multiple processors they have their own code and data. So, when a particular process is running suppose P2 is occupying the C3 in the home processor it should only restrict its accesses to the code and data of its own area and it should not respect this. But can you guarantee that they do always access only this if a proper process is there it may, but by if there is a you know a implicit sorry inadvertent mistake or may be intentional access could happen. So, in that case what happens it will may intentionally try to access the some other part of the memory. So, during that time we are there should be some provision that is supported by hardware to protect it from access from other processors so, that is what we are coming to ok. As to the some file access is that why a proper sign manager may be made ok file system ok scheduling and context switch. So, any process may give up the CPU ok give up the CPU means it may willingly wants to go out of the CPU. By performing an IO operation when it there is a IO operation why is there is a control because all IO operations are managed by OS ok why I will give one example suppose P process P is there P2 is there both of them are trying to output on to a serial port ok call it as UR ok this is a peripheral device and it is you can write it into this and then the character will come out and suppose you are connected into a PC ok PC is there and showing the old clear to display ok. So, if it is connected to the serial port now suppose P process P1 has put on hello world ok and in that way it gets scheduled out and then P2 gets the control of ARM ok ARM processor now P2 also tries writing to UR. So, as you know no hello world could have been written into some buffer and then the UR is trying to put it into the serial port and then it will take time because of the bar rate so you say if it is no 96th standard bar rate it will take no hello lot of time compared to the execution speed so the characters may be hello world may be hello has come world has not come then P2 has P2 also is interested in sending some characters out and it is writing may be how are you now what will happen hello will come then how are you will start them the buffer or it may stop this buffer from you know it may overwrite it it will do it so that whatever P process P1 want as that may get overwritten so we should not allow the processors to access their peripheral directly there should be some controller that is a OS so that it can order the sequence of processors and the suppose if it is busy with the previous one it may hold the access of this something like that so there should be some that OS will bring in that protection so in that case what happens is when this is executed OS gets the control because it is waiting for a character to be you know entered by the processor you know some user this process may have to wait for long so that time what happens is the OS may bring in another process to execute so this may be one of the reason for a new process to come into the processor may be the process wants to wait for some event to happen or some buffer to be very free or it may say that I want to sleep for 10 seconds the process needs to wait for 10 seconds that means what a new process can come into the processor so it will give up the CPU or it can wait for a device interrupt to happen maybe it has given a file access and then waiting for the file to be copied by the DMA to the memory before it can do any useful work and it can terminate itself they say that okay execute or no execute something to kill itself so in that case the process will terminate by itself so these are the reasons where a process may go out of the CPU and a new process may come into the CPU and then other one is OS can possibly schedule it so there are some scheduling mechanism where each process is given a time slide okay for each process to run so OS may decide that okay your time of 10 millisecond or whatever is there over so this has to go out and then now new another process in the release you may come so this kind of a priority in a new process with a higher priority has become ready so whatever may be the state of the low priority it should be thrown out and then a new higher priority will come out or a page fault the current process has access something and page fault has happened okay then also there are possibility of a new process coming so whenever when you give up the CPU means what has been since your current process out and get another process in that is what is the job of the OS okay so this is a different scheduling concept just thought I will just give a higher level overview of OS okay now let us go into more detail what is required for us in the CPU now typically now if you assume it is a lower address and this is a higher address okay because we are assuming that lower addresses are having no memory okay the system related code and data and then even the interrupt vectors okay IVT interrupt vector table is also part of the system so they are all deciding in one part of the memory okay and then the user program will be running here okay this is a typical scenario of how the layout of memory is used by operating system user programs okay so it could be that in some one process there are multiple process a job and task or process both you know in other the patient they are saying maybe if you go into the detail of particular OS it may be different but at this moment we are not bothered about those details so different processes may be occupying different parts of the memory okay that you should know okay so the CPU is reflected among them there is a single CPU sitting okay CPU and processor or what I mean by that is the on processor okay course which is used by all of them but in term one one guy will use it then one job will go and another job will come and it will be executed when I say it is using me that job is getting executed okay those instructions are getting executed by the processor and then it will now keep it here with the help of OS of course and then the new process will come in and then they will start having okay so this is the context so that we understand the protection requirement now I am going with little more detail as I mentioned to you our lower addresses are here okay sometimes it is drawn like this and then sometimes I put the lower address down and then write the higher address there so you may get confused which is why so I am just mentioning it for your clarity okay let us change the color as when the glues are long okay now what happens here this is the OS okay the structure is a scheduler actually OS now there are multiple processes which are already in the system okay who created the process OS creates the processes and they are all there now there are some access writes defined so here you see your process A when while executing you know that it can execute a branch with an object right branch with an object okay or with a label branch with a link register and then what happens it is moving to another address the instruction it starts executing from there now this address cannot be mapped to a location or area of memory which is meant for other process okay in the sense if it is not allowed to execute okay especially you know execution may not be allowed okay but sharing of data is allowed you know you can share data between multiple processes so that is why at that time we may have a shared memory which is in the system and we allow the process then in that case now this may not be a part of this process B this area it may be a shared memory between B and A in this case it may allow this access but code access is not allowed okay in some places because process A and C they do not have anything in common they are not executing anything you know for a particular common application. So, they may not have to share any data between them so, it is not allowed. So, that kind of a restriction may be there the decision may reduce know access restriction or even data access restriction and then may be you may also have some kind of a part of the memory of OS may be data allocation may be accessed by the processes because if it wants some support of the OS it will do it to call in the system calls ok that is why we call it a system call. So, it may not access it directly it will access the OS calls which will allow your process to use some of the resources cannot over or even any locking mechanism mutate anything you know any OS features can be accessed. So, this way we have to protect the OS first of all from the rest of the process and then we have to protect each of the processes from other processes running in the system. So, these are all can be done with a support of the processor that is what we are going to see now how it is implemented. Now, let us see what are the protective systems are there are two things shielding a system resources when I say resources and other task from unwanted access is called protection other task means the process area of the other task from unwanted access is called protection. Now, two methods are there one is unprotected system what I mean the unprotected means it relies solely on software to protect the system resources need to have cooperative tasks for reliable functioning what I mean by that is suppose I do not have MPU in the system ok because I do not have space in the SOC which is the very small SOC ok MPU also is a hardware right it accesses some part of the SIP. So, I do not want MPU I have decided that I will not use the MPU in the system I have built a SOC with the ARM processor ok. Then there is a that will be a possible that there are systems without MPU, but still I can support multiple processes in it provided they are all cooperative task what I mean by that is they know what their limitations are what their address limits are and then they are all written well written of course, that matter and will test it. So, that they do not try you know access inadvertently into the other area for the problem ok. And there is no OS may be OS is there because it is multiple processors are there a simple small micro panel may be there to create these processors, but we have to manage it ok. So, how without MPU is difficult we have to have a reliable functioning of these processors to make this you know this system run reliably ok, but what the advantage we get we get you know we there is no overhead of MPU or overhead of protection and other limitation you know hardware limitation, hardware functionalities which are complex they are not there in the system. But it has it has to be very very cooperative task for a reliable functioning otherwise they may disturb the normal functionality. Now what is the protected system here relies on both hardware and software to protect the system also ok. I will I will tell you why software is also needed because that I told you MPU needs to be configured first ok, configured in the sense it should be enabled, it should be configured which memory is having what access which processor has its own area and these are the other processors running what is their protection mechanism all this needs to be programmed into the MPU MPU who does it using the co-processor instruction you know MRC and MC are similar to cache, we exchange some contents into you know from the co-processor register and then from ARM register to co-processor we write something into some register and then this guys behaves perfectly it starts functioning as it is expected to we start protecting the system. So, prior to the MPU enabling the system is open to anybody ok. So, we need some software which runs at the beginning and then starts protecting different areas of memory and then starts giving the control to the different processors. So, software is required to configure the system ok that is sometime it is part of the you know most of the time it is part of the OS job, but I am trying to tell you why both are needed and dedicated hardware enforces resource ownership and restricted act. So, it you know who is the owner of the particular area of memory is controlled by the hardware ok very good. So, let us change colors for a ok now protection hardware in ARM ok what is the hardware? So, ARM provides several processors equipped with hardware that actively protects the system one is MPU I told you MMU I mentioned that MMU includes MPU from standard MPU ok. MPU provides hardware protection of several designated regions. So, we I told you different regions of processors are there the different area of memory is called region ok. I will explain you more about that MMU provides protection and has virtual memory capability ok. Let us not bother about this now because anyway we have the next question talking about that ok. Now, let us give a see a overview of you know what all systems have MPU in ARM CPUs which are used in embedded system with fixed or controlled application program do not require a full memory ok. So, suppose if we decide this is the area of particular you know physical memory is limited ok and then the number of processors running is also limited fixed ok we are not going to dynamically create multiple processors and then try to look for space. So, in the case what we can do is we can in the memory we can allocate some different locations of the memory for different processors and then and then maybe we need MPU functionality. So, that the protection is done by hardware right we can start executing this code multiple processors will be in the system and they will be reliably running as long as the number of processors are fixed and the area that they are going to use are also fixed and these are all controlled application program ok. That means, it is not going to go in terms of size in terms of display you know memory requirement and then the personalities are all well defined. So, in this kind of scenario we can go away with MMU. So, for that system a simpler MPU functionality PPUs which are the CPUs that is ARM CPUs which use MPUs are this and this ok. Let me give you a overview. So, these are all the advance versions of ARM ok and when I talk about the whole SOC it is a CPU if I talk about only the core it is a processor ok if you remember. So, CPU is a bigger present. So, these are all see you know different cores inside that see you know CPU. Now, they may have number of regions most of them are 8 ok which are either can be considered separately as instruction and data region or the regions are memory regions which can be considered separately as instruction region and data region or they cannot be ok. It is a common area for both instruction and data ok no no is there for this core. But there is one which is unique which is 940 just for 16 cores. But still the numbering of this regions are always 0 to 7 ok I will be talking about this, but there will be an instruction region which are varying from 0 to 7 and data regions which are varying from 0 to 7. So, what I mean by region a region is the some part of the memory ok. So, how many such regions I can have 8 regions we can have in the ARM processor and some can be identified that it is an instruction region some can be algebra as data region. So, let us not worry about these regions you know because these numbers and things will you know it is not the need you know you can always look at the manual to understand them or you do not need to look them up ok. So, what you need to know is at a higher level some you know 940 has this you know support for both instruction and data can be considered and as a different two regions. And whereas, these two we have a limited 0 to 7 8 regions, but you can choose ok 0 region is a instruction and the rest of it for data region we can consider it whereas, here we cannot even identify a region is a data instruction they are only featured as a region single region ok. Very good we are let us get into MPU ok. So, two major classes of resources that need to monitoring that is memory system and peripherals I told you that memory and peripherals are mapped to the same peripherals are also memory mapped ok. That means, the peripherals registers also accessed as a memory and then. So, LDM or SPM or LDR or SPR are used to access them peripherals. So, they are all mapping into some part of the memory. So, we need protection for them also or some attributes specifically means for peripherals. So, that can be achieved by using MP. So, peripherals are always written generally memory mapped I told you MP uses the same method to protect both the type of users. So, it does not differentiate between those these two instructions are same ok. And you can define a different attribute for each of the regions ok. I will kind of you know tell you what is what our attributes are and we can different regions of the memory can be treated separately differently ok. What is the region in MP? An ARM MP uses regions to support and manage system protection. The region uses type of attribute. Still I have not told you wait a minute. Process of course, holes these attributes in several CT15 registers. So, some attributes are there for each region ok some memory part of the memory there is another another part of the memory they are also they are for different part of the memory and they have different attributes. So, this is all maintained in the CT15 CT15 is for coprocessor 15 registers. So, the MPU as I mentioned is three you know implemented as a coprocessor in the component. So, I will give you region by a number ok which ranges between 0 and 7. So, I told you there are eight regions. So, the numbers are there which are varying from 0 to 7 and regions are independent of whether the core has a 1 mm or forward architecture. So, this is whether it treats data and instruction number as separate or unified single memory does not matter. The regions are same for both ok the way it handles for same. Now, let us talk about attribute. Following are the set of attributes. The region is defined by a starting address and then let me change color see every region is again you have to remember that it is a part of memory area nothing but a memory area. So, if I need to identify a particular part of the memory. So, suppose it is 0 and this address is may be some 20,000 hexagonal ok this is some 50,000. So, like this I am identifying different areas in the memory. Now, you have to mention what is a start address and then what is a length ok length or size whatever you call. So, these two will exactly tell you what is a start address of the region and what is the end address of the region once you are adding to these two parameters you can find out. So, we need this region is defined by that. Access permission could be any of this that means a particular area in the memory can be both read and write what I mean by that if a processor is executing an instruction when will the read or write will happen only when it is doing some LDR, LDR or SDR ok SDR, LDR but all load instructions are so instruction. So, especially for a data ok and for a code area it is the instruction. So, anyway there is no read rate for a code area. So, first of all code area ok has to be read only ok hardly you find a reason for it to be a read rate right this is understood. Now, data area there are two possibilities of data area one could be that I want a constant location ok I store all the constants in the program constant you might have seen it in the C program. So, I want to keep all the constant here that means what this a data area which is maintaining constant values to not be written by even our own program the program the suppose process one is having the owning this address ok its own range ok assume that P1 is having this code also, but that does not mean that the process can write into its own code area right it can read from it, but it cannot write into the code area similarly it cannot write into some part of the data area because it is the constant. So, we do not want run time this area is modified we do not want this to be modified. So, that way we can say that as a particular data area is read only and then some area we want the data to be written and then read then written. So, it can be read right ok, but you may say that some other area is which is not in its own preview this is a P2 we should we have a no access. So, we need access permissions which are one of this there is no read as you know permission like write only ok please remember it cannot be if you want to write you have to read that rotation first to write. So, you know or there will not be any need for only write only access to a particular part of the memory ok. So, normally it is not supported so, we do not see that ok. And then you have cache policy see though as when I spoke about cache I only talk about cache there, but suddenly when you when I am talking about NTU cache is coming because cache can be there without an MMU ok cache can be here and then the address may go here as well as it will go to this guy ok and then it will go to memory ok. So, sorry ok so, it is not that while NTU is there cache cannot be there cache can be can very well be there only MMU access cannot be there. So, cache can be there in that case what happens we need to have some features attributes which are related to cache why we are talking about memory attributes ok. So, we can associate some part of the memory a region whether it can be cache ok or whether it can be a write to policy or write back policy ok there is kind of a different properties can be there as part of particular region of memory if the system supports cache also. So, because we are talking about memory memory might have this system may have a cache. So, we need to have a a feature supported in the NTU so that if the cache present then we can assume how to we can consider the NTU so that cache is also behavior is also managed that is very important to have in mind and then similarly write buffer can be there it can be as I told you with the people which writes into the memory ok write buffer we will talk about it in detail. So, if there is a write buffer whether whether it can goes to a buffer or not that is the decision which you can you can decide. Controlled access based on processor mode this is a another thing which I have not told you a ARM processor as you remember it has got a user mode then supervisor mode system mode user mode or system mode and then there are FIQ IRQ ABOTS all that we saw and if you remember recall ok these are all supervisor mode ok with your own bank register ok and then system mode has a it is also part of supervisor mode ok, but if they it is uses the same register set as user mode. So, there are some control things coming out of the processor which will give you indication of NO PCIP then it will give you indication of whether it is in the supervisor mode or user mode. So, some protection can be given some privileges can be given based on the mode this is very important because normally OS will be running in the supervisor mode ok and then the all the user programs will be running in the user mode ok then we can easily protect the OS code OS code will be accessed only by the supervisor code which is in the OS code which is running only in the supervisor mode whereas user processors may not be able to access them. So, NPU has to know which mode the processor is in ok now what are the rules for region there are several rules that govern the region regions can overlap other regions. So, I can have a region I so far I have showing you region is not overlapping with other one. Now, suppose I can I am given a freedom to define a region with a overlapping ok. So, this is the main memory and there can be a region without overlapping with other region these two are one region and this is another region. So, this there is a overlap region there is a confusion now if overlap region is there how that is behave I will explain you then you will understand that regions are assigned with priority number that is independent of the privilege assigned to them. So, privilege mode is user or privilege mode ok, but priority number is defined ok that is a region number which we are giving. So, if the number is higher then it is higher higher privilege 0 to 7 of the region. So, this will be privilege is you know priority is higher than this, but privilege is different privilege is whether user mode or privilege mode whether the processor is in this mode it talks about that, but you can have a region with a higher priority number given to the user process ok. Similarly, we can have a lower one given to the kernel process ok a privilege process. So, I will explain you that context context then you will know then regions overlap the attributes of region with the highest priority number state privilege. That means, if I have I will explain you if if a priority number is higher then that is having a higher privilege that means what in the overlap region suppose two regions are overlapping I told you ok there are two regions overlapping in the in this ways ok. Now, suppose ARM processor is giving an address which is calling under this region it will not know whether to take this attribute or can it take this attribute belonging to this. In the case what happens is if this region happens to be 3 and this region happens to be 0 priority number then the attribute belonging to 3 will be considered and taken for this. What I mean by attribute for this means whether what kind of a cache behavior what has the right behavior right buffer is enabled or not or ok this kind of a different properties of the region or as per this region because this we do it when it is two regions are overlapping the region number with the higher priority numbers attributes are considered as long as it is within that region. Once it comes here it will go to this attribute once the address access is happening here this attribute should be used by the processor. So, the priority only applies over the address within the overlap region ok some more rules the region starting address must be multiple of this type suppose I will tell you the size is 4k ok you are right the region starting address should also be aligned to 4k that means what a given an address 4 kilobyte will of ok how many bits of the address progress you can know now by now ok. So, the address starting address ok has to be map aligned to this type that means all this will be 0 now what happens if suppose if it is a 8k one more bit ok that also will be 0 that means the starting address is aligned on 8 kilobyte so and the size is also very big we cannot the arbitrary sizes so whatever is the size given there are 6 number of sizes given in the system and you can define a region of that size and then which is aligned on that address that means that particular address that is the size occupied all that will be 0 so that the region is starting from that aligned address ok so given sizes are also any power of 2 it has to be any power of 2 and varying from 4 kilobyte to 4 gigabyte so you should now know the memory total memory that can be accessed by the processor is 4 gigabyte correct 30 degree so the region can be of maximum size 4 gigabyte it can be more than that you can also define a region which is you know covering the whole memory area of the processor between that we can define some other smaller trillions maybe starting with 4 kilobyte ok we can define a region maybe this is 8 kilobyte something like that you can keep on defining whatever regions you need of only these sizes ok it will 21 values you can go to maybe here 1 MB then you will start or 2 power 2 right so you are starting with 2 power 13 you know like that you can go on till 2 power 32 which is a 4 gigabyte so only these sizes are there possible to define in the as a region you cannot arbitrarily say that 200 kilobyte I want to define no you cannot ok this is not a power of 2 and you know only these kind of numbers which are all given in the book you can make you want or you can find out yourself process times ok accessing an area of main memory instead of define region this is in an app so I have not told you how mpu operates mpu what is that mpu doing suppose you have configured it and then no I define that system ok saying that 0 to 1 gigabyte only is there ok in this memory so I said that ok all these are all no accessible but beyond this there is nothing ok only one region is defined and this is here now suppose process mpu gets an address from the processor which is beyond this 1 gigi the mpu will try to see what are the regions are there define so only one region is there which is assume that it is a region 0 it checks whether this address which is suppose I am accessing address which is above this it will see that whether it falls within the defined region in the system because I have enabled mpu so it will be checking for any addresses coming from the processor needs to be within one of the regions defined in the system because I have defined only one region of size 1 gigi and the address happens to be more than that something outside this then it will create then get an award so far I said that the memory award data award or instruction award comes from a memory unit mean or the memory unit memory unit means it could be mpu also mpu also ok so now you may get more detail about who will give which award signals to the processor so the processor will go to the intraposter table and it will go to all that whatever we have discussed earlier all that will happen so mpu is continuously looking at the addresses once it is enabled it will be looking at addresses have you know going in the you know what the processor is accessing both for instruction and data and it will be checking against the region so it is all done in hardware that is why I am telling you it has to be done in hardware because it is happening every cycle every m clock cycle this is happening the comparison of all the addresses and then try to see whether it is allowed or not it needs to be done in the single cycle so you cannot do it in software again it has to be done in hardware but you configure it using software and then leave it to the mpu to do its job ok I hope this is clear to you so it could result into pre-fetch or data apart now what are the overlapping regions why we need it ok I will explain this now overlapping regions occur when some portion of the memory is assigned to one region I will give an example so overlapping regions provide greater flexibility of assigning decent access permission because you have two regions so you can give two different access permissions to both of them but how is it giving a flexibility let us see an example ok we will remove all the now you have a system with only 256 kb ok see this these numbers are chosen such a way that you can do it ok so it is very you should know even 32 kb is far off too so you see the shaded region the dark shade one is privileged access that means it is meant for may be OIS code why is it given a lower address that has also been a purpose 00 is here why is it given 00 is there in the lower address here ok there are some configuration possible to keep the you know IVT interpreter table as a high address but I am not talking about it because the system has only this much memory the interpreter table has to be here and it should be protected that is why it is having a privileged access and then the rest of it is having a user access ok now you see the user access is overlapping with this way also that means this user process will have a free access to this way ok why it will not have see the number here very very important if it was reversed then what I have said just now was possible but it is chosen very intelligently that region 0 is given to the user processors to access and then this is the system memory is given a region of 1 so even if the user process is running the ARM processor will be in a user mode correct and it is generating an address to access this location by mistake or intelligently the NPU will wake up it is always awake ok NPU will look at I am getting an address overlapping with this region as well as this region now what the processor of job of NPU is to find out who is having a higher priority number this guy then whose attributes it should consider or validating whether this access is valid or not it should take the attributes of this region which happens to be a privileged access then who is trying to access now which is running in the user space then create a abort ok do not allow the access to happen so the abort handler is implemented by whom by yf so it will go and see a user process was trying to access it so it will not try to fix every problem and then as I mentioned that during abort handling it fixes that and executes the same instruction if that was true for normal access where a page is spoiled or memory corruption because of some you know some memory space is not available or basically it is used for virtual memory where a new page has to be brought into the memory those kind of situations the user abort data abort has to restart the instruction whereas in this kind of cases if you restart it it will again encounter an abort because it is trying to access a system area so it will prevent the access and then take appropriate action as per what the yf is program to do so this is what the use of the overlapping region here if you see the region for a region 0 the start and end addresses will be including this particular area ok you know wonder that why I do I need to do I can have done it this is the user area right you agree to do it but this overlapping I will explain to you some more but if suppose you have mentioned it like this also there is no reason to get concerned because this will be protected that is one of the advantages the remaining memory has been to the user space except for this remaining are alerted the privilege region 1 is given a higher number because its attributes must take over the user so you are intentionally giving higher number so that its privileges are over overruling the privileges of this area ok very good now region 1 is not accessible in user mode though it is overlapping with region 0 though it is overlapping that does not mean that this guy can have an access to this region ok this is one of the uses of overlapping regions now I will explain you another one take a scenario where this diagram is not showing where the OS is running or OS code is may be I can keep an OS here everywhere ok OS may be there because it stops are created there must be some kernel somewhere so it is doing let us worry about that later now see what is happening here this is the you know white area are user regions ok it has got user access and there are only 2 regions region 0 or 0 region 3 2 regions are defined ok this is the higher privilege please remember higher privilege and region 0 because 3 is a bigger number right so it is a higher priority number please there is a priority number is higher that is to a user process ok it is a it is given with a purpose ok now since the regions are restricted to either this or this or only this much area and region 0 has a total area coming under this preview it has got an advantage what is that take a scenario where task 1 is running ok it is genuine and it is correct if it generates the address which is within the region ok so will it get allowed see region 3 is higher priority compared to region 0 so the attribute assigned to this area is belonging to the region 3 which says it is a user process and its address range is only this much that means when the user process is running this task 1 is running ok if it by mistake generates intentionally or whatever to access the area belonging to the other task what happens it is not within this region so even though the region 0 is the lower priority number because of the restriction in the area the range of address given to the higher priority number rest of it becomes inaccessible to the this way so when task 1 is running it can only access its own area can you get it it can only access its own area if it tries to access anything outside ok which attribute will it become active this region 0 attribute will become active because region 3 is not covering this region this area so region 0 becomes active what does region 0 says it is a privileged access and where what is the privileged level of the user process it is in the user mode so it does not have access to any of this so the background region indirectly protects the other task areas see what you are seeing is a memory area ok please remember and in a typical system in a embedded system in particular the there is no hard disk associated and then no processors are not brought in and go out brought out all those things are not happening but processors may be switching in the CPU ok processor may be in a switching that means P1 will run for some time P2 will run up for some time and then they may be switching but all of them are in the memory they reside in the memory each process is residing in the memory prior to the execution OS is also residing so you have to protect when this process is running we have to protect the other area and when this process is running we have to protect the other area so that is what is achieved by this kind of a overlap or background region we call the their region background region because that what is active when a particular task window is open ok even this task is running this window area is open when this task is running only this area is open for its access rest of it is protected similarly here so this whole thing is protected and only this is accessible so whereas when OS comes OS takes a control it will be running in which mode it will be an impregnated mode then it will have access of rolling data why? ok it will have access for some time none of the process will be running ok OS only will be running so this is also not active so now what happens this whole thing is accessible for the OS and you can have ok so what we can do is with this background region we will be able to now selectively enable access to a particular that is what is the another useful feature provided by the overlapped region is the background region higher priority region is pending a subset of the background region attribute the higher priority one changing the attribute so maybe you know in this scenario if privilege mode will not have access to the task area because once you give the access to the if you are accessing on task area then immediately that region will become active because it is nothing to do with the process being active in the process once the access comes that region gets activated so OS will not be allowed to access this region keep in mind ok it may not be needed once the processes are running there is no need for the OS to or any controller to access them it is all no individually given to the task that is how it is in this particular scenario that will be the access restriction ok correct now since dormant memory areas from unwanted what I mean by dormant is if this task is not active it is dormant so it has to be protected from other task which is running region 3 has a higher priority than region 0 even though region 0 has a higher privilege so region 0 has a higher privilege whereas region 3 has a higher priority so any address calling in this category will be controlled by the attributes assigned to the this process and when we say user the privilege mode can access any region only user cannot access the privilege mode so that way if you differentiate the access to different regions in terms of privileges then higher privilege can access other part of the memory so that way OS also can have an access so it is all depends on how is implemented ok so in terms of privileges higher privilege OS will not have an access sorry the lower privilege region user process will not have access to the higher privilege so that is the crux of the matter ok let us quickly see what are the CP15 registers with control the input on system control coprocessor control coprocessor is an on chip coprocessor ok so the CP15 I thought I will explain you so it controls the cache controller it controls NPU, MMU, it controls site buffer it also controls instruction prefetch buffer there is provision possible that you can have a prefetch buffer in the processor before instructions are accessed that can be decided in a prefetch buffer branch target cache it will come into play only when branch prediction and other things happening so let us not bother about that we can impact in some of the higher processors again processors of on family only I am talking about on family we can even configure the NDNS of the processor in a chip so we can change the big NDN to NDN may not be coming from the external signal as we saw in on 7 period so this kind of configuration of NDNS can also be controlled by the CP15 registers ok the control is affected through the reading and writing of CP15 registers now how do you write and write you know that co-processor instructions are there the instruction registers of 32 bits long and then it is access is restricted to only MRC and MVR and only in supervisor mode so any of the CP15 instruction can be executed only in the supervisor mode ok and then only these instructions can be executed still you cannot view any other co-processor instruction like no other CDP instruction and then co-processor transfer instruction we saw so many other co-processor instructions data processing and transfer instructions now from co-processor to memory transfer those things cannot be done on CP15 ok it is implemented such a way that only MRC and MRC MRC and MRC are instruction which transfer from on register to co-processor register and on co-processor co-processor register to on register so only these instructions are allowed that means you can only consider it and also it has to be in supervisor mode the processor has to be in supervisor mode if it is executing a CP15 instruction that means the co-processor instruction with the co-processor ID 15 instead of other co-processor instructions any attempted access in the user mode will cause undefined instruction so this is that you know you just recall what we saw earlier when we discussed about co-processor instruction so this is the register of on which can be put some value can be put and we can transfer it to a co-processor register and the co-processor registers are there are two and then you know that there are some operation code one more operation code is here additional operation code so in the CP15 world this register is called primary register and this is called secondary register I will tell you why I am bringing this this you can this is the MPU and MMU co-processor controllers they maintain two levels of registers and then they associate one register number along and on and then some more secondary registers are there suppose C co-processor register 0 we will have its own secondary register that means it will have another co-processor register 0 1 2 so they are all secondary registers and this is the primary register see effectively this there should be a space provided in the controller which is behaving like a co-processor co-processor 15 so when operand with CR0 comes then it will know that any number mentioned here is actually referring to the another set of registers in the system so it can always be built in such a way that when you are writing to a CR0 under CR0 one register you can always pass two parameters and then try to write in that so that is what is being done in implementing the MMU and MMU co-processor you can put some big patterns here here and then instead the co-processor to do different jobs in our sense it is a MMU or MTU co-processor now there are so many register numbers these are primary register numbers okay the protection unit has okay co-processor 15 okay these registers are there okay so if suppose it was a we are at a floating point processor its number may be no CP10 okay that is the number given to it it will have its own registers right we saw so many registers in the floating point register that is resolved by CPID so it is in a different area because the register itself has different registers so CP15 has the primary registers like this it will be varying from this and the different processors each of them so they are all given different functionalities when you write into this it is controlling the configuration of the system that is the way the hardware is designed this if you write into something it controls the cache controller if you write into this right buffer writing into this creates different access permissions for region and then you can write into some of the registers here to control the different regions in the system okay region 0 to 7 8 regions can be there and there will be different registers for each of them and you can control their length and size of the region so different CP15 registers are allocated who has done it because they are all IPs given by the ARM so they will follow this particular naming convention and the register number okay so CP15 registers that control the mpu are mpu are these registers only control the mpu they are all mpu related part of them controls the cache also some of them are here some of them controls the cache lockdown which we saw in the previous session these registers control the cache operation so these set of registers control only the mpu okay so how do you program the mpu so if we want to do any region size and location of a region we have to write into that I will explain you each of the registers how they are returned into so this I am giving an example here see when you are writing this instruction who is executing this instruction ARM is executing this is why programming the mpu instruction and then we say that okay I am interested in writing into c2c3c3 and then the secondary register happens to be this and then the other opcode is you know some value I can give 0 or some number and then from which register in the ARM I am transferring the value it is R to co-processor so I am just transferring some value in a particular register in the ARM whatever value store 32 bit value I am writing into the co-processor register which primary which secondary register we can mention so an ncr instruction once you view like this it will be embedded into the co-processor instruction and then put on the it will be executed when actually this instruction goes on the bus actually who is executing it actually the mpu executes it because it will grab this instruction because it will know that it is meant for it itself and then it will look at these values and then accordingly it will consider it itself so actually these instructions are fetched by ARM and then actually the job is done by the mpu ok it is not that ARM is doing but ARM has to provide the value ok so when it is this is executed this instruction is executed it is transferring the content from rn whichever register it has mentioned so ARM has to provide the content out and this this drive will read it that is all but and then accordingly it will program it inside ok so you should know how it is done otherwise we will have always the doubts in the back of the mind why secondary register, why primary register what really happens when you read a book you may get into all kinds of doubts of how do I understand this so you should know these instructions are actually accessed from the memory and it is executed by the processor ARM processor and ARM is you know writing the code you would have mentioned R1 or R2 and some proper value would have been written into those registers and then transferred to this now it may be OS code or you may be writing this code and then the mpu will grab this instruction because it will see that it is basically which is meant for me and then it will from what is coming from R1 while execution happens this ncr instruction executed then that value will be taken in by the ppu so sorry and it will come to the result so then based on whatever instructions we give it will be done ok I hope this is clear once you understand this the instruction that I am going to do now will be easier you know we should know how it is getting programmed that is what we are trying to understand now using these instructions which are actually registered on register to coprocessor transferred and we are writing into the coprocessor this is the coprocessor which are dedicated for some processor and it is expecting some parameter to be passed which coprocessor register which secondary register and what operation and which value based on the content of value in stored in the register you are mentioned here it will get configured ok that system control may happen or cache attribute may be written so or you may enable the npu or anything here or you may decide the regions all these things will be happening ok based on this mentioned here ok what is mentioned here region and size location can be configured then you need to consider age region so you need to measure the size and length you are starting address and the length of the region you have to mention so we need at least one big register to hold that values so a dedicated C0 to C7 8 registers are reserved for different regions in the programs ok and which is coming under C6 so under C6 there are multiple registers maintained inside what inside the npu where it is maintained ok I hope the whole scenario is clear to you ok so to configure each of the regions these registers are maintained so one small example system setup ok let us go by configing it ok now what are the steps involved in doing it see whatever here given we are going to do it in this step ok that means we will first decide a region number of regions in the memory ok how many regions are there and what are their addresses starting address and then all that will be decided by writing into proper register each region 1 0 to 7 you will write these values and then we will give different access permissions whether a particular region is the read only this is only read and write whatever you want you can give different regions different read access or access permissions whether user mode or privilege mode all that will be configured using these registers then if there is a write buffer in the system whether it can be buffered or not whether the data when it is written into the memory can go through the write buffer or it can it needs directly goes to the memory that we can enable we will do it using write buffer attributes and then we will say whether it can be cached or not whether the particular region can be cached or whether it is an instruction or data cached and know what kind of write policy can be applied on the region all that we will write after doing all these things once you decide all the attributes and then you have configure all of them then only we will come to the system control register this is the separate register under C1 there is a C0 we will enable the MPU cached then what happens the complete system with that now till that point none of them are enabled because that is the difference you should call it you cannot enable it and then start deciding what parameters or what attributes to give then there will be a mess the whole thing is failed so first you decide what each regions are and how they are going to be behaving what is the behavior we expect all that we decide based on writing into this register and then at the end we enable the MPU till then MPU will not be enabled that means it won't be active it won't look at the addresses coming on the bus it won't even recognize any regions so you can start filling the values left until it is enabled MPU will be no in a government state it will not do anything once it becomes active then it will start controlling so define the size and location first using this register 616 and then set access permissions for each region using C5 then please remember it is all under Cp15 so everything is inside the co-processor 15 inside that the different regions are there so it registers are there so they may be inside a MPU or it could be all captured and then they will be controlling the MPU doesn't matter how does it matter where it is exactly physically located but we should know that it is access to Cp15 and cache and write workers are accessed using controlled using this and then enable all of them using the C1 region now this is how the region is managed different regions are there they have different physical they have different addresses are given the sorting address and size and you have a priority number it will encode the priority and then decide what is the highest priority needs to be enabled because you have overlapping regions so if two regions are overlapping we have to choose the highest priority and then based on the highest priority attribute registers will be accessed higher priority attributes will be given that will decide whether a particular attribute is accessed whether it is cacheable or bufferable or whether user mode or privilege mode access is happening now one thing you should remember here notice it is only taking the top bits the bottom 12 bits are not only 20 bits okay this is 20 and this is 12 sorry okay so that is 20 bit is 1 MB okay the accesses are given with respect to this okay and then the regions are verified okay let me tell you what are the regions and then we will see the details in the next question okay any other generated by ARM is just against the region it calls under associated with that upon the highest priority number access is allowed based on permission or about happen okay so in this case we have put 20 because may be all the regions are 1 MB or more okay if it is a smaller regions then it could have taken the bits of it solves it okay here you can see that okay 12 bits are not used only the top 20 bits are okay this 12 bits so only the top 20 bits of address it could be top 20 bit or less than that or we can take always this because this will be 0 okay why you must be knowing it by now I told you that the sizes of the regions can start from 4KB to 4MB if the regions cannot be smaller than this okay and then also the starting address has to be aligned to the region size okay if it is a 4KB this is the smallest region you can have in the memory then the lower 12 bits of the addresses are addressing this so since I said that the starting address is aligned to this it will also be 0 or it will be 0 so it is enough if you take only the top 20 bits of address and store it in the register that is why you are keeping only this values okay this is the actually what I am showing this is Cp 15 C6 register either it could be C0 or up to C7 okay based on which region they are trying to program for example if you are programming a region for the R region 0 then C0 register and that C6 of C15 will be used and its value will be based on what is the region size if it is a 4KB starting at you know 20,000 okay then top 12 bits will be ignored and the remaining addresses this 200 will come here okay now should be 0 should be 0 and then this number n is a number varying from 11 to 31 actually what it means is 2 power 11 plus 1 so it will become 12 2 power 32 so what exactly means this corresponds to 4KB size this corresponds to 4GB size so you can choose that is why it was mentioning that power of 2 only will be given vary from 2 power 4 to 2 power 13 2 power 14 up to 2 power 32 can be given as one of the sizes of a region so we are deciding the size now that is decided by this 5 bit pattern stored here which will be interpreted like this okay inside the processor so once you enable it this bit you make it set then this region whatever address given will be checked that is and if the address whatever being accessed by ARM falls under this region then it will pick the attributes associated with this region 0 because it is B0 suppose it will be associated with region 0 now we may wonder where are the attributes of region 0 it is not here it is only this particular register holds only the region size and location okay so there are some other registers used for that vary from 4th yellow to 4th yellow and the region size and starting address are determined by the memory map of the system okay so we decide based on the memory map and where you want to use a particular region for what purpose okay access permission now that is used by this register okay C5 and C0 here you do not need to separate register for each region like what we used for a starting address and the region size in the previous case now we are trying to check one by one region size is done now we are trying to get the access permission of each region we want to initialize that is done by using this register and this is the big pattern used for each of it okay the first two which are used for region 0 this is for region 2 one like that and then what are the number 0 means no region 0 for value and then how are we giving it we are giving different access permissions to it as I mentioned supervisor may have a read rate permission for all the regions whereas user may have a restricted access to some of the regions okay so a typical example could be a restricted system resources you may want no access at all to the user only for the user supervisor system configurations may be user process wants to know what are the components of the process where the cache is there or not may be there is not that you want to take some decision so may be you want some configuration registers to be accessed by the user but you do not want the user to write into it and then correct the configuration so we only provide read only permission to that you can use it okay it is not that you need to provide that permission at all but you can use this kind of a configuration for a user region wherever they want a system configurations okay so you provide only read only access to the user but read rate for the supervisor mode here we want read rate to both but that does not mean that user can go and write anything into it limited region of limited part of the supervisor know area can be given access to the user because we want some target system resources okay with the user area so those kind of thing we want to give this kind of a permission okay okay see here user area only is even a user know read rate but not you know user may not have a read rate for the supervisor region because it has to be in the supervisor region supervisor mode for it to do a read rate otherwise so it is actually both in this region we have both the supervisor as well as both user also have a read rate we may give it for the user area where user processor wants to have access the system area will be in this region okay we will give this access position so that if this has an access may be some part of it may be read only OS normally will be here we do not want user to access at all only some shared resources we may give a user access but for a typical OS code application so what I am trying to say is suppose you have a region 0 okay given to the OS area OS area then you have to decide with access permission you will give to the OS area you have to choose this so that user has a no access to it and supervisor has a read rate access rate got it and we will define the start and end length also in that case it will be restricted access only OS will have access supervisor user will not have whereas if you are you know user process area you may give which one you may give this because you want to view complete read rate access for the user data area this own data area for a code may be you will give user code area you will give this access because user should not even user processor should not write into own code area so you may choose so this are the ways you will decide so cache and write buffer this is the cache and write buffer behavior for a particular region so we can decide to do one bit for cache okay one bit for cache for each region and then one bit for buffer and then write buffer so we can decide whether it is a not cache or non buffer or not cache type buffer or cache with write true policy or cache with a type type policy so a region of memory can have a different cache properties and the buffering properties so what are the typical scenario we may give write this this one we may give for a particular if you want suppose you want to give a region 0 we should be consider for this purpose then you set both of them to 1 okay you set both of them to 1 okay you see this so that region 0 will become write type write back cache okay and if you want a peripheral region you want to give not cache and non buffer you will write a 0 0 in that region region 7 is reserved for you know map to the peripheral area you may write a 0 here okay that is the way it is configured then finally you will enable that to enable the region as well as the hardware first of all regions can be there in the system but it is not enabled so you saw that E was there so if it is 0 a region will be defined okay all the parameters will be defined for a region but it is not enabled at a particular moment and then you can make it active at some point in time so the regions can come and go so that can be done by setting this bit of a particular region that is why I am giving you C0 to C7 whereas a particular MMU or cache or sorry MPU this is MPU so MPU or data cache or instruction cache if they support two different caches they will have a different MPU here and they will be set so then those caches will be enabled so this is the typical example of how to do it okay now I will show you a system with a small no I am not giving you how to program it but as you have seen all the registers how to write them so you will be able to achieve this okay you can take it as an example and then try to write into those registers okay to realize this and it is actually in the book also this reference book this has got this particular state of the event so you can verify it also or you can go through that particular example to understand it more okay so these regions are chosen like this okay a typical example this is a protected area where ODS related and the stack you know lower region IVT in the perspective it will be there and then there are active task regions are there there is some tag region which are shared by different processes and then IO devices very soon will start given some different we know active regions so region IV region III 2 are the different regions give us okay totally there are 4 regions in the system but it takes care of the complete area of ODS okay complete ODS so this will be a typical example I will like you to go through the book to see how this is all done so that you have a better understanding of this okay for the this will be will make your understanding much more clear so with this we will we are coming to an end of the class now so I hope it was useful I enjoyed really sharing this complicated information but I hope you are able to follow them and see you in the next class have a nice day bye bye