 Hello everyone, welcome to lecture on VHDL module for comparator and 4-bit full adder. At the end of this session students will be able to analyze design and implement comparator and 4-bit adders. Now, before starting with the actual session let us pause the video and think about what is a mean by components right. So, it is nothing but the simply a conventional code in that which is having which is nothing but your VHDL module, but which contains the library or package declaration plus entity and plus architecture. It can be declared in a architecture or package or in a block statement. And the declaration as a component is allowed reusability of your code means what happens when you are using a one you are designing a module which requires other module. So, that other module is can be used as a component in your module right. Now, let us start with the 2-bit comparator right. So, this figure 1 shows the 2-bit comparator which is having 2 inputs each one is of 2-bit right and comparator depending on this comparison whether it is equal whether it is greater than whether it is less than it has 3 outputs. So, this truth table show that according which input what will be the output if a equals to b y of 0 is 1 if a greater than b y of 1 is 1 and if a less than b y of 2 is 1 right. So, if you consider this y is 3-bit output right. So, now we know the inputs and outputs of our system we know the internal working how it is going to work. Now, let us go for the VHDL module of that right. So, this is the VHDL module created using the Xilinx. This one is divided into 3 main part first part is a library declaration part, second part is a entity declaration and the third part is a architecture declaration. Entity declaration in which you are using which library you have to mention that. So, here we are using IEEE library so, library IEEE from that which package we are using. So, that is use IEEE dot std logic 1164 this package is included from that we are using all. So, that is why dot all is there right. Second part as I said entity declaration so, entity comparator entity name is then we have to write the port declaration in that we have to mention what are the inputs and what are the outputs. Now, the inputs are a and b both are 2-bit so, that is why it is a bit vector 1 down to 0 or you can write 0 to 1. Output is again y, y is the output again it is of 3-bit y 0 y 1 and y 2 so, that is why it is again bit vector 2 down to 0. Then entity end now the third part is architecture part. So, architecture architecture name of the entity name same name supposed to be used is architecture begin you have to write the begin keyword. Now, we know the truth table from that to the truth table we are just writing over here y equals to 0 0 1 when a equals to b following the truth table else 0 1 0 when a greater than b else 1 0 0 when a less than b. So, 0 0 1 over here means y of 0 bit is 1, here y of 1 bit is 1 and here y of 2 bit is 1 right depending on this condition right. Once you done with that declaration part concurrent statement all the concurrent statements in your architecture you have to end the architecture so, end architecture that is the architecture name right. Once you done with the BHDL model you can verify that with the help of simulation. So, I use the inbuilt simulation of the Xilinx which I use to create the BHDL model. So, these are the simulation outputs so, here you can see that 2 bit signals a and b. So, if you consider this condition both are 0 0 here a is 0 0 b is also 0 0 right in that case both are equal means output is 0 0 1. Now, in this condition situation at the time I change the value of 0 0 of a bit is 0 0 to 0 1 and keep the value 0 0 of b bit in that case it is 0 1 0. Now, here I keep a similar to 0 1 only I change the value of b now 1 1 b is greater so, it is having 1 0 0. So, I verified all the 3 cases of 2 bit comparator so, according this using the simulation you can verify the working of your BHDL model. So, now let us go for the 4 bit full adder now this is the 4 bit full adder now if you observe the diagram these 4 bit complete 4 bit full adder is implemented or created with the help of 4 full adders 1 bit full adder. So, this if you consider this is a single bit full adder again this one is single bit full adder again this one is single bit full adder. So, 4 single bit full adders are used and if you consider this complete box as a one design you can say that this is a 4 bit full adder. So, means what you can implement 4 bit full adder with the help of 4 1 bit full adder. So, you going to use or we can going to use 1 bit full adder as a component to design a 4 bit full adder. These are the inputs these are the outputs seen also input and see what is the output. Now, if you consider these 3 C1, C2 and C3 these are the internal signals which cannot be accessed by the user. So, we have to consider these also. So, now let us go for the BHDL model writing. So, first part obviously, library declaration part right then we have to write the entity. So, entity entity name right in that you have to write the port declaration in the port we have to mention what are the inputs and outputs A and B we just saw in a previous slide A and B are the inputs which is a type of vector. So, bit vector 3 down to 0 4 bit full adder we are designing. So, 3 down to 0 seen also input we just saw then S is output which is a type of vector again 3 down to 0 and C out these are the outputs we just declared over here which are having a interaction with the physical out word outside the word. But we are not mentioned over here about the C of 2, C of 1 and C of 3 why because those are not accessible by user which is not having access to the user. So, those signals supposed to be considered while writing the architecture right. So, now let us go for the architecture C architecture architecture name of entity name is now as I said we are designing 4 bit full adder using 4 1 bit full adder. So, we are using 1 bit full adder as a component. So, in previous video sessions we already studied about the 1 bit full adder the same full adder we have to write before writing this code and that full adder is used as a component. So, component full adder name component name this one this name supposed to be same as you used for the entity while creating the code for the full adder right and same port declaration supposed to be there after that end component. Now, here you can see we use 1 temporary signal. So, all these component declaration and signal declaration part is done before the begin of your architecture once you done with that architecture begin. Now, here seen is assigned to the temp of 0 right then these are the component instantiation we using we are using full adder as a component. So, we using 4 full adder 1 bit full adder. So, we required 4 component instantiation. So, FA0 full adder that is component name then port map this is a syntax for component instantiation. Now, in the port map we have to write the signals which are going to be mapped with these signals of the component. So, A of 0 is mapped with the A, B of 0 is mapped with the B, temp of 0 is mapped with the C in and S of 0 is mapped with the S and temp of 1 is mapped with the C right. Similarly, second component instantiation FA1 you can you have to relate this with the diagram full adder port map then signals associated with the FA1. Now, here A of 1 B of 1 now the whatever the output carry generated from the previous component instantiation is as a input right to the second component instantiation then it generates to output S of 1 and temp of 2 same for the third component instantiation and the fourth one. Once you get over here final output S of 3 and temp of 4 that temp of 4 is nothing, but your final C out. So, that going to be updated over here C out equals to temp of 4 then end architecture. Once you done with the VHDL module you can verify this with the help of simulation this is the simulation output you can verify that right. So, here if you see last case the C out is 1 because the both last bit 1 1 is there. So, because that carry will be generated so that carry is nothing, but the C out and this is the final sub right. These are the references. Thank you.