 Welcome to the second lecture on VHDL as part of the course digital system design with PLDs and FPGAs. The last class I gave an introduction to the language VHDL so we will have a quick run through the slides and come to reasonably serious part of the VHDL. So let us go to the slide. So basically we have looked at how it is evolved it stemmed from the some lacuna in the schematic in the sense that it does not it only represent the network I mean the interconnection of the components or net list and there was no hierarchy supported it was proprietary and it needed a design description because from the schematic you cannot make out the function of the circuit. And when you have a company has multiple vendors using multiple CAD tools integration understanding all becomes difficult. So for documentation describing the circuit for documenting this has started subsequently it was used for simulation because the description was unambiguous ultimately people thought why not use it to generate the circuit itself so three purposes. This is human readable as well as the computer algorithms work on it to do all these you know simulate and synthesis it support hierarchical design higher level construct library based design type strict type checking and all that. Basically VHDL has two description of a component as two part one is entity which is basically the name of the block inputs outputs the direction of it whether in or out and the data type and architecture is a functionality in terms of the input and output. We have taken an example of 4 bit equality comparator we know the circuit for XNOR gates and then AND gate and we have seen an example code as I said the inbuilt data type is bit which support only 0 and 1. So to be able to use something serious like tri-state and don't care and all that we use a data type called std underscore logic and we call it standard logic. So the standard to be able to use that we use this library and use as I said I will use the key words in green all other thing in blue. So that is why this library and use case and library as the like various packages and packages as components and so on inside and this is the common which cannot be nested. And this is the body of entity where the ports specify the input and output and name the direction and the data type and std logic vector is an array of standard logic. And we have seen in out in means input the input should come on the right hand side of the assignment and cannot come on the left out is output it should come on the left hand side of assignment. And we have some requirement if there is a local feedback or this output is used as input to the further circuit then you have to declare this as buffer then only you can use the output on the right hand side ok. But this is restriction in the sense that it cannot be used with multiple components. So we essentially use signal to circumvent that problem that means we will declare this as signal and assign the signal to an output pin ultimately there is in out which essentially means this particular signal or the port can drive out and also somebody when this is tristated cut off something and drives in and that is different from this and when you have this structure only you should use in out. And this specify the bit order this is a MS bit LS bit so depending on little n in or big n in you have to use this is the assignment operator this is the equality operator which say that equal is gets 1 and 1 is defined with the codes because in the library it is defined like that when a is equal to b else it is 0. So that is what is the kind of sample code and we have looked at all these in the comments the libraries the mode bit order and alpha numeric and underscore can be used not case sensitive first character should be alphabet the last character cannot be underscore and to underscore in succession is not allowed all that. And the architecture body before the begin you can declare many things and after the begin you have the statements these are the logic operators which is defined for bit but in the standard logic 1164 package this is overloaded for the standard logic data type and we have arithmetic and arithmetic operators and there is mode and rum and we have seen the difference this rum is the real works with the negative number the real mode of the computer science. And once again this is defined for integer and float for standard logic these operators are overloaded in this particular package standard logic unsigned then you have relational operators again this is overloaded for standard logic in standard logic arith and again shift operation shift logical shift arithmetic which is used for sign extension of two complement numbers and rotate all left and rotate all right and these are overloaded once again in standard logic arith. And we have seen aggregate operator if you have some signals of the same type and same size that can be aggregated together to a bus or a multi bit but more useful thing is to have an concatenation operation which will work for the same type but different size elements and we have looked at the precedence of various operators the priority precedence is ranging from 1 to 6 that means this is the highest precedence but when the same precedence is there it is left to right evaluation. But as I said it is better to use the appropriate parenthesis of bracket for easy readability and for understanding because maybe some people were used to some other language comes and read it they should not be confused for simple cases you can probably when you have a multiplication and addition you can use without brackets and now let us start today's part. If you look at the sample code see we have given a name for an entity entity some name is and end that name okay that is the kind of syntax and as I said semicolon is a kind of termination character but when it comes to architecture there is a separate name for the architecture okay at the beginning it looks little awkward because anyway you have defined some entity name why not use the architecture of eqcom you can say why give a name. So this suggests that in principle you can write multiple architecture for a single entity okay so in VHDL you may have a single entity but you could write multiple architecture and at the time of synthesizing or compiling for simulation you can say which particular architecture you need to use okay so how to specify that we will see later so at least we will look at what are what is a kind of idea behind multiple architectures okay what is the use of specifying multiple architectures so definitely one can think of this like you can have an architecture for simulation okay as I said at the beginning the VHDL anything you write using the syntax can be simulated there is no if you know the syntax of VHDL you write any code you go to the simulator and that whatever you have written can be simulated but unless you take care may not be synthesizable okay. So these two are different games all together it is unlike the sequential languages like SC program or any other computer languages where you can write the code that get executed that can be simulated but in VHDL there are anything you write you know it is syndactically correct logically correct can be simulated but it may not be able to synthesize that. So maybe you want to write you know you are developing a system and you want to quickly check whether it is the ideas are okay maybe you can write without much thinking much about the synthesis you can write a quick code and make sure that your idea is correct and then you can work on how to write a code which can synthesize that so that could be one use of the multiple architectures there is another use you know that you have again at the kind of overview lectures we have looked at this part there are constraints which is area and speed and we mention there that it is not that always it is possible to get a minimum area and maximum speed when you go for minimum area you might end up with large delay or less speed when you give implement something with a large area you might get less speed and we mention the ripple adder and the carry look ahead adder as an example simple example. So maybe when you write some entity and architecture you might write some architecture which gives a very minimal area but less speed or which gives a really good speed but the area may not be minimal and things like that and once again maybe you can write an architecture for you know suited for FPGA in a particular way we will see maybe how to write optimal code for FPGA PLD and all that maybe you write something specific to FPGA some code and something specific to PLD maybe something even specific to an async you know that whatever code you have written the FPGA has lot of inbuilt components and you might instantiate those components in the code which may not work in the case of async when you go to the async. So you could have architecture for FPGA one for PLD one for async and so on. So you see the VHDL you know idea of providing multiple architecture is a really good use it as and you should be able to use it and but in any case when you have multiple architecture before whether you simulate or synthesize at the beginning you have to choose which particular architecture you are going to use it okay that has to be specified and that syntax is called configuration as we proceed little ahead we will see that the configuration syntax. Now let us look at the design flow we will keep the FPGA and PLD in mind and the VHDL as a front end okay. So we let us look at the how the design methodology okay so we are assuming that we are designing for FPGA or PLD and we are describing the design in VHDL or verilog some kind of hardware description language that is the basic idea. So initially you start with the VHDL source code so you can imagine and some kind of editor here you enter the code normally editors give you some templates some GUI to like you specify the inputs and output and name of the entity that creates some template for kind of making the life easy. So there are editors available so you edit the VHDL code once you do that before proceeding with any of the further processes you do a functional simulation okay that means that whatever VHDL code you have written is simulated in a VHDL simulator okay. So here we are not dealing with the circuit we are dealing with the code okay so it is convenient because at the code level itself if there are some kind of logical errors that can be quickly corrected without going for the further steps. So you might start with VHDL do the functional simulation okay now these words you know the functional simulation there are words like behavioural simulation this might differ you know people may be you refer to some text books somebody else might call it behavioural simulation and they might make a difference between functional simulation and behavioural simulation and so on. My advice to you is that you do not get kind of you know bogged by the particular terminology use you get you understand the concept you understand the idea generally like you go for an interview somebody say that it should not be called functional simulation it should be called behavioural simulation agree with them or her so that you can get the job do not worry too much about the terminology okay. So these are not great you know something 10 commandments written on the tablet. So let us call it functional simulation for our course so you simulate maybe you find error or you come back correct you try it quite a bit and you get the correct code in the first place then you go for synthesis where you generate from the written code the net list or the equation or that we are generating the logic circuit in terms of gates and flip flops sometime the synthesis tool can be quite smart can be quite linked to the next processes sometime it will generate the circuit which is very specific to the device you use maybe the FPGA has some kind of combinational circuit elements the synthesis tool can generate circuit in terms of those okay. So this I am giving a kind of generic description but this can be very general or specific and things like that. So and once again you may not unless you write properly which we are going to learn how to write properly that this may not happen the synthesis may not happen. So in that case you have to get back and iterate and make sure that it synthesize the proper circuit okay. But after practice if you follow the strict rules there should not be any problem at this point you can go for a logic simulation that means here what you have simulated was a code but here what you are simulating is a circuit which implement the equivalent functionality whatever written here in the code the equivalent functionality in terms of the logic circuit is simulated here mind you at this point there are no delays suppose you have an AND gate you have written here and you give the inputs you can see that when you simulate at 100 nanosecond if one of the input change the output also change at 100 nanosecond because we have not used any device yet. So at this point there is no delay there is no mapping to the device so the functional simulation and logic simulation are kind of zero delay simulation because it is just the logic bare logic which is not kind of fitted into a particular device. So the next step is something called PAR or a place and route and or fitting okay normally in the case of FPGAs we call as PAR and the case of PLDs we call fitting and you have to give the constraints okay there are two type of constraints IO constraints and the typing constraints. So you know that the FPGAs are field programmable the PLDs are field programmable device. So you can there are a lot of generic IO pins so you can map your signals the inputs and output to the any of the user IO pins conveniently okay and so you have to specify suppose you have an address line A0 to A15 you have to say which pin A0 comes which pin A1 comes and so on. So that is IO constraints and we have seen the expression for minimum clock period in a register to register path. So it is possible that you can specify the timing constraints you can say at this point when the algorithm do the place and route like I would like to have a register to register path with the delay of 5 nanosecond because we are planning to clock the circuit at 200 MHz. So the clock period the minimum clock period can be specified. So depending on how you specify this place and route tool will keep the components closer it will use shorter wire to interconnect minimum number of switches to interconnect and so on. As it interconnects as it routes it keeps track of the timing and any time it exceeds say you have specified 5 nanosecond then it comes back and find an alternate path. So the timing constraints also can be specified at this point in time and if everything becomes successful you will get a configuration bit stream which can be used by a programming tool to program the FPGA or the PLD. But before doing that now having placed this particular circuit in an FPGA or a PLD we will be able to do the timing simulation that now the device now the tool knows that a particular register to register path takes so much delay or if it is a combinational circuit from the input to output how much delay it takes in terms of the resources of the FPGA the wire delays of the FPGA the delay of the switches that interconnect the wires and all that. So there is this tool can generate a timing model and instead of logic and functional simulation in the same simulator many a times the VHDL simulator use it to simulate with the timing model can simulate the timing. Now if you have an AND gate and you give the input at 100 nanosecond you will see the output is coming after some delays maybe it will come after say 102 nanosecond depending on the delays you know kind of incurred within the FPGA. So but only thing is that for complex circuit this is very time consuming because you have kind of detailed model of the wires, switches and the various blocks within the device. So to do a timing simulation which takes long time is quite cumbersome. So many a times the people at the beginning do something called static timing analysis. In all the simulation you know that you have the model of your the circuit you specify various input and you verify the output ok that is the basic game suppose you have a clock reset input you give the clock you reset it you give various input and you check the sequence of outputs ok that is how it is verified. In the case of timing simulation all the delays will be shown in the simulation but the static timing analysis is a very quick analysis where suppose you have a register to register path it is not that you give clock reset and input and try to check the output waveform but what is done is that all the delays from the source register to the destination register is added together and that is reported ok. So it is very fast but the real problem with static timing analysis is that it need not be accurate because in a complex circuit there are lot of paths there may be some say 6 registers and 12 destination registers and some of the path may not be active at all in real life but when you do static timing analysis there is no way for the tool to know which is the path active which is not the path active because you are not simulating it you are not giving clock and the state machine is not the controller is not active it is just the addition of the various block delays and the real behaviour of the circuit is not known that is not only if you really give the inputs and simulate it. The static timing analysis is a quick estimate and you have to tell the tool some paths are not used that is called false path maybe from source to destination everything may not happen in the next clock cycle maybe there is a source register which is clocked at 1 clock it goes through some kind of combinational circuit and after 2 clock cycle it may be clocked into the destination register but this tool has no way to know that so but when you do the timing simulation it is very clear but in static timing analysis as need to be told all these things that this path is not used this particular path take 2 clock cycles and so on but then it can be accurate and this is a very quick kind of estimate before going for timing simulation suppose you do the power and you do static timing analysis and it is satisfied then you can go for timing simulation maybe you have to iterate it in all these steps and at the end you can program it. So that is the design methodology of an FPGA with VHDL as a source and for that you have an editor you have a synthesis tool you have a place and route or fitting tool you have a constrained editor you have static timing analysis tool you have a programming tool and you have a simulator which does the function simulation logic simulation and the timing simulation and most of the component vendors the FPGA or the PLD vendors they give they have separate tools but they give a GUI integrated GUI with from which you can call the individual you know the components using the graphical user interface so it is convenient but they also allow you to write some kind of shell script to use it separate so that you can run it without the GUI because when you have complex design it may not be very convenient to sit in front of GUI and start clicking many selections it will be good whatever is the commonly used whatever is used for a project can be in a script form and you run the script and it writes output to the file various files maybe at the end of the 6 hours 8 hours or a day you can check the various outputs how it goes on things like that. So that is a design methodology as I said it uses an editor synthesis tool constrained editor power tool or fitting tool a simulator VHC or simulator which can do all these and a static timing analysis tool so that is the design methodology. So now let us look at the various ways of describing the components or the circuit the first thing is the data flow model this is what we have seen we have already seen the data flow model and we take as an example 4-bit equality comparator. So this is the library declaration, use declaration, entity declaration with the port so you have AB as input which is a 4-bit vector equal is a single bit output we have seen that and the architecture we give a name of this particular entity and you can declare many things it is a simple code so we need not declare the begin and you say equals is assigned or get 1 when A is equal to B else 0 ok that means that when A and B are equal equal will get 1 otherwise it will get 0. So this is a construct which is a concurrent statement when else and this is assignment operator this is the kind of relational operator it is checking whether A is equal to B and this is enough and this is called data flow because it shows the flow of the data from input to the output as once again as I said maybe some other literature textbook might show this by some other name but then you basically understand what is the idea behind it then latch on to the particular name because in our field we will be forced to use the metaphors like you know we call a hardware a platform and many things like that we borrow from the English some equivalent word. So do not bother too much about the real meaning you do not ask why it is called platform whether there is some kind of a train is coming to the platform also something like that no point so maybe some textbook might call it behavioural do not bother about it. So there is another way of describing the data flow model so let us see that the same thing exactly same thing the 4 bit equality comparator now instead of using a when else statement we are writing the literally the equation using the logical operators. So we are writing equals get this is the same circuit we have described for exclusive nor gates for a3, b3, a2, b2, a1, b1, a0, b0 the output of which is ANDed together so that is we are just writing a3, b3, a3, x0, b3 and a2, x0, b2 and a1, x0, b1 and so on ok. So for most people at least at the beginning this looks a better code than this ok because here we are describing the circuit so you might think that this will end up with a very nice circuit and this might end up with something kind of complex but you need not worry you just think of say a scenario instead of 4 bit equality comparator if you are using say 31 bit comparator for whatever reason. So then we will write here a, b is in standard logic vector 31 down to 0 and you know that this goes down all the way a31, b31, a30, b30 and so on all the way up to a0, b0. So this can be quite difficult to even if you copy paste edit all that and do it but if you come here the previous code you just you want a 32 bit equality comparator you just write 31 down to 0 and no change is required. So if you ask me whether the when else or the equation is better then definitely this is much more concise and we will see that you know this is for the tool this will generate the exactly same circuit as that and we will see how the synthesis tool kind of generate the circuit out of the description. So we have seen two data flow model one is using the when else concurrent statement and one uses the kind of logical operators like XNOR and all that and we will see how the synthesis really works later how these operators work what are the various concurrent statement how it can be used and what is the meaning as for a synthesis is concerned all that we will handle. Now we are looking at the various models of description so the first one was data flow model. So let us move on but before going further it is very important to consider this particular fact you know concurrency. So if you take a digital circuit suppose you take the case of equality comparator there are two input signal A and B which are 4 bit assume that there are two outputs maybe this is an equality comparator output this is a greater than output okay. So assume that if A is changing at 100 nanosecond so maybe say A was less than B then A becomes equal to B then Z changes. So essentially if A changes both Y and Z can change like suppose A was greater than B so Y was 1 Z was 0 okay. Now you change the A such that A is equal to B then Y transit from 1 to 0 and Z transit from 0 to 1. So for a change in the input both can change at the same time so but when you write an expression in a sequential language you have to write something first and something else second okay. So but you should know that it is not like a C language in a C language you write something sequentially and the execution happens from the top to bottom. You can the model is such that you take the first statement executed and update the result take the second one second instruction do the execution and update the results and so on. But in the case of a VHDL when something changes both output may have to change at the same time okay same time that does not mean you compute at the same time but at the same simulation time when you simulate a circuit both being concurrent has to be computed at the same simulation time that you should keep in mind it is not like a normal you know sequential language the VHDL both are Y and Z are concurrent they are active. So now let us look at little more serious example of that say we have a circuit like this we have an AB going to an AND gate which produces an internal signal called X which along with the CD goes to an XOR gate the output of XOR gate is called Y and that along with EF go to Z okay. Now suppose we have written in VHDL code the expression like this have a look look at the expression you see that Z is written first Z is described as E and F and Y and F Y is written as C nor D nor X X is written an A and B suppose the simulator is trying to simulate by going from top to bottom as in a C language say like initially suppose there was an event on A and it starts computing so Z is computed first using value of EF and Y so the Y will have the same old value as before and Z will remain same then Y is computed using the old value of X current value of X and C and D so Y is going to remain same and now the X is computed the A has changed A at 100 nanoseconds so X will change but nothing happens to Y and Z okay. So this is the concurrency problem as far as simulator is concerned okay when somebody writes a code like that simulator has somehow have to figure out saying that if you sequentially compute from top to bottom the real time behaviour of the circuit cannot be simulated. We will see how the simulator handles it but you get you try to understand the issue and you might say in a simple case like this why do you write like this you know deliberately I have shown Z fast, Y fast, second and X you know the third but you could as well you know reorient X, Y, Z but you think of a real life scenario when you design a CPU you break down into pieces and you give one piece to one designer second piece to another team, third piece to another team and a fourth team is trying sitting there on top and integrating interconnecting it together. So when you interconnect it is a complex code you know this particular block itself has lot of codes and when the top level everything is interconnected together and it is very difficult to analyse which way the data flows and you cannot keep the order and things will be messy and so simulator has a little tough job of resolving the concurrency from the sequentially written code but if you think of synthesis, synthesis has absolutely no problem whichever way you write it does not matter because like if you are trying to generate this circuit from this code it does not matter whether the Z is written fast or Y is written fast or X is written fast or in any particular order because this say X is A and B and Y is C nor D nor X so the moment X is there you just put this and when it comes to this place Y you get C nor D nor X so that is formed. So it really does not matter how the code is written which order the code is written as far as synthesis is concerned because synthesis tool is worried about the structure of the circuit not the real time behaviour but the simulator has to simulate the real time behaviour and it has to worry about the concurrency ok. So we will see how this is handled but I bring this particular issue to the front it is not the job of simulator and the job of synthesis tool is different synthesis tool looks at the structure of the circuit but the simulation tool worry about the real time behaviour of the circuit. We will see how it is handled but that you keep this in mind and let us move forward let us come to the second level of description model which is called behavioural model and we are taking the same example equality comparator so the library declaration is same entity ports everything is same but when it comes to the architecture it uses a particular syntax or the body called process ok. So the syntax is you can give some label for the process because there could be multiple processes in a particular architecture so you can give a name and the keyword is process and you open a bracket and you write some signals in the bracket and this is called sensitivity list that means this particular body of the process is sensitive to changes or events on this particular signal ok. So basically normally these are input signals as suppose you have a block with inputs A and B the input signals are written in the sensitivity list little more detail is required but then we will see that later. So you have inputs written in the sensitivity list when an event happens in the signals in the sensitivity list we are talking about the simulator. Simulator will run from the top to bottom and whatever is written as description is computed from the top to bottom once. So that is the idea of process and the process use the construct like if case you know the loops for loops and all that. So basically this allows this process body allows you to describe the behaviour of the circuit in a behavioural fashion using higher level constructs like if case for loops and all that that is why it is called behavioural model once again this terminology might be different in different textbooks different literature don't worry too much about it and don't again make you know kind of big out of this processes don't compare this with the multi process of the operating system. There is no great you know kind of parallel with that process maybe there is a kind of some kind of similarity in a computer science operating system processes the process to become active when there is some event on a particular signal. So maybe that is why it is called process here also this computation happens when there is an event on the signals in the sensitivity list then it goes from top to bottom. So here it is simple if something changes a changes it comes to this it says if a is equal to b equal get 1 else equal get 0 and if that is a syntax. So if something condition then output is assigned else output is assigned and you say n process the process is n that is all very simple and as I said it goes from sequentially from top to bottom. So when the simulator computes the behaviour whenever there is an event it goes from top to bottom once for a particular event okay otherwise if the second event happens again it goes from top to bottom okay. Now for the synthesis tool it is not going to bother about all these sensitivity list even happening and all that because synthesis tool is not worried about the real time behaviour. So it looks at this code what is written in the code in the code say if a is equal to b equal is 1 else equal is 0. So it generates the circuit matching this behaviour that is all okay. So it is equal and do the when else code when else said that equals get 1 when a is equal to b else it is 0. So it is identical to the when else if then else if then else is identical to when else only thing is that the if else is used in a process and mind you process is a sequential body you can use only if case or you know for loop you cannot write the when else or with select there is a syntax called which select within a process body you can only use if and kind of the case and all that. And definitely you cannot write if and case and all that in an architecture directly it has to be used within a sequential body like processes functions and procedures. So that you keep in mind that is the idea of process and I told about how the simulator looks at it how the synthesis tool looks at it and use higher level construct for the behavioural model. So even in this process there is a declaration region before the begin and the statement region after the begin. And here you can declare you cannot declare a signal as in the case of architecture you can declare a variable now okay. We will see how the variable works it works similar to a you know like a sequential language like C program. But what is the hardware significance we will try to make out that how the synthesis tool handles that variable we will see later. But you can declare variable you can define functions and procedures you can declare constants here in this kind of declaration region. And this is a statement region which uses these constructs. So let us look at the process is a sequential body and when I say sequential body it is a way simulator computes when and even happens it goes from top to bottom once. Synthesis tool is based on the whatever behaviour you state within the statement region there is nothing like top to bottom sequential execution and things like that. And as I said the process body has two parts one before the begin one after the begin before the begin you can have variables and constant declarations data type declaration function and procedure definition. In the statement part you can use higher level construct if then case when for loop and while loop none of the concurrent statement can be used here like which select when else and some generate and all that cannot be used here. And this cannot be used in a concurrent part of the code outside the process outside the functions of procedures this cannot be used that you should keep in mind. So that is about process and we will see some kind of the issues with the process if you are not careful. So look at this, this is the same process for the equality comparator but in setting A and B we write only A okay. Now it means that it is an equality comparator but which is sensitive only to A. That means you have an equality comparator with inputs A and B but if B changes the output won't change. Maybe A was 4, B was 3, output was 0 but B has become 4 but output won't become you know 1. So that is basic idea and if you write such a code and try to simulate it will show that behaviour that means it will be sensitive only to A but you know that given to a synthesis tool there is an issue because this is supposed to be a combinational circuit you cannot have in a combinational circuit kind of two inputs which respond to only changes in one input. If you have to have such a behaviour you need to have some kind of latches which is you know latching the B input and keeping it you know kind of on the edge of A and so on. You can imagine a circuit but it involves some kind of memory. So when you give such a code to synthesis tool and mind you as I said synthesis tool is not going to bother about the event happening on the sensitivity list and so on. So synthesis tool basically looks at the code the behavioural code written. So if given to a synthesis tool it will look at this and try to generate an equality comparator but given to a simulation tool it will generate an equality comparator it will simulate an equality comparator which is sensitive only to A. So there is an incompatibility between the simulation and synthesis when you write such a code and normally you are not supposed to write a code like that maybe you have forgotten something. So synthesis tool is not going to generate a circuit which is sensitive only to A it is going to report many a time saying that something is missing in the sensitivity list that is what it is going to do. So that is what happens either it ignores and try to generate a circuit using this kind of behaviour or it just ignore and you know or warn saying that something is missing in the sensitivity list. So it means that you know it essentially means that you cannot use VHDL to invent new kind of circuit you know you cannot do that you know you just play with the syntax of the VHDL and you are thinking that you are inventing some kind of new circuit that is not going to happen that is kind of trying to discover some new LAN looking at the Google map or the globe or the maps and things like that. What is in the map is already kind of discovered it is already marked so you cannot discover something new with some kind of quirks of the VHDL syntax that should be kept in the mind. Many people do that many a times some kind of they kind of write something and they claim that kind of new kind of circuit is invented that is not possible so keep that in mind. So this is a kind of an error which you need to correct this is not a new circuit but this is an error and there is an incompatibility between synthesis and simulation model. So let us move forward now so the question is that do not get kind of bogged by this kind of keywords it is very simple suppose you have a block where the input is ABC it can be a single bit or a kind of multi array of bits and you have two outputs Y and Z and you want to use process to write this block it is very simple you write process and within the sensitivity list write the inputs A, B and C and say begin using if or case or for or mixer of these you write the behaviour of this circuit and assign the output then you implement this circuit. So do not worry too much about the terminology like process and behavioural and things like that it is nothing you have a block you have some inputs write the input in the sensitivity list use if case for loops and all to describe the behaviour and assign the output from the input and we will see how to do that it is not that we are going to have a detailed look at this construct like when else which select if case and all that how to write combinational circuit how to write sequential circuit using this construct we will see that ok. But now for the time being you take it that you have a block you have some input output you write a process with sensitivity list with inputs in the sensitivity list describe the behaviour using the higher level construct sequential construct then you are implementing it one point though I said so like let us turn to the slide there is little more detail when I say you just write the input in the sensitivity list it is not completely correct something is missing here but we will handle that as we go ahead in the lecture we will see that as we go along because now mentioning that will not bring clarity so as we go along we need to add something more we will see that what need to be added what kind of things need is missing here we will see that but little more detail is required. But this is kind of bringing clarity to the whole scenario because when you read a text book which say behavioural model process if and most students kind of worry what is this all this about process sensitivity list sequential execution. So when you say sequential execution we mean the simulator not the synthesis tool so you have to make a distinction between simulator and synthesis tool. So let us move to the second part of it so which now when you say you have two blocks like this say you have a one block where it takes the input like A, B and C and produce output like U and V and another block which takes the same A and D and D and it produces output like Y and Z. Now you can write a process for this like I am trying to show this process ok EQ process may be one because I have used the same label twice which is not correct. So this has to be corrected may be there is a one here there is a two here. So I write process A, B, C I am trying to write the code for this and I write some if then to assign U and V we will see that later. And I write a second process EQ proc 2 process which sensitivity list A, D and E and I write the code for Y and Z. Now you should know that if an event happens on A both process has to be computed ok that means like we have written we have seen the concurrency of the two statements earlier I have shown that we have written say we have written an expression for X, Y and Z and we said that all are concurrent like when something happens everything has to be executed. Similarly two processes are concurrent if A changes both has to be computed in the same simulation time and the result has to be brought in here. So when as many like you have some three concurrent statement as five processes something happens everything is concurrent like you have the same signals appear in the statement as well as in the sensitivity list of the processes when the simulator handles the simulation everything need to be computed at the same simulation time. Something changes if not like sequential language whole computation has to be done. So that is how the concurrency is handled by the simulator but for synthesis tool if you look at the like the two processes which is you know kind of simulating like for synthesis tool it does not matter it comes look at the code written here and generate the equation or the circuit for U and V comes here look at the code for Y and Z and generate the kind of the circuit which is written for this block that is all for when you say concurrency it is mainly the simulator we mean or the concurrency. So with that I try to I mean I would like to wind up so today's class we have looked at the different models of description and we have seen data flow model using concurrent statement like when else and we have also seen the data flow model using kind of equations and we have seen the when else is much better than this kind of you know the equations then we have looked at the concurrency basically if you write 2, 3 statements the simulator has an issue if the order is not correct it has to resolve concurrency but synthesis tool does not matter it looks at the description and generate the circuit. Then we looked at the behavioral model there is a syntax called processes and we use a sensitivity list where the inputs are specified when something happens to the event happens on a signal on the sensitivity list the whatever written the behavior is computed from top to bottom once and for synthesis tool it does not matter you know it described it looks at the description and if something is missing then the sensitivity list simulator shows some behavior and synthesis tool shows another behavior you are expected to write all the input signal which comes in the expression which comes on the right hand side of the assignment in the sensitivity list and we have seen how to use processes you write the at least you write the input signals in sensitivity list write the behavior using higher level constructs and little more detail is there we will handle it and multiple processes are concurrent with each other with multiple concurrent statements. So that is about concurrency as far as simulator is concerned synthesis tool look at the code and try to generate the circuit for the block so with that I wind up the lecture today and in the next class we will see the remaining the model which is called structural model which is important in describing the hierarchy and we will see how the simulator handle this concurrency basically in the next class so please revise today's portion try to understand various concepts refer to some textbook and so I end the lecture here thank you and wishing you all the best.