 Hello and welcome to this presentation of the STM32L5 Reset and Clock Controller or RCC. The STM32L5 Reset and Clock Controller manages system and peripheral clocks. STM32L5 microcontrollers embed four internal oscillators, two oscillators for an external crystal or resonator, and three-phase locked loops or PLL. Many peripherals have their own clock, independent of the system clock. The RCC also manages the various resets present in the device. The STM32L5 RCC provides high flexibility in the choice of clock sources, which allows the system designer to meet both power consumption and accuracy requirements. The numerous independent peripheral clocks allow a designer to adjust the system power consumption without impacting the communication bot rates and also to keep some peripherals active in low power modes. Finally, the RCC provides safe and flexible reset management. Safe and flexible reset management without any need for external components reduces application costs. The RCC manages three types of resets, the system reset, the power reset, and the backup domain reset. The peripherals have individual reset control bits. The first type of reset is the system reset, which resets all the registers except the reset flags in the RCC CSR register. It also does not reset the backup domain. The system reset sources are the external reset generated by a low level on the NRST pin, a window watchdog event, an independent watchdog event, a software event through the nested vectored interrupt controller, a low power mode security reset, which is generated when stop, standby, or shutdown mode is entered, but is prohibited by the option byte configuration, an option byte loader reset, and a brownout reset. The reset source flag can be found in the RCC control and status register. Here is the simplified block diagram of the system reset. All internal reset sources provide a reset signal on the NRST pin, which can be used to reset other components of the application board. In addition, no external reset circuitry is needed due to the internal glitch filter and the safe power monitoring feature, which guarantees the reset of the application when VDD is below the selected threshold. The internal pull-up on the NRST pin, which maintains a high level when no reset signal is driven low, is deactivated when an internal reset is driven in order to reduce power consumption under reset. Additionally, all IO pins are placed in analog mode during and after reset to eliminate power consumption through the Schmidt trigger when the IOs are floating under reset and before software initialization. The second type of reset is the power reset, the brownout reset, or BOR. It resets all registers except those in the backup domain powered by VBAT, which contains the RTC and the external low-speed oscillator. When exiting standby mode, all registers powered by the regulator are reset. When exiting shutdown mode, a brownout reset is generated. The third type of reset is the backup domain reset, which resets the RTC registers, the backup registers, the SRAM2, the LSE oscillator, and the RCC backup domain control register. This reset occurs when the BDRST bit is set in the RCC backup domain control register. It also occurs when VDD and VBAT are powered on if both supplies have previously been powered off. The RCC offers a large choice of clock sources, which can be selected depending on the low power, accuracy, and performance requirements. STM32L5 microcontrollers embed four internal clock sources, a high-speed internal 16 MHz RC oscillator, or HSI16, a high-speed internal 48 MHz oscillator, or HSI48, a multi-speed internal oscillator, or MSI, and a low-speed internal 32 kHz RC oscillator, or LSI. STM32L5 devices embed two oscillators for use with an external crystal or resonator, a high-speed external 4 to 48 MHz oscillator, or HSE, with a clock security system, and a low-speed external 32.768 kHz oscillator, or LSE, also with a clock security system. When enabled, the clock security system can detect failures on external clock sources and automatically switch to an internal oscillator, HSI16, or MSI, in case of HSE failure, and LSI, in case of LSE failure. If a failure is detected on the HSE clock, a clock failure event is sent to the break input of the advanced control timers, and a non-maskable interrupt is generated to inform the software about the failure. The PLLs present in the STM32L5 have three independent outputs in order to offer different frequency options to the CPU and peripherals. The system clock can be derived from the high-speed internal 16 MHz RC oscillator, or HSI16. From the high-speed external 4 to 48 MHz oscillator, or HSE. From the multiple-speed oscillator, or MSI. Or from the PLL CLK output of the PLL. The AHB clock, called HCLK, is derived by dividing the system clock by a programmable prescalar. The APB clocks, called PCLK1 and PCLK2, are generated by dividing the AHB clock by programmable prescalars. The RTC clock is generated by the low-speed external 32.768 kHz oscillator, or LSE, the low-speed internal 32 kHz RC oscillator, or LSI, or the HSE divided by 32. This selection cannot be modified without resetting the backup domain. The LSE can remain enabled in all power modes and in VBAT mode. The LSI can remain enabled in all modes except shutdown and VBAT modes. Note that the P, Q and R dividers present in the PLL are outside the closed loop, and therefore they can be changed without unlocking the PLL. The two additional PLLs, called PLLSAI1 and PLLSAI2, have the same input stage. The input clock is either HSI16, or MSI, or HSE. They can be used to multiply the frequency of these reference clocks. The PLL input frequency must be between 4 and 16 MHz. The value of the divider located after the clock multiplexer has to be chosen accordingly. The three outputs of PLLSAI1 are available as root clocks for SAI, USB and ADCs. PLLSAI2 has a unique output called PLLSAI2-CLK that can be used as a root clock for SAI. The high-speed internal oscillator is a 16 MHz RC oscillator, which provides 1% accuracy and fast wake-up times. The HSI16 is trimmed during production testing and can also be user-trimmed. The HSI16 can be selected as the clock at wake-up from stop 0, stop 1 or stop 2 modes, and as a backup clock if an HSE failure is detected by the clock security system. The HSI16 can be automatically awoken when exiting stop mode in order to make it available for peripherals when it is not used as the system clock. The HSI16 is requested by the I2C, the UART, USART and LPUART peripherals to support wake-up from stop 0, stop 1 or stop 2 modes. HSI16 is enabled only for the wake-up sequence detection and remains disabled outside of this wake-up sequence. The HSI48 is generated from an internal 48 MHz RC oscillator. 48 MHz is a conical frequency for a USB module. HSI48 can also be used as the reference clock for the RNG and SDMMC modules. The HSI48 is associated with a special clock recovery system or CRS circuitry that dynamically adjusts the frequency according to the receipt of USB's starter frame packet or the LSE or an external signal. The MSI is generated from an internal oscillator. Its frequency is programmable from 100 kHz to 48 MHz. This is the default clock source after a reset and wake-up from standby and shutdown low power modes. The MSI can be selected as the clock at wake-up from stop 0, stop 1 or stop 2 modes and as a backup clock if an HSE failure is detected by the clock security system. In addition, when used in PLL mode with the LSE, it provides a very accurate clock source, better than plus or minus 0.25% accuracy that can be used by the USB, FS device and feed the main PLL to run the system at the maximum speed 110 MHz. The low-speed internal or LSI oscillator is the unique clock of the independent watchdog and can be the clock of the RTC. It can be kept running in all stop and standby modes. Accuracy of the frequency is plus or minus 5%. The clock frequency is either 32 kHz or 250 Hz. When using the independent watchdog, 32 kHz operation is selected and forced on. The high-speed external oscillator provides a safe crystal system clock. The HSE supports a 4 to 48 MHz external crystal or ceramic resonator and also an external source in bypass mode. A clock security system allows an automatic detection of an HSE failure. In this case, a non-maskable interrupt is generated and a break input can be sent to timers in order to put critical applications such as motor control in a safe state. When HSE failure is detected, the system clock is automatically switched to an internal oscillator, either HSI-16 or MSI, so the application software does not stop in case of a crystal failure. The 32.768 kHz low-speed external oscillator can be used with an external quartz or resonator or with an external clock source in bypass mode. It has the advantage of providing a low power but highly accurate clock source to the real-time clock peripheral or RTC for clock and calendar or other timing functions. The oscillator driving capability is programmable. Four modes are available, from ultra low power mode with a consumption of only 250 nanoamps to high driving mode. A clock security system monitors for failure of the LSE oscillator. In case of failure, the application can switch the RTC clock to the LSI. The CSS is functional in all modes except shutdown and VBAT. The CSS on LSE failure is detected by a tamper event. It is also functional under reset. The LSE can be used to clock the RTC, the USARTS, low power UART peripherals, and the low power timer. The system clock is selected between the MSI, HSI 16, HSE, and PLL output. MSI is chosen by default. The maximum system clock frequency is 110 MHz. The APB1 and APB2 bus frequencies are also up to 110 MHz. The voltage scaling range is adjusted to HCLK frequency as follows. The system clock is limited to 110 MHz in range 0 mode, 80 MHz in range 1 mode, 26 MHz in range 2 mode. In STM32L5 devices, it is recommended to use a transition state when switching from low to high speed or from high to low speed system clock. This slide presents the recommended sequence for the transition state. To increase the frequency, the AHB clock frequency has to be divided by 2 prior to switching the system clock to PLL. After a 1-microsecond delay, the pre-scaler providing the HSB clock can be set to the targeted frequency. This is needed when switching from HSE or HSI or MSI to PLL and the system frequency becomes higher than 80 MHz. The AHB pre-scaler divides the system clock to obtain the AHB clock or HCLK. APB clocks called PCLK1 and PCLK2 are obtained by applying a programmable pre-scaler ratio to HCLK. This slide also describes the multiplexers in charge of selecting the clock of various peripherals. The various clocks can be output on an IOPAD. The microcontroller clock output feature enables the external output of one of these seven clocks. MSI, HSI-16, HSI-48, HSE, LSI, LSE, CIS-CLK, and PLL-CLK. The low-speed clock output feature enables the external output of the LSI or LSE clock. The low-speed clock output is available in stop zero, stop one, stop two, and standby modes. It is possible to indirectly measure the frequency of all on-board clock sources by means of the TIM-15, TIM-16, or TIM-17 channel, one input capture. These measurements can be used to calibrate the LSI, MSI, and HSI-16 frequencies. Concerning HSI-16 and MSI, RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. This is why each device is calibrated at the ST factory for 1% accuracy at an ambient temperature of 25 degrees Celsius. After reset, the HSI-16 and MSI factory calibration value is automatically loaded. If the application is subject to voltage or temperature variations, software can perform clock trimming. The dynamic power consumption can be optimized by using peripheral clock gating. Each peripheral clock can be gated on or off in run and low power run mode. By default, the peripherals clock is disabled, except the flash memory clock which is enabled. When a peripherals clock is disabled, the peripherals registers cannot be read or written. Other registers allow the configuration of the peripherals clock during the sleep and low power sleep modes. This also affects stop 0, stop 1, and stop 2 modes for peripherals with an independent clock active in stop modes. These control bits have no effect if the corresponding peripheral clock-enabled bit is cleared. By default, the SRAM 1, SRAM 2, and CCM SRAM clocks are enabled in sleep and low power sleep modes. If they are not needed, the SRAM clock-enabled bits should be disabled to reduce power consumption. Some control and status register bit fields support two levels of protection, security and privilege. The RCC register bit fields that can be protected against non-secure accesses are the following ones. Six system clocks, HSI, HSE plus CSS, MSI, LSI, LSE plus CSS, RC48, four system configurations, PLL-SIS, PLL-SAI1, PLL-SAI2, pre-scalers AHB, APB1 or APB2, two system multiplexer setting, SIS-CLK plus MCO, SCL48, one reset flag, RMVF. Security violations are reported to the Global Trust Zone Controller or GTZC. A maskable interrupt can also be generated. When a peripheral is configured as secure in the TZSC, the bit fields related to the peripheral in the RCC inherit the secure attribute. In order to explain the access permissions, let us focus on the remove-reset flag bit called RMVF, present in the RCCC SR register. By setting this bit to 1, all reset status flags are cleared. The table on the right indicates the access permissions of this particular control bit according to the RMVF-SEC attribute and the RCC privilege attribute. This slide lists the RCC interrupts. The LSE and HSE clock security systems can generate an interrupt request. RCC-IT typically reports PLL-REDI and oscillator-ready events. In addition to this training, you may find the power control interrupt controller and Global Trust Zone controller training is useful. For more details, please refer to the application note AN2867, an oscillator design guide for STM8S, STM8A and STM32 microcontrollers.