 And in this lecture, I shall discuss various topics such as, what do you mean by an instruction, then what do you mean by an instruction set architecture, classification of instruction architectures, and as part of the instruction set architecture, you will find there are you have to perform various operations. So, there are classification of operations, then classification of operands, instruction format, addressing modes, then evolution of the instruction set, then there are two basic classes of instruction set architecture, RISC versus CISC, I shall discuss and finally, I shall discuss about the MIPS instruction set architecture. So, let me start with by an instruction, what do you really mean by an instruction, you know whenever you want to talk to somebody, you have to know the language of that person. So, whenever you are writing a program, you are essentially communicating with a processor and you have to talk the language the processor understands, the language the processor understands is essentially represented by instruction set architecture. So, an instruction can be considered as an word, instruction is equivalent to an word in conventional you know language, then instruction set architecture can be considered as the vocabulary what the processor understands, so we can say that an instruction can be considered as a word in processor's language and question naturally arises, what information and instruction should convey to the CPU, as we know in our traditional language, a word conveys some meaning, so similarly an instruction should convey something to the processor, what it should convey, let us try to understand first. First of all an instruction can be represented by an instruction format and different components of the instruction can be represented by different fields, first thing that an instruction should convey to the processor is the off code, the operation to be performed by the processor, you know the task of a processor is to execute instructions one after the other, obviously the instruction should tell what operation to be performed and later on we shall see the various types of operations that can be performed by a processor like arithmetic operations, logical operations and like that. Then apart from the off code, the other fields of the instruction are number one is address of operand one, you know whenever you have to perform some operation, say let us assume you have to perform c is equal to a plus b, question is where from you will get a that is the address of operand one, then comes the question of where from you will get b, so address of operand two, third is you have to store this result somewhere c value of c, so that is known as destination address finally, so these are the four things and instructions should convey to the processor finally, this instruction execution is over, what the processor should do now, processor has to fetch the next instruction, where from it will get, so that information should also be present here, so ADDR address of the next instruction, so these are the different fields of an instruction, if everything is conveyed explicitly, now that means what I am trying to tell, you see if all the information like source address of operand one, source address of operand two, destination address of the next instruction, if everything is explicitly specified as part of the instruction, then instruction will be too long for example, say suppose this off code requires one byte, an address may require two to four byte, let us assume it requires two byte for simplicity, two byte, two byte and two byte, so you can see even in this very simple format, it requires nine bytes per instruction, now so if nine bytes is required for a single instruction and as you know a program consists of a large number of instructions written one after the other, so a program will require very large memory size, because each instruction is requiring five bytes, if all the fields are specified explicitly and then they have to be stored in the memory and as you know from the memory have to transfer it to the processor, whenever the execution takes place, so not only the program will occupy very large memory, because each instruction is long to fetch them from the memory to the CPU, it will take long time, because if the word size is 16 bit, you can fetch only two bytes at a time, so you will require, I mean for nine bytes you will require at least five cycles, five machine cycles to fetch it, so each instruction fetching will require long time, in other words execution time will be long, so storage requirement is long, processing time is long, if all the fields are specified explicitly, in that case what is the alternative, alternative is to specify implicitly rather than explicitly, how can it be done, for example you can use a special register known as program counter PC program counter and it is implied that address of the next instruction is always present in the program counter, when the processor is initialized, I mean whenever you put reset button, then the program counter will be loaded by the address of the next instruction to be executed and then as one instruction is fetched and it is executed, it will automatically load the address of the next instruction in the program counter, so program counter is considered to be the source of the next instruction, so you do not require this field, this field is no longer required in the instruction, if PC is providing the address of the next instruction, so it is implied that program counter will provide the address of the next instruction, so this field is not required, now let us consider another possibility, say you are using three memory locations to store the source of the operands and the destination address, what you can say that address of operand 1 will be the destination address, you make the assumption that address of the operand 1 will be the destination address, where the result will be stored, so in such a case there is no need for this field, destination address field is not required, now the question of these two fields address of operand 1 and address of operand 2, can you get rid of them, yes you can get rid of them in this way, you assume that one of the operands will be always available from a resistor known as accumulator ACC accumulator, so accumulator will hold one of the two operands always, that means you have to load the load one of the two operands in the accumulator before you execute an instruction, so whenever you make that assumption may be this particular address of operand 1 is not required, however you will require another field address of operand 2 will be required as part of the instruction, can you get rid of this, you cannot really get rid of this fully, but what you can do instead of specifying the full address, you can specify the address in various ways, for example what you can do, you can use a resistor as the address of the operand 2, in such a case may be the opcode can be little bigger, say some part of the opcode can be used to specify the resistor, which will be the address of the operand 2, in such a case again you will be able to overcome this I mean this field need not be present in instruction, so you find that ultimately you have been able to have an instruction with only one field, which specifies the opcode and remaining things can be implicitly specified available from some special purpose resistors, processor knows where from they will get it and also what if you use resistors then the size will be small, the reason for that is size of the memory is pretty long may be 64 kilobytes minimum few megabytes or now a days few gigabytes, so you will require 16 bit address or 32 bit address as it happens in present day computers, so instead of 32 bit if the number of resistors available is may be say 16, only 4 bits is required, so 4 bits can be provided as part of the opcode field, so in such a case you will require a very small instruction size and this is how the instruction size can be reduced, so and based on this discussion we shall see you know different techniques have evolved addressing modes and other things, so the instruction is too long if everything is specified explicitly, so it requires more space in memory, it requires longer execution time, question is how can you reduce the size of the instruction specifying information implicitly as I have already told by using program counter, by using accumulator, by using general purpose resistors and stack pointer I shall discuss about it little later to implement some special data structures, so this is the basic idea about an instruction. Now coming to instruction set architecture, what it really means an instruction set architecture is a structure of a computer that a machine language programmer must understand to write a correct program for that machine, so instruction set architecture is equivalent to vocabulary of the processor, which the programmer must know and with the help of which he can write program in assembly language or machine language. So what the instruction architecture defines, it defines the operations that the processor can execute, various data transfer mechanisms and how to access data either from memory or from registers, then various control mechanisms like branch, jump and so on, so it is essentially a contract between the programmer and compiler and the hardware, so you have got hardware and software and instruction set architecture is essentially a contract between the hardware and software. And knowledge of instruction set architecture is important not only from the programmer's perspective, that means if the programmer does not know the instruction set architecture he cannot write program in machine language and not only that is important, it is also important from another perspective, from processor design and implementation perspective as well. That means not only a programmer should know an instruction set architecture, but the designer of the processor should also know it, because it is essentially the specification, it serves at the specification to the designer, because what the processor has to do has to implement those instructions, so that these instructions can be executed by that processor. So, the instruction set architecture essentially serves as specification to the designer of the processor. Now, let us focus on the programmer visible part of a processor, number one is registers, that means with the help of these registers you can, I mean the registers are available where data are located, you can store data, you can access data with the help of instructions, then the instruction set architecture also provides the various addressing modes with the help of which data can be accessed either from registers or from memory, then instruction format. You will see that I have already mentioned about the instruction format, you may call it as instruction format, the various fields of an instruction, where with the help of which you can specify various things, then it should also know exceptional conditions, what do you mean by exceptional conditions? Exceptions can occur in two ways, exceptions can be generated from the outside world, for example, interrupt, it can be generated by an IO or it can be generated by an user, so reset, interrupt inputs are the external interrupts or exceptions coming from outside of the processor. In addition to that, some exceptions are generated from within the processor, so whenever an instruction is executed, there may be something wrong, how that code that is being executed may not be an off code, may be an invalid code because of wrong alignment of the memory that can happen or while performing an execution of an instruction, there are some situations like divide by 0. So those situations are known as exceptions generated within the processor, whenever an instruction is executed by the processor. So whenever that happens, what happens if something goes wrong? That also has to be specified, I mean should be known to the programmer, whenever these exceptions happen, for example, if interrupt occurs, it knows that there is an interrupt service subroutine, there is a specific address to which it will jump, then all these together represents the instruction set, what operations can be performed. So these are the different parts, programmer visible parts provided by the instruction set architecture. Now, there are various instruction set architecture design choices, for example, types of operations supported, the processor has to do some data processing, what kind of data the processor can process. So this can be like arithmetic or logical data transfer, control transfer, system calls, floating point operations, addition, multiplication, division, decimal addition, subtraction, decimal operations, string operations, bit manipulation operations. So these are the various types of operations which can be supported. If it is not necessary, a processor should support everything, depending on the application, a design one can decide that this is the subset of the operations, the instruction set architecture will provide and accordingly the processor has to be implemented. So it depends on the application for which a processor is designed. Then comes the types of operands supported. So types of operands means whether it is byte operand, the operations can be performed on bytes or it can be performed on 16 bits or it can be performed on 32 bits. So it can be byte, character, digit, half word, word, double word and also floating point number. You can see the operand sizes can vary and their format can also vary. So some can be fixed point operands and some can be floating point numbers. Then types of operand storage allowed, again where the operands will be stored, obviously either in registers or in memory, these are the two alternatives available. So there can be various types of storage facility like stack, accumulator, then registers, registers can be of two types, special purpose registers and general purpose registers. Then memory, by memory we really mean the main memory where form the processor accesses various operands and also instructions. Then as I have already told there is a possibility of specifying either explicitly or implicitly. So implicit versus explicit operands in instructions and numbers of each. I have already explained this particular feature, how instead of specifying everything explicitly you can specify some of the things in an implicit manner. Then orthogonality of operands, that means whether each operation will support all different types of addressing modes like that. So that defines the orthogonality of operands, then operand location and addressing modes. So these are the various design choices of instruction set architecture. Now let us have some kind of classification of instruction set architecture. So it is actually determined by the means used for storing data in CPU. So I have already told you can store registers or memory for storing operands and depending on that the instruction set architecture can be classified broadly into three types like stack architecture, accumulator based architecture and register based architecture. So there are three possible alternatives. In case of a stack architecture operands are implicitly on top of the stack. So everything you are doing with the help of a stack and you can access from the top of the stack. So as you know stack is a data structure, last in first out type of data structure. So you can access always from the top of the stack. And then it can be accumulator based architecture. So as I have already told one operand is in the accumulator which is a special purpose register and others are elsewhere. By elsewhere I mean it can be either in some register or it can be in some memory location and essentially this is a one register machine. That means whenever it is accumulator based machine it implies that the processor has got only one register, that is why it is called one register based machine. And this is particularly available in older machines, you know in early years the implementation of registers was very costly, hardware was costly. So only one register was allowed to be provided as part of the processor and that is how the accumulator based processors were popular in the earlier subcomputers, but subsequently as we shall discuss that restriction was overcome. Then comes the general purpose registers where operands are in registers or specific memory locations. So it is a general purpose, you have a set of registers may be 16 or 32 registers, they are general purpose in nature. So you can access operands from the registers or it can be also from specific memory locations. So you can see how the instruction set architecture has evolved over the years. As I said in the early years it was all accumulator based architecture like EDSAC, IBM 701, these were single accumulator based or IBM 700 series back in 1953, these were all accumulator based architecture. That means you have only one accumulator and one operand is always available taken from the accumulator and result is also stored in the accumulator, however the second operand can be taken from memory. Then came special purpose registers architectures, I have already mentioned about the special purpose registers like program counter, stack pointer and there are some more special purpose registers provided from where you can access operands. Then came the era of general purpose registers architecture, so where it can be register memory type that means one operand is taken from the register, second operand is from the memory. So these are known as register memory architecture for example, processors like IBM 360, DECP 11, Intel 80386, these are all belong to this class and they are essentially one operand is taken from the register, another operand is taken from the memory and they belong to the category of CISC architecture, complex instruction set architecture. So then came subsequently the RISC architecture where it is register architecture that means both the operands are taken from registers and result is also stored in the register that means whenever you are performing various operations arithmetic and logical operations the always the operands are taken from register result is also stored in the register. So these are known as register architecture and these are also known as load store architecture because you have to perform loading of the registers from the memory with the help of explicit instructions and store the result from the register to the memory with the help of store instructions. So these are also known as load store architecture and the RISC processors belong to this category and they are also known as load store architecture like CDC 6600 MIPS processor, DEC alpha, these are all register architecture processors. So you see it started with simple and then gradually it has become complex. As I have already told you can do the classification in three ways, three ways stack based where the operands are taken from the top of the stack, top to elements in stack and destination is also top of the stack everything is done with the help of the stack in accumulator based processors I have already told one of the operands is from the accumulator another operand is from the memory and result is stored in the accumulator. And in case of register memory or register processors it can be register or memory and destination also can be register or memory that means source of operand and destination both can be register or memory. For example, let me illustrate these three architectures with the help of this very simple operation, consider you have to perform this simple processing c is equal to a plus b. In case of stack machine these will be the four instructions push a, push b add and pop c. So, this is how the operands will be taken and the processing will be performed. Then in case of accumulator based machines first you have to load the accumulator from the memory then you will be adding that one operand is taken from the accumulator and second operand is from the memory and you are performing the operation then storing the result in the accumulator then result can be stored in memory location c. So, this is accumulator memory type of processor architecture and then register memory. In case of register memory as you can see you have got the register r1 which is a general purpose register where you are loading one of the operands then you are performing the operation I am adding the content of register r1 with the content of memory location b and then you are storing the result here the result is available in register r1 and result is stored in memory location c in the third instruction. And in case of register architecture you are always doing with the help of register. So, accumulator is loaded I mean register r1 is loaded with the first operand then you are loading the second operand in register r2. So, this is essentially that load store architecture and then you are performing the addition operation result is stored in another register r3 by adding the content of r1 with content of r2 then you can store the result with the help of a store instruction in memory location c. So, you can see this is the register architecture or load store architecture. So, we have compared 4 different architectures that is possible. Now let us come to the classification of operations. The operations can be classified into 4 different categories as you can see data transfer. Data transfer means data transfer is taking place from register to memory or memory to register. So we can say data transfer, so you have got some registers and memory, so this is your storage space. So, you will be either transferring from register to memory, so it can be called store or you will be transferring from memory to register load or from one register to another register, so this is your normally known as move. So, these are the 3 possible data transfers that can take place between the register and memory or within the registers and then comes the data manipulation operations. So data manipulation operations can be broadly divided into arithmetic operations or logical operations. Arithmetic operations are like add, subtract, multiply, divide, so again you have got different possibilities sign or unsigned integer or floating point, so you can have unsigned addition or signed addition or multiply, unsigned multiply or integer multiply or floating point arithmetic operations, so you have got several alternatives. Similarly, you have got logical like conjunction, disjunction, shift left, shift right and or like that. So these are the various data manipulation operations where you are performing manipulation of the data, the value of data is changing. Then there are some instructions which are known as status manipulation. What do you mean by status manipulation? In case of status manipulation instructions, neither you are transferring data, no transfer of data takes place, no manipulation of data takes place. That means, neither the data is moved from register to memory or memory to register or you are changing the value. What happens? The status of the processing changes, there are some instructions like that. For example, set carry, there is a carry flag bit as you know, so set carry flag bit here the status of the processor changes or say enable interrupt or disable interrupt. So these are some of the status manipulation instructions with the help of which the status of the computation can be changed, but neither data transfer nor data manipulation takes place. Then comes the control transfer instructions which can be conditional branch like branch on equal, branch on not equal, set on less than or unconditional jump. So there can be various types of control transfer instructions, operations which can be performed. So these are the different classifications of operations that is provided by the instruction set architecture. Now comes the instruction format, whenever we are considering instruction format, it is very important that the length of the instruction should be multiple of bytes. Why it is necessary to be of multiple of bytes? Because you will be storing instructions in memory and the accessible unit from the memory is byte. That is why we call it byte addressable memory. So your instruction has to be either 8 bit, 1 byte or it can be 16 bit for 16, normally it is 8 bit for 8 bit processor, 16 bit for 16 bit processor that means 1 byte or 16 bit 2 bytes or it can be 32 bit 4 bytes. So there are it has to be multiple of bytes, so that you can access it from this point and read it or from this point or from this point and you can get a complete instruction and that is why I was telling that alignment is important. If it is read from the middle, for example, whenever the instruction is 16 bit and if you read it from here, you will not really get the instruction properly. So whenever you try to execute it, it will give error or exception. Now instruction encoding can be variable or fixed, there can be a fixed format. In other words, what I am trying to tell an instruction can be of fixed size, say 32 bit. All instructions are of 32 bit, so that is one possibility. Another possibility is that it can be multiple of some bytes, say one can be of 16 bit, one instruction format, another can be 32 bit and third one can be 48 bit or 48 bit. That means in these three cases, in this particular case that instructions can be of 1 byte size, 2 byte size or 3 byte size. So we call it variable format. So instruction we call it variable format. So you can either have variable format or fixed format, particularly later on we shall see the SISC processors have variable format. On the other hand, the RISC processors have fixed format, in general that is true. So variable format leads to variable encoding tries to use as few bits as represent a program as possible, but at the cost of complexity of decoding. So that means here the complexity of decoding is present whenever you use variable format. And later on we shall discuss about MIPS instructions, you will see that all decalpha or MIPS instructions, they have fixed instruction size because they belong to the RISC category RISC processors. And this is the general instruction format for RISC processors, off code then 3 addresses address 1, address 2, address 3 they can be usually they represent the registers, but I shall discuss about various formats with the help of an example, particularly the MIPS instructions. Now, addressing modes describe how an instruction can find the location of the operands. So you can have a variety of addressing modes to facilitate accessing of operands from registers as well as from memory. And you will see that either from registers that means you have to do calculation of the address from where you will get the operand and that is called the effective address. So effective address is calculated whenever your operands are in memory what you can do that effective address calculation may involve reading some value from register and some part of the instruction that can be used to compute the effective address. Later on I shall discuss about the how effective address is calculated in various situations or in different addressing modes. So effective address is essentially the actual memory address specified by an addressing mode. The mechanism by which the effective address is calculated varies from one addressing mode to the another addressing mode. Here I shall discuss about the various addressing modes for example, inherent addressing zero address. So here for example, you have nothing but the off code. So rest of the things are implicit obviously one of the operands is in the accumulator. So it can involve an accumulator based instruction. In such a case say it can be say increment of the content of the accumulator or compliment the content of the accumulator. In such a case it involves only one operand. So if it is in the accumulator that is incremented or inverted and result will be also in the accumulator. So there is no need to have any other operand address. So that is why this is known as inherent or zero address addressing modes only the off code needs to be explicitly specified rest of the information are implicit. Then in immediate addressing the operand itself is provided as part of the instruction. That means you have got off code the first operand may be in the accumulator second operand is provided as part of the instruction explicitly. That means you will add the content of the accumulator I mean if it is a add operation with the operand which is provided as part of the instruction. So this is the second addressing mode third addressing mode is known as absolute or direct addressing mode. In such a case as you can see the address of the operand particularly address of the second operand first operand is assumed to be in the accumulator address of the second operand is available from the memory and that address is explicitly specified and as part of the instruction. So that is why it is called absolute addressing or direct addressing. Then you can have to incorporate little bit of flexibility you can have indirect addressing in indirect addressing instead of specifying the address from the memory you the sorry instead of specifying the address explicitly what you can do that address can have the address of the operand instead of the operand. As you can see here in this case this is the address but this the address does not contain the operand the address contains the address of the operand. So you have got a kind of indirection. So this address is pointing to another memory equation which is the address of the operand. So that A2 is the address of the operand and so again you have to read it from the memory location A2 to get the operand. So this is known as indirect addressing essentially to provide little bit of flexibility in addressing. Then you can have register addressing as I have already told some parts of the opcode a small portion of the opcode I mean that instruction the opcode is little smaller here you can provide the register name register number and which will provide the operand. So here is your register set of registers or register bank whatever you call it and this is pointing to the operand operand where the I mean through the register where the operand is stored. Then you can have register indirect so just like your indirect addressing here also that register is not having the operand but is having the address of the operand. So you can sometimes we use the concept of register pair because a single register may not be able to hold the entire address for example your register is of 16 bit but address is of 32 bit. So you will require a pair of register to provide the full address. So in such a case we use the concept of register pair so as you can see here a register pair is holding the address and that address can be used to fetch the operand. So that means effective address here is coming from the registers so this is how in different situations the effective address is generated as you can see. Then comes the paged addressing sometimes we use the concept of paging and particularly to reduce the size of the instruction we use different pages or you can use a paged register. So in such a case an offset is provided and then the direct paged register is used these two together provides the full address where the operand is available. So this is known as paged addressing that is done with the help of a special purpose registers which is available in the as part of the processor. Then indexed addressing is used to facilitate implementation of data structures like Q and as you can see we use a special purpose register X. So this register gives you the offset value and another register base address is provided as part of the instruction these two together is used to generate the address and you get the operand here. This is very useful for accessing array elements. So the base address is the starting address of the array and then indexed register will point to different elements of the array. So base address is fixed and then you can change the indexed register value to point to different array elements. If it is 0 it points to the 0th element, if it is 1 it points to the first element like that. Then this way you can access an array very conveniently by indexed addressing as I said that this is useful in implementing some data structures like array Q and so on. Then comes the best addressing where a special purpose register known as best register is used and a constant is added to that to point to the operand. So in this particular earlier what we have seen that register value are changing now this value will change I mean this base register is added with the constant to generate the operand address. This is particularly used in situations like relocation you know sometimes you have to do relocation in a multi user environment then you require best addressing you change the content of the best register to locate relocate the instructions to different parts of the memory. So and then you can combine best addressing with indexed addressing you can have a index register and a base register both of them can be used simultaneously to have best indexed addressing. Then you can have relative addressing, relative addressing is you are essentially providing an address with respect to some register particularly program counter with respect to program counter. So off code and a displacement is provided as part of the instruction which is added with the program counter to generate the effective address which is the address of the operand. So this is known as relative or whenever the program counter register is used then we call it PC relative. Then there are various I mean there are addressing modes related to stack. So you have got a stack pointer which is pointing to the bottom of the top of the stack and you know whenever you push some element it is decremented and value is stored. So you can perform push A so you can see it is pointing to the stack pointer is decremented to point to the next location and value of A is stored here. Then another push you can see it is again decremented and top of the stack is holding the value B similarly you can perform pop operation. So with the help of push and pop operation you can store or load operands from the in the memory. So whenever you do pop operation you can read it from this location then it will point to next location. So in this way you can see stack manipulation you can do with the help of these two instructions push and pop. So these are the various addressing modes but our discussion will not be complete without mentioning about SISC and risk controversy. I have already told that there are two possible architectures one is known as risk instruction set computer risk architecture another is complex instruction set computer or risk architecture and what is the genesis of SISC architecture. So implementing commonly used instructions in hardware can lead to significant performance benefits that means what you are trying to do you are trying to minimize the semantic gap with high level languages. That means whatever the high level language instructions can perform you are trying to do with the help of the machine language instructions by making the instructions more and more complex. As a result a single high level language instruction will lead to very few machine language instruction may be one or few. So the semantic gap between the high level language and machine language reduce that is the basic idea behind complex instruction set architecture. So what is happened as the various programming languages evolved and various operations which are provided statements can performed in high level languages those are implemented in complex instructions. So that is the genesis of SISC architecture for example use of a floating point processor can lead to performance improvement and there will be complex floating point operations which can be specified with the help of complex instructions. On the other hand in case of risk architecture the rarely used instructions can be eliminated to save chip space on chip cache and large number of registers can be provided. Here there is a story behind it particularly IBM did some study on various types of instructions which are used by the compilers you know you are writing a program in high level language then compiler is generating the machine language code. So which instructions are used by the compilers different compilers it was found that a lot of simulation works were carried out by IBM people and it was found that very complex instructions are rarely used rather the compilers used only simple instructions while generating the code object code. So what was decided the instructions which are rarely used by the compiler why to implement them. So they removed those complex instructions leading to what is known as risk processors where complex instructions were removed and only simple instructions which are commonly used by the compiler are retained and that is the genesis of risk architecture. Then of course these are the features of risk architecture, rich instruction set some simple some can be very complex, complex addressing modes then many instructions take multiple cycles as I have told they can be the instruction format can be complex I mean variable. And there can be a large variation of CPI some instructions may take one cycle some instructions may take two cycles some instructions may take ten cycles depending on the complexity of the instruction. Then instruction of variable sizes as I have told then small number of registers because it uses primarily it is a register memory architecture. So one operant is in the register other operant is from the memory that is why you require small number of registers and micro code control you know that the control unit is implemented with by micro programming micro program control unit instead of hardware control unit. You may have studied the two ways of implementing control unit one is hardware control unit another is micro program control unit normally the risk processors use micro program control unit and it is very difficult to implement pipelining in SISC processors. So obviously one instruction could do work of several instructions because it is quite complex and there may be many variations of SISC instructions because it involves memory and registers. On the other hand the risk processors have small number of instructions small number of addressing modes large number of registers. This is one very important features of risk processors they require very few large number of registers and instructions execute in one or two cycles clock cycles you will find later on when I shall discuss the MIPS processor architecture you will see all the instructions will require a single format and also will involve only one cycle or two cycles for its execution. Then uniform length instructions and fixed instruction format as I have already told and is essentially register architecture where you require separate load and store instructions that is why it is called load store architecture and separate instruction and data cache. This is a very important feature later on I shall discuss about it in more detail. We will require two separate cache memories one for instruction one for data instead of a single cache memory. Then the control unit has to be hardwired instead of micro program control unit it has to be hardwired control unit. So these are the features and finally I shall discuss in detail later on when we shall discuss about pipelining you will see the risk processors can be risk instructions can be very easily pipelined in contrast to SISC processors. So implementing pipeline architecture for SISC processor is very difficult which can be very easily done in case of risk processors. So with this let us come to the end of instruction set architecture in by next class I shall continue our discussion on risk and SISC and also consider a representative processor architecture that is the MIPS processor architecture in my next class. Thank you.