 Good morning everyone, sorry it's a bit of 4 to 5 minutes late, sorry, okay. So the topic is base porting of Linux kernel on RISC 5 architecture. So let me introduce myself, myself I am Satish Kumar, I have been working for KVM networks. We do work on the networking process developments actually. So I am doing this RISC 5 architecture, this is for my personal projects actually. Out of that I am trying to give a session today. So before we are getting into the RISC 5, let me give a basic introduction on the RISC 5. So this is a pretty new architecture, but anyway it's been already developed in the kind of organizations are already working on the RISC 5. But yeah it's a new architecture coming based completely to the ARM we can say that. And right now the people are working on the servers basically, servers in the desktops. So we didn't see the RISC 5 stocks into the mobility devices till now, but yes. Let's go into the further. So I will try to capture the set of slides where we can try to be, modify that or we can use that RISC 5 architecture for the mobilities also. So coming to the basics, so first thing is once we are talking about any new architecture because the first part is when we say that base porting, right? So base porting for a new architecture because there are two things. One is base porting for an existing platform and base porting for a new architecture. So that when we talk about a new architecture we have to start from the ISA, the instruction set architecture, what that actual RISC or whatever the ARM or X86 what it is talking about. So part of this index I am just trying to cover out RISC 5 ISA and the existing RISC 5 stock boards in the commercial market and the technology in the sci-fi boards. I mean like we have actually lot of stock boards in the market today, but the thing is I am taking the sci-fi one which is the only one high five unleashed board actually they called as H540. So that is the one board actually running on the Linux support. So we are taking that sci-fi board and we will see that the terminology in the sense when we are getting it to the new port, the new set of instructions, the terminals what they are going to use that we will discuss about. So that it will be easy that when we are talking about a trapping or talking about a memory paging the kind of instruction set they are using. So maybe we are familiar with ARM, maybe we are familiar with X86 or PowerPC. So when it is coming to the RISC 5 the instruction set names itself varies. So that we discuss on that part and then booting with respect to the sci-fi kernel. So with respect to booting they are talking about the new boot loader called BBL and then the early boot part and the setup architecture part and then SMP initialization in the sci-fi kernel and shutting down. Shutting down is one thing like actually these guys are using the SBI which is called an open SBI might be we guys aware of that a supervisory binary interface and how we are using the shutdown and then traps used in the sci-fi kernel and the other one is the timer interrupts and the paging. So when it is coming to the basic instruction set architecture we can see that there are 4 kinds of instruction that they are supporting that is 32 base integer instruction set and E supports the embedded and 64 I that is for the base integer and 128 is for the again integer instruction set. So if we are try to see this ISCA here we can see that there is X0 to X31 registers. So out of that X0 is always 0 and from X1 to X31 is a general purpose registers. So we can try to like if it is a pretty new might we can compare with it with the existing architecture maybe with respect to ARM. So there we can say that R0, R1, R2 to R14 right R15 and then CPSR and SPSR the kind of same like we can present here also let me get into that then we can see that instructions what we are using there right. So these are for the 32-bit integer but actually that sci-fi is a 64-bit supported right. So the commercial RISC 5 stock boards developed already available in the market is provided by the sci-fi guys and the Sainte-Court and its technology Green waves, X5 and Western digital Alibaba. So these are already available in the market but and there are some more boards also from the IIT Chennai safety processor and kind of things they are on development actually but these are already developed boards. So now for the next slide we are taking the one that sci-fi we are taking as an example out of this all these boards I am taking the sci-fi board. So part of this the terminology that what we are going to use maybe it is just a kind of adaptation with the new terminology. So the first thing is the CSR the control status register instructions they want to say that. So and whenever they say in the CPU ID earlier they called as a hot ID the hot ID is nothing but hardware thread ID which is running on a current CPU or you can say that it is a CPU ID hot ID is equivalent to CPU ID and the scratch register is a kind of trap hand less like you know regular way we can know that what kind of trap is kind of an exception where we are trying to save kind of registers before we are moving to the other instructions like ISR prologue and ISR epilogue right. So this prologue and epilogue in between we want to save those stack frames so that we have to use a kind of register so they are telling that that is a scratch register which I want to use for the trapping right and here we are you use the one word extra called supervisor. So actually that supervisor is a kind of a mode provided by the RISC-5 when we talk about the ARM we have seven modes and when we talk about the RISC-5 there are four modes actually. So part of that when I say scratch actually scratch is a supervisory trap handler if there is a M scratch that is a machine mode I will explain that later. So scratch is a part of a trap handler and SQL is make a request to the operating system environment and SQL is a supervisory cause register. So these are the combination of this scratch SQL and SQL is the combination for the trap handling actually and then M hot ID is the hardware thread ID which is part of machine mode and then M return from it is representing the return the trap from the machine mode actually and the page offset anyway this is a common technology that we use in all architectures page offset is a kernel technology Linux kernel technology and STVEC this is a supervisory trap vector base address register. So this is used and when we are using for the how to handle a trap or the exception how when we are writing this STVEC register instruction going to be used and then S return return from the traps in the S mode that is supervisory mode and Sfans.vma this is the kind of instruction that we use in a regular memory optimization sorry dmb dsb isb which are part of ARM right mb and rmb memory barriers kind of stuff that they are using the Sfans that S is represented in the supervisory but actually there is a command called fence which will be used for the memory supported operations which is equivalent to our dmb in the ARM architecture and LEN is a common register actually LEN 1, XELN 0 these are the new register instruction set part of RISC 5 and PMP PMP is the physical memory protection is a name it's a terminology proved by RISC 5 again so now how to boot it in with respect to the sci-fi kernel which is of RISC 5 sock inside so the first thing is it is supporting the four modes so that user mode supervisory mode hyper hypervisor and the machine mode so user mode anyway it's a basic one where all user space programs going to run and supervisory is to support the Linux and hypervisor mode actually right now they are telling that the sci-fi maintainers telling that it is not specified now but actually right now they are giving the patches last night they are pushing a lot of patches on the hypervisor part and the machine mode is the one that which is a the low level area which part of the BBL the Berkeley bootloader code will be presented in that machine mode level so it is the actual one like when we are talking about that m heart ID or the m return so that m and that m represents to the machine instructions and the S represents to the supervisory mode instructions and the SPI which we are talking about that supervisory SBI is a combination or it can be a interface between the machine mode to the supervisory mode let's check that one how it work so now the booting party with respect to sci-fi so they are actually using the BBL that's a new bootloader you can say the Berkeley bootloader I mean regularly you go with the you would are the normal bootloader so these guys are using with the BBL so this BBL is the combination of device tree and the SBI it's actually teeny bootloader compared to the you would so anyway the device tree usage is equivalent to the basic one only it is not specific but when you see the SBI usage it is it's a combination of interface it actually provides interface between the machine mode to the supervisory mode we can understand that part so that BBL's entry point will be running in the machine mode which is taking the device tree entry from the earlier or you can say that the first stage bootloader it will take that BBL and then provides to that one so by that time one hot ID the hot ID matching but not even the core we can say that a core ID or the CPID which is we represent as a CPU 0 right because basically in ARM we can if you are talking about always the CPU 0 will be the core boot I mean are the you know the first boot will be with the CPU 0 same thing they are telling that the one heart will be taking as the main heart and the other hearts are put it to the sleep like how we are taking about our WFI or WFE wait for event or interrupt so the kind of things they are telling that but the one that they are saying that it will be put into the sleep mode where they just keep running that with respect to spin lock that we will see later but yes the point is here BBL's entry point is from the machine mode and it is going through the one core that we have to provide which is the CPU 0 always and the other quotes we are putting into the sleep we will see that how that SMP initialization will be done here and see so all the other hearts have woken up woken up so that they can set up their PMP PMP nothing but the physical memory production trap handles and enter into the supervised mode this is provided by the setup part actually like how we are doing in a regular kernel we enter into the secondary core right same way by that time once it is been getting once it is going through the main heart ID after that it will be woken up all other hearts so the thing is here the functionality wise RISC 5 or the ARM or XID 6 is common the thing is adaptation with the existing instructions how they are going to use is the one that we have to understand so based on that I am trying to give that M heart ID or whatever that machine mode or supervised mode instructions maybe it is the terminal device it is pretty new for me it is new but yeah the try if you are trying to understand the functional device is equivalent to the ARM or any other regular architectures but yes yeah so yeah when we are trying trying out that M heart ID CSR so this is passing to the Linux which is of per heart identifier and then PMP physical memory production okay so that mission mode wrap handlers including a mission mode stack is set up these are all are the regular stuff that what the core one or the core 0 will do actually and then that M return will says that I am getting into the supervision mode and so that you can you can start getting into your Linux kernel so now we will see that early boot in Cypher board so here what we are going to present here so if you see the code actually there is a kind of code called disk 5 iphone pk there is one directory there they mentioned that there is a 0 and a 1 like how the ARM contains R0 R1 and R2 here this R0 is always a 0 contains a unique per heart ID map is hard ID to the Linux CPU IDs that is of core 0 actually and they even contains a pointed to the device just like our R2 in the ARM architecture and then memory is identity mapped because by the time I do not have any MME initialization and then kernel CLF image has been loaded with all the various segments at the addresses this is the common thing for the two architectures and then heart ID specification so in early boot risk 5 system boot hearts in an arbitrary more order like here the change comes is it keeps spinning there and whichever this core is getting out I mean the secondary course that will be identified and getting all the traps are the PMBs will be loaded into that so that is the only change that I identified coming to the regular ARM or x86 course or even PowerPC course so this is managed using the heart lottery system they are talking about so we will see that how they have defined that heart lottery system so the rest of the heart spin waiting for the Linux to boot for the far enough so and and part of that that is one thing which is we are talking about this heart ID management and then the page offset will be initialized by this time and the paging is unable and the C runtime will be set up over there and the spin only trap factor is set up and that catches any others early in the boot process and the start kernel is called to enter into the standard Linux boot process so the thing is here might if you try to compare this whatever I added here this is basically the base port they are talking about because if let's say that if you go back when when when any pretty new architecture comes might be I remember that you know the Russell King the guy who has ported ARM into the Linux in first time right so the way that art is an ARM code it can be kernel it can be setup dots here it can be MM lips it's a pretty simple code right the kind of thing that we have to compare actually because the kind of area right now we have a porting on the sci-fi board is pretty simple so that way like if I go for a you know 15 60 years back the kind of ARM coding provided to the board and how much that right now we are available on the sci-fi because the way that we can expect the area of the code that we can add into the arc slash risk five right there's a pretty huge because if we see the regular board how that sci-fi board or any risk five dog what are all the things it contains and how much it is defined in that area it's pretty very less that is why you can see that the page offset or paging Siri and time directly it's going to see random setup but if I see that either it's a power PC code there we can see that MSR registers or a lot of issues over there right and even in the arm we can say that compressed head dot as I mean there are a lot of things happen which are all defined later on but by this time for the risk five it's a pretty simple one and I can say that yes my board is up so I and if I want to add a piece of code in that area yes we have a lot of things to add over there and even you know that yesterday in the keynote they're adding that risk five open hardware specification is one of the project from the Linux foundation right so based on that once we keep changing that specifications the instructions that what we are talking about and the piece of code that we are going to add in this area will be increased in a huge way because we can identify that the base porting starting from this area it will be you know at least continues for the next two or three years of course for the from the open source from the Linux foundation projects I believe so that is why it is pretty simple that it's going into the start kernel maybe you know it's very it's very you know 4 to 5 steps that we are doing it and getting into because that is a basic setup that I can enter into my start kernel because once I say start kernel it's a kind of thing that we are entering into a architecture independent code right it's a completely my kernel code so before that I'm telling that setup part actually so whatever the things that we are doing them in the kind of porting that we have written in the for the sci-fi is one thing is enable the early print case support because why these things I'm trying to explain is when we say any board bring up right the starting from the IRQ controller setup I mean from the DTS after that we talk about the timers clocks early print K SMP GPIO pin control you what so these are the eight controllers we talk about if these eight controllers are up then only we can say that my board is up right that is a first level board bring up and in the second level you can say your ITC or SPA PCI sort of boards or whatever USB what are the things will be common in the second level but when I say I'm giving you earlier print or early board bring up these eight controllers I should make it up but in this case I can say that my early print case support is up here I can say that the code that I've added here so this is part of my art class risk five in the setup.c code so this is a simple function that they have written by this time and it is taking care of my early print case support but actually if we try to compare or if I want to add more piece of code here yes we can add it right so part of the setup part actually I'm talking about like let's say if we can compare this area with respect to either arm or x86 or any other architecture we can see that there is a lot of changes or lot of code can be added here so that is the intention to add this slide because it's pretty simple but it is actually not that much simple right so we can see that there is a more options that we can add here right. Kernel command line passing anyway that's a simple thing and device memory map is passed that is anyway part of the kernel stuff so now one thing is early print case support we are trying to show and then memory management subsystem is initialized and other hearts in the system is woken up that is part of SMP enablement and process ISC reads from the device and used to fill out the hardware cap field in the ill of auxiliary vector let's show you that what that memory management subsystem is doing if you see that present code right they're trying to support the normal zone and the DMA zone that do for the 32 bit DMA bound buffers so with this we can find out that how much that may be for that DMA bound buffers how much that we are supporting and how much that max we can add in this area so that is one area that we can add a lot of code here we can see but the only restriction part is with this there is only one board from the sci-fi and it is pretty much costly that way that actually the restriction part when we when anyone wants to work as a open source engineer but yes it supports on the chemo but it's you know anyway the emulator is always restricted one but yes once we get that board and you know lesser cost maybe you know these areas will be developed as much as early that's what my feeling so this is one thing that memory management part and I will show you that SMP and the hardware cap right this hardware cap actually decides the type of the instruction set architecture we are going to fill it out so this is the one like when I talk about ISA to hardware cap of IM, A, F, DC means F is the kind of floating point instruction set I is a kind of integer M is a kind of multiplex and division I believe and A is a kind of atomic F is a floating point and D is a double floating point and C is a compressed instruction set so these are all the instruction sets supported by the RISC-FI but here in this we are adding it to the I that means integer instruction set RISC-FI 30 to 64 bit integer instruction set we are supporting so this RISC-FI fill hardware cap which is part of my setup architecture will be taking care of my this function based on that I want to fill it out which was what type of ISAs I want to load right now the SMP initialization how we are doing the SMP initialization here so we are talking about the remaining course are all put into the sleep and it will be wait for the time whenever it comes it will be very woken up right so for that they have given the this piece of code that I have taken it from them right so this is just a CP of is anyway regular kernel function that which is taking from that one when it's coming up once that heart it came up it will be taken it and getting into that the all other PMP strap and that will be set to that heart ID and then SPI shutdown so the difference that we can find out that SPI supervisory binary interface which they have added in the RISC-FI might we didn't see in arm actually but it's actually that that's open SPI project that they have done it which is a kind of in this project they are trying to use it in between the machine mode and to the supervisory mode like you know kind of API is there sending out so with that API is we are telling to the mission mode boss you change from this mode to the other mode by passing just an argument kind of user space API is we provided in inside they're providing that that SPI actually so with that you can see that and the machine power off I am just saying that SPI shutdown into the veil one loop right so now the traps how to execute the traps so there is much there's if you can see in the bbl.c file in the bbl code actually there's one file called traps.c regularly we can see in an arm or power PC right if there is any traps I can say that it's a kind of synchronous interrupts synchronous means which is of predefined or you can say that by this time I can get it like you know prefaced about a data about a data storage a program exception kind of power PC exceptions so there we used to maintain type of a veil one loop saying that we are entering into an exception loop we have to get into hang over there right so these guys telling that to handle that we are using a kind of registers called that scratch register that s t vector register as call register and the s cause s cause is the kind of one which will find out that what actually make you to enter into this as call is the one that from kernel to the ways to the user level it is telling that it's something like a system called that we use right kind of instruction is provided so it I mean don't get into inside of this but I added at least one slide extra but the intention is it uses the s s crash supervisor discuss register which will take care of my trap handling exception okay so yeah the CSR provides a single excellent size save region and all software context switching implementations uses register whatever the extra information is actually required to make the context switch so that is what I'm trying to explain that earlier if there is any exception happens I want to save the existing registers into one kind of you know process control block right so part of that we are trying to use one that scratch register which will keep all my data and do my action and going back and fill out the existing one which are being already stopped over there right for that we are using that a scratch that's it so the main thing is we are trying to identify the adaptability maybe that a scratch I never know earlier but as we are going to the risk 5 we came to know okay that a scratch is for something like a trap initialization or something kind of that so when we are trying to write tomorrow with open risk for hardware specifications or any other new board with respect port so these are the technologies are these because that functional device we never change right but the thing is only the adaptability that is why I'm trying to add that word adaptability to the existing functionality with a new instruction set architecture is the only thing that we are trying to learn here right so handle exception code also present provided here and we can see that how much that we can add the code here of course I really didn't want this when I've gone through this code but yes definitely we can add a kind of extra stuff here yeah now s cause CSR and s call and s crash these are a combination of things which will be finding out what type of user space call get into kernel so that it is entering into your S return so it is just a combination of those things I have captured one timer interrupt over there so when we get the timer interrupt the SCC nothing but a supervisory execution environment determines the timer interrupt occurred with the s call and enters into supervised trap handler in Linux it is handle exception and that calls do IRQ which is of a generic IRQ call Linux call and then do IRQ calls the risk 5 interrupt IRQ so when I say risk 5 INTC this is my this is the one that you have defining right this is for our architecture we are defining this is an interrupt controller drivers interrupt handling function so this risk 5 INTC call the risk 5 timer interrupt which we are defining over there telling that boss I got a timer exception over there on the top level and we are getting inside and we are trying to make sure that we have to take care of that exception sorry take care of that interrupt and the final thing is the paging and MMU so paging anyway we know that when we are trying to access a particular page there will be definitely a kind of privileged levels right so for that this risk 5 is telling that I have a user mode supervisory hypervisor and the mission mode like how that modes we have the same way that we have we are getting the privileged levels also because from one level to the other level let's say I am into machine mode I want to let's say I'm in a top level user mode so the user mode is user you you you the college user execution environment and a supervisor is a CE so every time once you want to enter from the user to the supervisor supervisor next level there should be a kind of trigger should come over there then only we can enter into that particular page area it's like you know the kind of basic memory management but as based on the modes that what it is providing that modes corresponding to that execution environments kind of privilege levels in a sense like I have a maybe set of flags that I set to enter into this area otherwise I cannot it's a simple kind of thing so what type of page size it is having I'm trying to capture into one slide only pages are of 4k besides at each leaf node and RV 32 I base systems can have up to 34 bit physical address with a three level page table and 64 I base systems can have multiple virtual address with starting with 39 bit and extending up to 64 bit in increments of 9 bits so now with respect to the existing sci-fi code right I can see that in the memory management unit there is a lot of patches going on because they're trying to expand that PTE bit extension which is not yet done so if if anyone wants to walk on that yes it is there definitely we can give a patches over there that is one thing and yes mapping must be synchronized by the why are the S fence dot VMA that that fence is nothing but instruction equivalent to that dmb right dmb of arm architecture kind of a memory barriers so which which will take care of my synchronization part of the memory devices okay and what other thing is that there are dirty bits and there are bits for global mapping supervised only redirects good so this is all simple things like when you are saying any memory production unit pages we use to provide a kind of flags over there in the mpu in the mmu.exe right so those things are all provided here they're telling that yes we are giving the port support to these areas also in the MMU so now yes till now what are the things we have checked is the paging support MMU support the trap support and the regular setup practice support and the booting support early boot support so with these things they're trying that I can find it in the RISC-5 in the chemo emulator so with that I try to capture that how it is going to run so now there is a set of commands that provided I mean it is already there I provided you that RISC-5 getting started guide from there we can find out all these the corresponding chemo code support chemo RISC-5 support chemo code with that we can try it on our regular x86 base pieces without use of any requirement of RISC-5 board so that we can try it on the chemo itself so with that it is it is working successfully you can see that the bgb Linux is running up and we can see here proccp info here the heart will be 0 that means my core ID or the core number is 0 and the ISC instruction set architecture is RV64 IMAFDCSU I mean I really don't know what actually this complete extension is but yes it will be supported integer atomic floating point double floating point compressed and I don't know what that s and u means but yes so the existing the intention of providing this page is yes with this basic support whatever the support I showed in the earlier slides with that I can get into this kernel running on this and the basic from where the file system is also getting up and running so if we want to add it extra it can be you are giving to the servers you are giving to the mobile source or you are giving to any hand-held device because I can say that the western digital guys and the micro semi guys are already walking thoroughly on this sci-fi boards for the servers for the file system enablement and all but I can see that you know the areas that where you can hit is a hand-held devices that means you know with this if I can run a regular android OS or any or any custom OS there custom file system there might we can use it for the kind of devices where we can hit to the market right so that area is really interesting that anyone wants to work that is the one thing that I want to add and this is a reference that I took it so actually the guys from the size of has given the kind of blocks from there that I took it and the code areas that I've used only the RISC-5 the BBL code only and the regular kernel code RISC-5 supported code and it has been already mainline so that it can directly work on that yeah so that is a reference part which we can if you want to explore more we can take it out and yes we can start work on that but as it is a supported to chemo we can there is a set of restrictions but yes on the kernel side you can work on it might be not on the hardware side because chemo is always provides you the kind of IO devices the restricted IO devices it will provide but basic kernel support you can add like you know that MMU support or the trap support not the trap the kind of basic kernel architecture features we can add into the chemo and check it out the the functional device or the output wise and then we can put the patches to the community right so that that's why it will provide the basic idea of you know you know it's a pretty simple actually when we are talking about the ISA itself the Rixfa instruction set architecture itself is pretty big and it's interesting actually but because I didn't capture that it will be you know pretty big but you know if you are tied to understand that Rixfa ISA it is really cool because you can see in the ARM architecture we have total 56 instructions right of type 8 8 types I believe because for register to register there are 8 instructions for memory to memory 8 and for immediate load address 8 like that 7 types of each 18 to 7 56 instructions but in coming to Rixfa total they have 47 instructions only of type 6 instead of 7 there here 6 types only that means you can do the register to register operation immediate load address operations and the branch and instructions operations with reduced instruction set compared to ARM that is one advantage that we can see so when we are trying to enter into that trying to understand that ISA model that that those things will come into the picture so with that we can write a better one or you can explore more I cannot say that better one you can explore more to add or the restricted one and and they mentioned that the total entire boot code that entry data is right they mention like 71 instructions only they have used sorry 71 commands they used to write the entry.f code so I didn't explore that for what how they are going to do that for 71 instructions but yes they mentioned that yes they are doing it with a pretty low level code storage sorry instructions so with that yes I am closing it okay is that is that anything useful or I mean because I know like you know maybe few guys are aware of that Rixfa architecture earlier maybe you know it is easy to understand if not it is pretty new even for me when I started it is new for me so the way that but yeah I am trying to compare always how my power piece works how my arm works so that how my Rixfa is going to work so that it is you know kind of thing that I can say that it is easy but yes we can say that there will be lot of work in the future in this area we can we can explore more right so you have any questions we are out of time actually