 Hello, and welcome to this presentation of the STM32MP1 system timer generator. The system timer generator, or STGEN, is used as a system counter for Cortex-A7 timers. The system counter expectations are resolution, 64 bits to avoid rollover, counter-red S232 bit registers, CNTCVU, CNTCVL, monotonic counter, sufficient accuracy, counter can be saved and restored by software across the low power state, counters starting from zero on system reset, trust zone secureable, and counter halt during full debug, optional. This is a block diagram of the STGEN. It is composed of a 64-bit system counter clocked by TSGEN CLK to provide a clock counter to the Cortex-A7 CPU for its timers. For trust zone support, control registers are aliased in two sets. STGEN R is the read-only registers subset, such as counter value, accessible by secure and non-secure environments. STGEN C is the full register set, read-write accessible by the secure world only. The HLTDBG signal is used to halt STGEN when both Cortex-A7 CPUs are under debug. During the boot phase, the STGEN is clocked by HSI, around 64 MHz, until HSE is set up. At that time, it may be switched to HSE by software. During run, sleep, and stop modes with HSE clock on, STGEN is clocked by HSE. During stop mode with HSE off, or during standby mode, STGEN is stopped by software. STGEN is enabled on wakeup, and the counter may be adjusted by the secure software for accurate time using RTC information. The counter can support transitions between high, HSE, and low HSE frequency clocks without any impact on the required accuracy of the counter. Application software can access the CNT FRQ register to read the STGEN clock frequency and modify the value of this register for calibration and timer accuracy purposes.