 Welcome to this presentation of the STM32L5 Direct Memory Access Controller or DMA. It covers the main features of the DMA controller module, enhanced by the new DMA Request Multiplexer or DMA MUX module. The main application benefit of the DMA is to offload the CPU for trust zone-aware data transfers from any memory mapped source towards any memory mapped destination. STM32L5 DMA features two DMA controllers. For each DMA controller, it is possible to do programmable block transfers with eight concurrent channels, each of which is independently configurable. Programmable channel-based priorities transfer via the AHB Masterport connected to the bus matrix. There is also a DMA Request Router or DMA MUX with Programmable Request Source Selection, either from a peripheral in DMA mode or from a trigger and then internally generated. Synchronization Mode From a Synchronization Input with a DMA MUX Request Counter Request Chaining A DMA MUX Request Counter to generate an event that is an input trigger or synchronization to another request or channel. Trust Zone-Aware DMA and DMA MUX Resource Isolation at the channel level Secure or Non-Secure Channel If TZEN is enabled Privileged or Unprivileged Channel There are 90 peripheral requests and 4 DMA MUX Request Generators There are 23 triggers and synchronization inputs There are 16 DMA requests, 8 per DMA controller Let's focus on the DMA controller. Each channel of the DMA controller is independently configurable. A channel can be assigned to a DMA hardware request from a peripheral in peripheral to memory memory to peripheral data transfers or peripheral to peripheral transfers. Alternatively, a channel is assigned to a software request in memory to memory data transfers. A channel is programmed with a priority level. A channel is programmed for a number of data transfers at a block level. The software can control a channel via separate interrupts and or flags upon programmable events, such as a block transfer complete and or a half block transfer complete and or a transfer error. A faulty channel is automatically disabled in case of a bus access error. A channel is programmed for a number of data transfers at a block level with independent source and destination data size, independent source and destination start address, independent source and destination address increment, either contiguously incremented or at a fixed address. Programmable amount of data to be transferred within a block, up to 256k source data, automatically decremented by hardware. In a circular buffer mode, i.e. continuous data transferred to or from a peripheral, when a block transfer is completed, the programmed amount of data to be transferred within a block is automatically reloaded by hardware, as well as the source and destination start addresses. In memory to memory mode, a block transfer starts as soon as the channel is enabled, whereas in peripheral to memory, memory to peripheral and peripheral to peripheral modes, a block transfer starts as soon as both the channel is enabled and the peripheral sends a DMA hardware request. A DMA hardware request identifies a single DMA data transfer. Each DMA hardware request is paced and granted by the DMA, when each data is successfully transferred to the destination. In peripheral to peripheral mode, the hardware request from a peripheral is selected to trigger the DMA channel. This peripheral is the DMA initiator and paces the data transfer from or to this peripheral to or from a register belonging to another memory mapped peripheral, this one being not configured in DMA mode. In any mode, channel arbitration is reassessed between every data transfer. Each DMA channel can notify software with an interrupt triggered by any of four possible events. Half transfer completion, block transfer completion, transfer error, any of the three above events. The DMA MUX has two main sub-blocks, the Request Multiplexer and the Request Generator. The DMA MUX Request Multiplexer enables routing a DMA request from the peripherals to the DMA controllers. The routing function is ensured by the programmable multi-channel DMA Request Multiplexer. Each channel selects a unique DMA request, unconditionally or synchronously with events, from its DMA MUX synchronization inputs. The DMA MUX may also be used as a DMA Request Generator from programmable events on its input trigger signals. A DMA Request Multiplexer channel generates both a request to the DMA controller and an event that can be used as a synchronization input as well as a trigger input. Do not confuse DMA Request Generator channels 0 to 3 with DMA Request Multiplexer channels 0 to 15. For each multiplexer channel, there is a configuration register, DMA MUX CXCR with Programmable Input Request Selection via a DMA RecID field. For each request from a peripheral working in DMA mode, a DMA RecID is assigned. DMA RecID equals 0 corresponds to no DMA request selected. After configuring this channel and the DMA controller channel to which it is routed, the DMA channel can be enabled. Two different channels are not allowed to be configured with the same non-null DMA Request input. For each multiplexer channel, a built-in DMA Request counter is programmable via the NB Rec field. A served DMA Request decrements the programmed DMA Request counter. At its underrun, the DMA Request counter is automatically reloaded with the value programmed in the NB Rec field. At its underrun, a DMA MUX event can be generated if enabled via EGE field. Four DMA MUX events from channels 0 to 3 are looped back and connected to the DMA MUX as trigger inputs and synchronization inputs. This allows request chaining for a different DMA channel via synchronization and or trigger. For each multiplexer channel, there are two operating modes as programmed via the SE field. Unconditional mode, input request is output as is. Synchronized mode, a number of requests is grouped and delayed and synchronized. When the request multiplexer channel is configured unconditionally when SE equals 0, the DMA Request is transmitted immediately. When the DMA controller has served a data transfer, the DMA Request is de-asserted and the built-in DMA Request counter is decremented. At the counter underrun, if enabled via the EGE field, an event can be generated. Additionally, in synchronous mode, the request is conditioned with a programmable synchronization input selection via sync ID field, a programmable synchronization event, none, rising, falling in either edge, via SE Paul field, the single built-in request counter via NB Rec field that may be also used for event generation. After the synchronization event, output DMA Request is connected to the pending input request. At the counter underrun, DMA Output Request is disconnected from the multiplexer channel input. Finally, a synchronization overrun flag with SOFX in DMA Mux CSR is reported. If a new synchronization event occurs before the counter underrun, an interrupt is then generated if enabled with SOIE field. When the DMA Mux channel is configured in synchronous mode, its behavior is as follows. The request multiplexer input can be pending and it will not be forwarded on the DMA Mux Request multiplexer output until the synchronization event is received. Then, the request multiplexer connects its input and output and all the peripheral requests will be forwarded. Each forwarded and granted DMA Request decrements the request multiplexer counter previously set at a defined programmed level. When the counter reaches zero, the connection between the DMA controller and the peripheral is cut, waiting for a new synchronization event. For each underrun of the counter, a request multiplexer can generate an optional event to synchronize and or trigger a second DMA Mux Request multiplexer channel. The same event can be used in some low-power scenarios to switch the system back to stop mode without CPU intervention. Synchronization mode can be used to automatically synchronize data transfers with a timer, for example, or to condition transfers from any peripheral event that is mapped as a synchronization input. Additionally, a synchronization overflow can notify the software if a programmed number of DMA requests has not been completed between two synchronization events. For each request generator channel, a DMA request can be generated following a trigger event and selected as input of a DMA Mux Request multiplexer channel via DMA Rec ID field of the DMA Mux CXCR. The request is generated by the configuration register, DMA Mux RG-XCR, if enabled by the GE field with Programmable Trigger Input Selection by the CIG ID field, Programmable Trigger Event, none, rising, falling either edge via the G Paul field. A built-in request counter via the GNB Rec field, a served DMA request decrements the programmed request counter. At its underrun, request counter is automatically reloaded with the value programmed in the GNB Rec field. Request generator stops generating a request, a trigger overrun flag indicated by OFX field in the DMA Mux RG-XR is reported. If a new trigger event occurs before the counter underrun, an interrupt is then generated if enabled via the OIE field. On a trigger event, a programmed number of DMA requests GNB Rec plus 1 is generated. There may be a trigger overflow if two trigger events occur before the GNB Rec plus 1 requests and data transfers are completed. This table shows the STM32L5 mapping of the DMA Mux Request Multiplexer inputs for any channel. Assigning a request input is programmed by the DMA Rec ID for any DMA Mux Request Multiplexer Channel X in the DMA Mux CX-CR register. The same request input must not be mapped to two different channels. This table shows the STM32L5 mapping of the trigger inputs and the synchronization inputs for any channel. Assigning a trigger input is programmed by the SIG ID field of any DMA Mux Request Generator X in DMA Mux RG-X-CR register. Assigning a synchronization input is programmed by the SIG ID field of any DMA Mux Request Multiplexer Channel X in DMA Mux CX-CR register. The DMA and DMA Mux modules present in the STM32L5 microcontroller support resource isolation at channel level. This is a new feature versus STM32L4 series. DMA and DMA Mux are trust zone aware at a channel level. A DMA Channel X can be programmed by the software and isolated as a privileged or unprivileged resource depending on the privbit of the DMA-C-CR-X register as first written by a privileged software. Secure or non-secure resource if TZEN is active at the device level depending on the SEC-M bit of the DMA-C-CR-X register as first written by a secure software. Be it the DMA, trust zone aware and privileged aware AHB slave port. The secure state and the privilege state of a DMA Channel X i.e. the priv and SEC-M bits of the DMA-C-CR-X control register rule out the read and write access rights to the other configuration and status registers and the other register fields of Channel X. The read and write access rights to the registers and register fields belonging to the DMA-Mux output channel Y which is connected to the DMA Channel X via the DMA-Mux trust zone aware and privileged aware AHB slave port. Thus a DMA-Mux request multiplexer and generator channel is also isolated as a secure or non-secure resource and as a privileged or unprivileged resource. Once a Channel X is configured as secure or non-secure and as privileged or unprivileged, an unprivileged channel performs unprivileged DMA transfers. A privileged channel performs privileged DMA transfers via a privileged aware DMA AHB master port. A non-secure channel performs non-secure DMA transfers. A secure channel can perform secure or non-secure DMA transfers. With secure or non-secure data read from the source address depending on the securely written S SEC bit of the DMA-C-CR-X register. Secure or non-secure data write to the destination address depending on the securely written DSEC bit of the DMA-C-CR-X register via a trust zone aware DMA AHB master port. A source or destination peripheral or memory address is secure or non-secure and privileged or unprivileged depending on the globally configured MPU. SAU and GTZC units at the system level. CSTM32L5 system security chapter. The DMA controller generates a secure bus via DMA SEC-M reflecting the SEC-M bit of the DMA-C-CR-X register in order to keep the DMA mux informed of the secure or non-secure state of each DMA Channel X. The DMA controller also generates a security illegal access pulse event via DMA SEC-IL-ACC on an illegal non-secure software access to a secure DMA register or register field. This event is routed to the trust zone interrupt controller. The DMA controller generates a privileged bus via DMA PRIV reflecting the PRIV bit of the DMA-C-CR-X register in order to keep the DMA mux informed of the privileged or unprivileged state of each DMA Channel X. The DMA mux also generates a security illegal access pulse event. DMA mux SEC-IL-ACC on an illegal non-secure software access to a secure DMA mux register or register field. This event is routed to the trust zone interrupt controller. Each DMA mux request generator channel can notify software of a trigger overrun through two interrupt requests, one per security level. A request generator overrun is signaled when a new DMA request trigger event occurs before the request generator counter is equal to zero. Each DMA mux request multiplexer channel can notify software of a synchronization overrun through two interrupt requests, one per security level. A synchronization overrun is signaled when a new synchronization occurs before the request counter is equal to zero. This table indicates the state of the DMA controller and DMA mux according to the power mode. In sleep and low power sleep modes, the DMA controller and the DMA mux remain active and can be used, for example, to transfer UART or I2C received characters to memory and afterwards to wake up the CPU.