 Hello and welcome to the series of video lectures on the subject digital techniques for secondary IT students. I am Dr. Sri Shalasarad Kajbar and in this video lecture we are going to study identifiers, keywords and data types that are used in Veriloc SDL language. At the end of this session you will be able to identify identifiers, keywords that are used in Veriloc programming. You will be also able to describe data types that are used in Veriloc programming. Identifiers in Veriloc are nothing but the names given to the objects. The objects in this case are nothing but the, it may be modules, it may be instances, it may be nets, registers, parameters, system tasks and functions, blocks, etc. Here to the C programming language they may be made up of any number of letters, digits, underscore and dollar signs are also allowed. However, there are certain rules and these rules are the first character of an identifier must be alphabetic or you can also use the underscore character and the rest may be the combination of alphabetic, numeric, underscore or dollar. However, an identifier cannot start with the digit and identifier may be as long as one million characters and one thing you have to remember all the identifiers are case sensitive. The examples are given here, here the identifier name is n dollar 6.7. As mentioned earlier, an identifier may start with the underscore, here the name is underscore bus 2 3, the another name is shift rate underscore 8. Now many a times a programmer wants to give the name of his choice and in that case he can use the escape identifiers. The escape identifiers begin with the backslash and the name is considered until the first white space. Using escape identifier, one can use any printable ASCII character as a name. For example, here the escape identifier name is a plus b minus c. One thing you have to remember that it starts with the backslash. So anything that start with the backslash is considered as a escape identifier. Similar to the C programming languages, there are variety of keywords in verilog hdl language. Keywords in verilog are nothing but predefined non-escape identifiers and escape identifier is not treated as a keyword. For example, although begin is a keyword, backslash begin is not a keyword. Following is the list of various keywords. In the last two video lectures, we have seen some keywords such as assign, we have seen module keyword, we have also seen end module keyword, we have also seen the end module keyword and these are the remaining keywords. Here is another list of the keywords. We have also seen this wire keyword to define the wires. Now pause the video for two minutes and write down the answer of the following question. I hope you have written the answer. The answer is the first entity given was underscore wire and in this case it is an identifier because although wire is a keyword it starts with the underscore so it is an identifier. The second backslash module is an escape identifier although module is a keyword since it starts with the backslash it is an escape identifier. And the third example was end module and in this case it is nothing but a keyword. Now let us see the data types that are available in verilog hdl language. In verilog every signal, constant, variable and function must be assigned a data type. Verilog provides a variety of predefined data types. Now before considering the data types in detail let us see the values that a data type can type and we refer to them as a value set. Every data type in verilog can have either of the four values that is verilog supports four basic values that a signal can take and those are 0, 1, x and z. The zero in this case describes a logic zero or false condition. One indicates a logic one or true condition small x or capital X indicates it is an unknown or uninitialized value z or capital Z indicates high impedance it may be a tri-stated or floating value. The next data type is net data type and this data type models an interconnection between components. A signal with a net data type must be driven at all times the meaning of this is that consider this diagram here there are two AND gates one NOT gate and one OR gate in this case the interconnection between this first AND gate and OR gate is through this T1 and this is nothing but a wire because it models an interconnection between components. The meaning of this is that whatever the value this T1 wire takes it must be present at all times and this value may be 0, 1, x or it can be a z value. The most common synthesizable net data type is a wire data type for example consider this circuit suppose you want to declare the net data type in your module definition then you have to write as wire which is the keyword followed by the names of the wires that is T1, T2, K. Verilog also contains data types that model storage called variable data types and they can take value 0, 1, x and z they hold the assigned value to them until next assignment and the different variable data types are given in this table a reg data type indicates a variable that models logic storage there is also data type called as integer it is a 32 bit 2s complementary variable representing whole numbers between this big range there is a real data type also which represents 64 bit floating point variable there is also a time data type which represents an unsigned 64 bit variable between this range now let us see the vectors data type it is nothing but an array of only elements all the values of the net data types in addition to the variable data type reg can be used to form vectors a syntax for defining a vector is as follows so there will be first you will define a type followed by in the square bracket MSB index colon LSB index and finally you will write the vector name for example here the first example is wire the wire in this case indicates a data type followed by in square bracket there is 7 colon 0 followed by the vector name as sum here the MSB is given as the index 7 whereas the LSB is given the index 0 ok this another example this defines a 16 bit vector called Q of type reg this another example reg data type is defined however in this case the 0th bit indicates MSB whereas the 15 bit indicates the LSB of this data type R now let us see the arrays data type and it should not be confused with the vector data type a vector is a n bit void quantity whereas array may have multiple elements that are 1 bit or n bit void array data type declaration is allowed for reg integer time and vector register however it is not allowed for real data type also virilog does not permit declaration of multi dimensional arrays now let us see the examples here in the first example the data type is integer the identifier name used is count in square bracket 0 colon 7 is given the meaning of this is that 0th bit will be used as an MSB bit whereas 7 bit indicates an LSB so this defines an array of 8 count variables each of which is 32 bit void because the data type is integer in the second example it indicates an array of 8 port IDs each of which is 5 bit void as you can see here port ID in square bracket 0 colon 7 means what it indicates 8 port IDs and each of which is 5 bit void so this is an array data type these are the references thank you very