 Hi everyone and welcome to Embedded World 2020 here at the Risk5 Foundation. Let's have a look on the booth. Risk5 Foundation this year is really growing. We show a strong ecosystem. By the way, my name is Florian Wolrab. I'm from Andes Technology, but I'm also a member of the Risk5 Foundation. What we are seeing is that Risk5 is really gaining market traction. We are getting more and more members. We have over 500 members worldwide. There are 60 members only here in Europe. It's amazing. We see more and more hardware vendors coming. And here on the booth we have many of them exhibiting certain things. So let's have a look and talk with some of them and ask them what they are presenting today. This is some of the logos. You see these logos? All of this company is doing Risk5. It's amazing. We have it from China. We have it from South America. We have Russian guys. Of course we have Taiwanese guys. We have German guys, French guys. Everyone is doing Risk5. Let's go to the gentleman from Cy5. Please. Hi, my name is Danny Nativale. Welcome to our booth. I'm from Cy5. It's been a great show this year at the embedded world where we introduce the... Sorry, sorry. That's okay. Where we introduce our new deeper-gantary solution. We also showcased the mode of security architecture of Cy5 Shield that includes Cy5 World Guard hardware and force security solution for true hardware isolation for cores and tasks running in SoC. So what are you showing here? So we're showing the operation of... We're showing the World Guard operation. So it's like a treasured thing. So we're showing how tasks and cores are separated for each other. And when a core task tries to access a memory, that is not supposed to access, it gets an exception. So we have a core zero on the left and core one on the right. So are you being very busy working with a lot of these logos to create some chips? Yes, we are involved. We have one of the founding members of the Risk5 Foundation and some of the partners are also some of our customers. So we are working with significant customers to get the Risk5 adopted. And make better product and faster product to markets. What's the adoption? What's the growth? The growth is very significant. Everybody wants to move and get into the Risk5 train. So over the past year, we've seen a significant amount of customers moving away for existing solution to the Risk5 instruction set. What are the main challenges to create a Risk5 CPU? You first need to have a feature priority with the older ecosystem. So you need to provide good software, good compatibility with previous solutions, such as IP, security, power consumption and so on. Maybe let's have a look to the next booth. So the next booth that is Andes Technologies, that's where I'm working from. Andes Technologies is a CPU IP company. So we are doing Risk5 IP and then we are selling it to people who are making chips with it. It's pretty cool. It's pretty amazing. Market adoption. Risk5 is really great for AI, for machine learning and all this stuff. You know, with this new market where you have the maintenance predictive or where you have the voice recognition like devices like this. I'm not allowed to show the brand. But they are waking up when you say the keyword and then they are waking up the big system and operating what you want. That's where you need Risk5 where it really has advantages. Like our little Pikachu here. Konnichiwa! That's where you have our chips inside. But it's not Risk5 yet, right? That is not Risk5 yet, but we are working on Risk5 so the next series will be Risk5 and Andes is one of the leading providers. Like I said, we are coming from Taiwan, but we see a big adoption in China now and also America and Europe, more and more traction. Also Japan is really hot for Risk5. And your IP is being used by many different chips? Yes, for example MediaTek but also big storage manufacturers so people who are making SSDs using our chips. Carmakers are using our chips for the car inside the 360 degrees roundabout view. Bitcoin mining for example. These guys are looking into our chips where you have some AI, some clever things. And that's the nice thing about Risk5. You really can have the innovation. You can innovate, you can do your own stuff and you can change the course compared with other big manufacturers who say you need to take our core, you are not allowed to modify it. Risk5 gives you the flexibility and allows you to innovate and bring it forward. So when you are a CPU IP company for you it can be more fun to have the Risk5 freedom? It is a lot of fun. We have been making our own RiskIP before but now with Risk5 all the universities teach it. They contribute to the open source. I mean we upstream our codes, our GCC, our U-boot but then you have the universities, they are downloading it, they are teaching it. You have many more companies doing it. It's great. So very busy in that direction also. We are extremely busy. How far do you think it would be for a device like this to have Risk5 in them? Not far. We are working on this. So I think we will see this year a lot of devices. They are already a microcontroller manufacturer in China who has their first microcontroller on the market with Risk5. You also can license this IP from us, for example, if you want. It's the same. And we are seeing that it's now also finding an adaption and data center. So I know you are always looking for a Linux. Linux, give it one or two years and you will have your Risk5 chips and then you have setup boxes with Linux. Is it maybe a smartwatch company? It's not a smartwatch. It's our partners from Sci-Fi. They have it in a smartwatch company. We are more in the memory area, in the data center area and we are also in the AI. Like maybe you hear it from the Bitmain and all the stuff. We are kind of co-working with these guys. But those chips are actually deployed, Risk5? Yes, yes. They are deployed. You can buy one microcontroller unit on the market from GigaDevice. The assets are kind of closed source, but they are on the market, they are in mass production and they are really hot. Maybe we can continue the tour a little bit? Sure. So let's go over there to GreenWave, right here. Let's have a look at GreenWave. Hi there. We are GreenWave's technologists. We are a fabulous semiconductor company from France. We are designing IoT application processors that enable artificial intelligence in battery-operated IoT devices. We are presenting today the new platform for occupancy detection that we designed with our partner Lin Red. Is there a chip already here? What are you showing? What is running? So the platform is supposed to be recording? Yeah. So the platform is supposed to be inside. I already removed it. But what it does, it counts people when you pass by. And on the app, you can see how many people are there around the booth. What does the platform look like? So what's the chip? This is our chip. This is an example of our chip. This is GAP8. So is that a Risk5? Yes, it's based on the Risk5. All right. What's the design of this PCB like this? So this is an example that is currently right now available. So this is a micro drone that runs neural network and avoids obstacles when it flies. So it's autonomous navigation drone. It's like that. So your company designs a lot of chips? Yeah. So we're a chip company. So our chip already are available online. And we have some boards for demonstration and prototyping application. You can buy them on our website. What do you think about the Risk5 ecosystem? I think it's really cool. I think it allows a lot of start-up semiconductor companies to innovate. Because it's open source. So we can really revolutionize the market of AI devices based on Risk5. What does the open source aspect of the chip really enable you? It helps us to innovate really fast and keep up with all the algorithms available in the market. All right. Cool. All right. Thanks a lot. My name is Alexander Kazov and I'm representing company called CloudBear. We are Risk5 processor IP providers. So we are making series of product lines. So starting from microcontroller level to Linux capable core to embedded compute and the float acceleration for... What are we looking at here? Yeah. Here is a prototype of our dual core Linux capable CPU currently it's running Debian on that screen that you can see. It's a Debian Linux standard compiler for Risk5. And yeah, you can see the camera working, Quake running. So it's prototypes, it's run on 100 megahertz only but in ASIC it will be 10 to 15 times faster. But what is the chip in there? Currently this is FPGA prototype but currently we are developing ASIC together with our customer based on this core. So basically we are an IP provider and we are licensing CPUs to our customers which make complete chip. Do you do many chips out there in the market? Currently not so many but it's evolving. Many under development and I hope next year we will see more already ready chip. What's the... So you see an opportunity there with Risk5 to get into doing lots of bunch of chips? Yeah, for sure. So it is growing very fast and predicted in five years we will have 60 billion cores on the market available. 60 billion? Yeah, it's containing Risk5 devices. Who did this prediction? There was some market research agencies which are making the investigation where Risk5 will be used, what domains. What is this over here? So this is just graphic cards which is derived by our prototype. So here is a Linux course, it's BCIE and then they drive the graphic cards and these graphic cards are showing this normal Linux on the screen. And where are you based? In Russia. In Russia. Alright, so exciting ecosystem. Thank you. Thanks a lot. Let me just kick something off here. Hi, I'm Pete Shields from Ultrasock. We're exhibiting here on the Risk5 pavilion showing our embedded analytics capabilities. So what do you show here on the screen? So this is an example of a typical, the contents of a typical SOC. So the green blocks are the typical building blocks you would find inside an SOC such as various different processes. Maybe a DSP, some GPU, custom logic, all hooked up around some kind of interconnect. Maybe that's an ACSI fabric or a network on chip. And then all the blue blocks that you see here are the IP components that Ultrasock can provide to give embedded analytics. To give you insights into what's going on inside the actual system. So those can be looking at the actual processes and those processes could be a mixture of processes. So obviously we'll support Risk5, but it could be also a mixture of ARM and other architectures on the same chip. And then also we provide other modules such as our bus monitor to actually look at the actual transactions to get performance metrics and as well actually extract the bus trace from the system. And all this plugs together into an infrastructure together with communicators that get that data off chip. And so here we have an FPGA demo board. This is showing three different cores running at the same time. You can see a game of tennis taking place. You see a very simple fractal and a very much more complex fractal. So there's three different cores running simultaneously. And we can do debug of all three of these cores on this FPGA at the same time. And we could also look at the bus transactions and debug the entire system to get a good understanding of perhaps where the bottlenecks are and where the performance problems are inside the SOC. So I notice it says winner in security category for the whole show? For the show, yeah. So we won Best in Show for the security category. And this is for our new analytic module, which we call Bus Sentinel. And this actually sits in the bus itself. It has a bus monitor. And this is different. The bus monitor just listens to the transactions. The Bus Sentinel actually sits in between the bus master and the actual bus itself. And the bus Sentinel can then detect perhaps what are considered illegal transactions. And it can then acknowledge the transaction back to the bus master, but then block the transaction to its destination. So that the hacked software does not know that the transaction has been blocked. But at the same time, it blocks the transaction and raises an alarm within the rest of the system. So yeah, so we're very lucky to win this award. So this is a new way, a different way to do security? It's one way to do security. So we have various elements that we can add to the system to enhance the security. Is this implementing something like a trust zone when it's armed, or is it a different area? Is it a different area? So the kind of trust zone is something that would sit alongside this. The bus Sentinel itself may be communicating with the trust zone and be alerted to perhaps, it may be configuring the Sentinel to determine what is safe and what is not safe. But it also may be receiving the alarms. What's nice about this, of course, is that the hacked software running on here would not know that it's been blocked. The transaction is responded to in the normal manner, but the result of that transaction is blocked, so it doesn't actually end up at its destination. So the hacker doesn't know that they're just wasting their time? Exactly, yeah. And Ultrasock is all over the industry, the embedded? Yeah, so we have customers in all different verticals, high compute, automotive customers. So the application to our technology is broad. It's initially used during the development of the SoC, so whilst the design has been built, it's first then used in the lab to actually get the chip out the door, to get the system out of the door, but then it continues being used in the life of the product. So the bus Sentinel could then be used to detect these kind of security issues throughout the life of the silicon. So this award-winning bus Sentinel, how far is it from the market? It's still very new. We have several customers who are interested, and we're going to be the first revisions of the Sentinel will be released in the next few months. All right, thanks for that. Okay. Okay, let me bring you to the next booth. Like I told you, over 500 members in risk five. Here on the booth we have now 14, half of them you have seen, and now we will go to one of the next one. Let me introduce you to the Open Hardware Group. I think you have heard about them. That is headed by Rick O'Connor. So what these guys are doing, they bring a lot of companies together. They bring a lot of IP together, and then they make this IP usable for some chips. So you see we have universities, but we also have big names like NXP was here, and many others. So that's really nice. That allows you to use the IP and other products. I think we should go to the next company. It's Syntacore, my favorite. All right. So I'm Alex, I'm with Syntacore, and as a company we are focusing on risk-high-compatible processor IP, and we also provide one-stop customization service around those IP. Here on the XGBit we have a few interesting things. We actually have our smallest core and our biggest cores, which support quite heavy multi-core configuration here on the XGBit. So here we have some samples of our completely open-source core, which is named SR1, and everything for this core and to deploy it is on GitHub. Quite easy start, sort of self-starting platform, a lot of collateral documentation, etc. What are we looking at here? What's the chip? The chip is by our Chinese customer, and I believe it implements both sort of power delivery functionality and interface conversion, because we think there are different products based on that, things like that and some cabling connectivity solutions. That's RISC-5. It's RISC-5-based, based exactly on our open-source design of microcontroller class. So on the other end of our product line is quite capable, out-of-order multi-core design, and we have it here on the XGBit as FPGA prototype, and we have live demo, in which we actually have octa-core system running full-debian distribution. It's FPGA-based, but it tapes out this year with one of our customers. We are very hopeful about that project. It was very interesting. So it tapes out, how's it going to look the chip? How big is it? How much performance? It's quite big. In terms of performance, the core itself is like mid-range if we compare to the alternative ecosystem. So it's octa-core, dual-issue design, around 5 core-mark per core, fully coherent memory subsystem and things like that, but the chip itself is not about that. I cannot really disclose what it does because of the customer agreement, but they agreed to go public about it later when chip comes back, so maybe at that point you would be able to disclose more. Can you say more about the background of the company? It says custom cores and tools. Yes. How long time have we been doing this? So we are a founding member. We were here right from the beginning. Our core technology is ACIP, so we know exactly how to customize cores, tool chain and software stacks specifically for the customer task. And before that we come from more than 10 years of highly-reliant background. We've been doing quite similar things and applying them to some interesting domains in major multinational corporations, the team which established that company. So how's the atmosphere around these custom-sourced cores? It's quite exciting, I would say, so a lot of interest definitely. The initial wave was mostly, you know, enthusiast and maybe startups and other early adopters and now we really do see how it takes off and major companies starting to pay attention, starting doing something, so we definitely feel that interest. All right, cool, thanks. You're welcome. Good afternoon, my name's Kevin McDermott and I work with Imperus. In Imperus, we build a software simulator that allows you to simulate a processor before you have hardware. So with a virtual platform, you can test and develop your firmware and software, your drivers, all before you tape out. We have a quality model of RIS-5 that allows you to do verification. So what are you showing here So what we're showing here is the design flow that helps you work through. Let's flip this over. This is an interesting flow talks about how to build a custom instruction. With RIS-5, which is an open ISA, allows you to use a modular approach and add different extensions into a potential new hardware design all to optimize and run your application better. The best way to start with this is to take your application code for good areas of candidate instructions that would help you build a more optimal solution to run your software in dedicated hardware. And at the show you announce... We've got two announcements here. For the first time, we've done a UVM encapsulation of our reference model in a system verilog environment. This allows you to do a step and compare in system verilog with your target processor against the model and we have a diagram on the back here. This diagram here shows you taking a directed test or a compliance test or a Google random instruction stream generator test and applying that into system verilog where you can run your RTL model and your reference model step by step to compare the outputs. And there's another announcement you said? Yes, the second announcement is we've worked with a company to develop a verification flow which is on the next diagram which is a way to look at the quester simulator comparing with the reference model and then do coverage analysis. This is to look at whether you've fully exercised all the corner cases of your processor before you tape out and clip that over for the diagram. So here we're showing the Google instruction stream generator through a compilation into the mentor simulator for the RTL in the imperial simulator for the reference model and then you can compare the outputs and then look at the coverage of what actually happened on the processor. So how would you define the adoption of the RISC-5 thus far? Well, in certain markets when there's a new application area such as AI you've got a heavy workload, big algorithms, lots of data sets and they're looking at how to optimise the hardware that would best fit that algorithm. So with RISC-5 you've got this module approach, you can build a custard array and you can build custom extensions that fits very well to these new algorithms. Jeremy Bennett from Embercosm We develop open source compilers in operating systems and pre-silicon models for all sorts of architectures but a lot of it is RISC-5 these days. So what do you talk about here, what do you show? This is showing all the places we fit in and it's amazing how much open source there is. From the modeling whether you're using C-gen or table gen to make cycle acryl models, QMU for fast system models, Verilator and GHDL for cycle acryl models, there's even open source event-driven simulation traditionally done by commercial companies but Icarus Verilog is an open source event-driven simulation. So you're pre-silicon you've got your model of your RISC-5 and then which compiler do you choose? The big ones, GCC or LLVM we can do those but the specialist one, the small device C compiler, the plan 9 C compiler and of course there are still commercial, the one player left standing in the commercial space in the proprietary space is IAR systems but it's dominated by companies making open source compilers and then on the right we have all the operating systems and it's completely dominated by open source. You just don't get industry looking at all at anything other than open source operating systems from the big source distributions, embedded Linux embedded free BSD if you want something more secure the custom real-time operating systems things like Apache Minute and then down to the traditional deeply embedded real-time operating systems, very lightweight kernels like Zephyr or Friatus so we provide you with the support all the way through for that, if you've got a custom instruction set extension for RISC-5 we can provide you a proper compiler that will take full advantage of that, we can bring up your operating system kernel, develop your device drivers to work with that and all before you've got silicon. So it's like support? We're a service company, we're providing the skilled engineers who can do that, you want GCC for your RISC-5 extension we will provide it, you want operating systems for your extension we'll provide it, our engineers are deep experts in that field and you do much better by going out and getting someone for whom they live and breathe this stuff and trying to just do it yourself and there you have a board connected, let me tell you about this, so this is one of the most widely available ARM boards this is not RISC-5, this is an ARM board, it's an ARM Discovery board and the reason it's here is one of the initiatives we're involved with is the Mbench project and Mbench is a community effort to bring a next generation of benchmarking to embedded systems and we've used it to benchmark RISC-5 but the baseline on which the whole project is based is ARM Cortex M4 because your baseline should always be the established incumbent mainstream player, so that's the baseline and we can compare RISC-5 against that, see how fast RISC-5 goes, see how compact the code is and on deeply embedded IoT systems code size matters as much as code speed. So what do you find out so far, do you find out that the code is compact? So we find out that the code is roughly equivalent, statistically you can't tell this apart, if you're going to choose between ARM and RISC-5 there are all sorts of reasons to choose one or the other but actually when it comes to code size and code performance in general they're about on the power Cortex M4 or a 32 bit RISC-5 IMC core, they're about the same performance. Are you able to do everything in this field like anything people would want to do? Anything at that low level system level that's what we do, they're deeply specialized fields, we don't do general support but we do do detailed stuff, so compilers, we've got some of the world's top compiler engineers operating systems the same and that's what we do. Alright, thanks, thanks a lot. Hopefully you've got enough there I'm Philip, I'm from Codesip what we do is that we provide our own processor IP but we specialize in customizations of the IP so our customers can start off by taking one of our predefined cores which are all modeled in our own architecture description language so it is much more abstract than just doing the design in HDL and they can do their own modifications which are very often adding new instructions to the model but they can also do some customizations to for instance the pipeline. What is our newest product actually that we're preparing now is in collaboration with Western Digital who decided to open source one of their RISC-5 cores and since they open sourced only the RTL we're working with them to provide a support package which will be a collection of open source tools but also some support and scripts and documentation for commercial tools so that developers can start working with the core as easy as possible. So Western Digital is doing a lot of power drives SSD and stuff like that. So does a chip target that market? Yeah, it will be in a flash drive I think. And so it's optimized in this kind of use case. Yeah exactly it's rather a MCU but a quite high performing one. So how would you describe the market adoption RISC-5 how much activity are you doing in there? Well, we're usually collaborating with customers who want to build their SOC on top of our cores obviously. And especially the ones who have very specific needs so that they can leverage the ability to add their own extensions to the core. So that means some cybersecurity companies or something like that. But we receive actually a lot of interest in the open hardware now. Some companies are interested to use the open sourced RTL so I think this will be also an important part of our business in the future. Well, thanks a lot. Great. So you have seen how RISC-5 is enabling a free and open process architecture where everyone can make his own CPUs based on this ISO. You have seen how the diversity of these people from software enabling security, enabling the compilers and then to IP manufacturers of processors. RISC-5 because it's kind of open because you can make your own processor or you can license it. It's diverse, such a big field and it's getting more and more bigger. What do you think? Do you have any questions? What do you feel about RISC-5 because what we see is that this is the new market trend and you will see more and more people will use RISC-5 so we are very happy. Thanks a lot for doing this tour. It's really awesome. It's too bad I arrived on the last day and the CEO is not here, right? It's a pity with Callista. Can you say some more? Yes. Callista was actually talking of the transformation in this industry, of the transformation. You know when you started in the beginning you had these guys who were making processors and it was faster, faster, faster, more transistors but more slow is kind of coming to an end and we need to find more diverse ways to innovate. We need to find something how to make it faster without packing double of the transistors inside and that's where RISC-5 comes in, where you can make your own instruction, where you can make your own special hardware, software IP. The big universities started to switch their teaching. They are now teaching with RISC-5 and that means the students coming out of university will know how to use RISC-5. Look at all these people. It's amazing coming together in the industry and making this new RISC-5 architecture. So that is Callista's message and that's why we have the RISC-5 foundation to push this, to allow companies like Andis but also others like Syntacor you have seen or RISC-5 to generate this new market, to bring this new dynamic inside and really create and innovate new applications for microcontrollers. So it's 5 years now, right? RISC-5, 5 years old? Roughly, yes. There was some launch 5 years ago. Yeah, that was when we founded the foundation. A lot of people you saw here today have been starting from the first minute but the foundation is now 5 years old. That is correct and it's coming from Berkeley, the university in the United States. They had some tries before but yes, 5 years since we have this foundation and more and more members. What's happening in the next 5 years? In the next 5 years? That is my personal opinion. I'm going a little bit bold but if you see all this stuff, in 5 years we will have mobile phones running on RISC-5 so there might be other course inside but we will have it powered on RISC-5 with Linux, with Android running on it natively with full speed like you're used today.