 This paper proposes a new implementation of a physically unclonable function, PUF, using the NAND SR latch architecture on the Xilinx Arctic 7 FPGA platform. This architecture uses fewer resources than other PUF implementations, resulting in better reliability and lower power consumption. Additionally, it was found that the proposed PUF architecture outperforms existing PUF architectures in terms of reliability and resource utilization. This article was authored by Ricardo de la Sala and Giuseppe Scotty.