 This paper proposes a new hardware algorithm for an integer-based discrete cosine transform, INT-DCT. It is designed to enable efficient VLSI implementation of the discrete cosine transform using the systolic array architectural paradigm. The proposed algorithm has several advantages over existing algorithms, including efficient hardware implementation and sufficient precision in approximating irrational transform coefficients for practical applications. Additionally, it can be restructured into five regular and modular computational structures of lengths of four and one of length two, known as pseudocycles. This allows for efficient VLSI implementation using systolic arrays. Furthermore, the proposed VLSI architecture includes a tag control mechanism that enables the integration of an obfuscation technique that significantly improves hardware security with minimal overheads. This article was authored by Daru Florenchipper and Arkady Kraken.