 Hi friends, welcome you all to the 18th session of home base development. So, in today's discussion we will be touching upon instructions. Now, actually in the last session I have covered how thumb is implemented and what is the background of thumb design and philosophy of the thumb design and then why does anyone require that mode ok. So, we have a good understanding of that now. So, we will look at the thumb instruction in this session.My intent is not to go into the details of every instruction as we did for arm instruction set ok, because there is not much of difference except that it is this instructions are subset of this. So, I will give you a summary of all the thumb instruction and I would expectas a assignment know you can look at every instruction of thumb and then know maybe you can write a no difference by the way in what is the arm okand then what is supported in arm and then what is the difference in the thumb mode ok the instructions thumb mode instruction. So, I would like to give it as an assignment of looking at all the instructions of instructions supported in thumb state ok. So, in this discussion we will be justgiving you I will give you a some major differences between arm instruction set and the thumb instruction set and then we will carry on with the inter processing module ok. The topics that are going to be covered I will touch upon this push and pop instruction which you are not seen in the arm state and then some minute differences in the conditional branches implementation in thumb state and then I will give you a summary of all the instructions with the major high level difference between what is there in arm state and how how does it differ in the thumb state ok. Then we will spend a majority of the time on inter processing in the session. So, followed by this in the next section we will go into the actual implementation of some of the interrupt handlers ok I will show you some assembly implementation of the few of couple of implementation of interrupt processing and then we will go into the details of how it is done ok. So, that is going to be the next section. So, in in this section this is what is going to be covered ok push and pop if you are familiar with x86 processor ok you might have seen this instruction ok already. So, thumb state has a similar push and pop which you did not see in arm state ok. So, I will show you what is the difference how push and pop differs from the instructions that we are used in arm state ok. So, now you can see that the instruction length is only 16 bit ok this is the encoding of the thumb instruction ok. Totally 16 bits are there ok this particular bit pattern ok all are the refer to this push or pop operation ok. And then we have one bit reserved for whether it is a load or store. Please remember push and pop is actually a stack operation ok let us draw a stack ok. This is the stack and this is a lower address and this is higher address. Now, assume the stack is stack pointer which happens to be R 13 ok. Remember in thumb state R 13 is only assume to be a base register for the stack operations ok this is a stack ok. This particular register only could be used with the push and pop it always assumes when push and pop instructions are used the R 13 is picked up ok whatever is the address stored in R 13 is what it assume to be the stack pointer ok. So, whenever you are using push and pop make sure that R 13 is initialized with the proper value and then use them. And one more assumption is if you remember there are so many modes right full and decrement right and then we have full and increment and empty decrement empty increment right. That means, when the stack pointer is pointing at whichever location it is assumed to be full that means, it is already filled with some value. So, when you want to do a push operation ok it is already pointing at full and then what are we supposed to do? Decrement the pointer. So, R 13 is supposed to decrement and then load the first value in push suppose this is the current location where the R 13 is pointing at and then we have an instruction push ok and format I will tell you, but suppose you are put R 2 ok. Please remember this can be only from R 0 to R 7 ok only these registers could be used, but there are special cases where R 14 and the R 15 will be used, but for a generic purpose only these registers are you can be used with the push and pop. Now, when we do push R 2 suppose what are we suppose what are we trying to say R 2 whatever is the content of R 2 which happens to be some 32 bit value needs to be pushed into a stack, but in this in the instruction we are not mentioning whether it is decrement or full or empty we are not saying about that. So, it is implicit in the term state it is always assumed that the stack is going downwards that means, from the higher address to lower address ok from higher address to lower address it is growing. Why do you say growing when we push something into the stack the stack is growing because more items get into the stack. So, when we push it is growing and when we pop it is decrementing right it is decreasing the number of items in the stack is coming down. So, effectively when we do a push we have to assume whether it is pointing at the empty location or a full location, but here in term state it is always assumed that it is pointing at a full location that means, already some value is there. So, it would not write into that location it will decrement it by how many bytes 4 bytes because we are pushing 32 bit values into the stack. Please remember in the term state also the data is assumed to be a 32 bit value ok push and pop always does a 32 bit push and 32 32 bit of by pop operation. So, a 32 bit value that is 4 bytes are pushed into the stack. So, R 2 will come here the value in R 2 will come here and stack pointer will point at this location that means, what has happened it will automatically get incremented to the address where it is currently pointing to it is not incremented here because it is going down. So, it is decremented by 4 and then it is pointing at R 2. So, this is how stack grows in the term state ok. So, so how is it converted whether you are giving a push or pop based on that this will be see this is the CPU and this is stack. So, we are writing into this for push into the into the stack and then we are reading it from stack for pop operation correct. So, it will correspond to what it will correspond to store in the ARM ok and this will correspond to load LDR ok. We are loading some value into from the stack into the register this is the CPU ok. So, push will correspond to store ok. If you say pop then it will be this bit will be set pop this particular bit will be set when it is encoding this instruction ok and then these are all stand you know always 1 and 0 and R this is a another 2 registers. See if you recall I mentioned that in term state only R 0 to R 7 could be used in all the instructions and then some of the high end registers could be used ok selectively. So, and then also I said that the the job of each of this higher registers are fixed. That means, R 15 is always assumed ok it is true with ARM state also is PC and R 14 is for link register ok and R 13 is stack pointer. So, this is not actually fixed in the ARM state, but it is a fixed in the term state R 13 is always assumed to be a stack pointer that is what I mentioned that push and pop will always assume that R 13 is what is used as a pointer to write into the stack and then it is automatically decremented or incremented based on push operation or pop operation. So, that write back also is assumed ok we we are notyou know we do not have a choice in making making whether this write back happens or not because in the stack operation you want the stack pointer to point to the next ok otherwise we will be over writing on the same things that we have pushed earlier. So, it should get decremented as we push and then it should get incremented as we pop ok that is what happens. So, so register list let us go back here register list has 0 to 7 that means, if you are pushing a value from R 0 this bit will be set you are also pushing R 1 this will be set suppose only R 3 6 4 this bit will be set. So, so we can give an option of which are the registers from R 7 to R 7 could be pushed into the stack or pop from the stack. Now, what happens to these other registers especially this R 14 is very important because when we are doing a branch with exchange the subroutine call it moves to some other location and then comes back to the next instruction which is below the branch link right or when you want to do a exception handler it goes to the exception handler and then it comes back from exception handler. So, the return address where it is supposed to come back is always kept in R 14. So, there is a requirement that this R 14 value is also need to be saved into the stack to avoid over writing of this R 14 by some other branch instruction or some other exception. So, moving R 14 into stack is a must ok some occasions. So, that option should be there just because it will top set and we say that only R 0 to R 7 could be saved into a stack then we have a problem in supporting the exception handling in the thumb state. That means, in the thumb state exception should be recognized and then it will go to arm state and then exception will be handled, but we should be able to respond to exception and come back from exception. That means, the link register is a very critical piece of value which needs to be preserved you know ifwe want the return value to be untouched. So, R 14 we should have some means of pushing the R 14 value into the stack that is why there is a selective bit provided for that ok. So, ok now you may wonder how do I use it. So, I will show you an example. So, push if you have and then you have a register list then you can say R 0, R 1 or whatever R 4 comma when you are pushing you can say that I want to push the value of R 14 also into the stack and then when we are popping it we have to say this R 14 has to come back to PC. So, same register sets you write R 0 to R 4 R 0 to R 4 you know it is R 0 comma R 4. So, I will say that and then I will say PC. That means, what the value which was stored in the stack which happens to be the R 14 content now comes to a PC. That means, that is the return address where the processor should come back to. So, when we are pushing we can mention that as a PC and when we are sorry when you are when you are popping out value we can mention it as a PC and when you are pushing it we can mention a R 14. So, these two though they happen to be the higher part of the register set ok, we said low and high ok, but we could use R 14 while pushing and then R 15 while popping the value. So, only these two registers are allowed ok, you cannot write the reverse because during the load and store this bits will be once you mention this register it will set this bit ok over encoding and the processor automatically assume if it is a push operation it will because it will know that whether push or pop based on the load and store and then it will know whether one more register is mentioned it will assume it will be R 14 while pushing and then it will assume that it is a PC while popping the value ok. I hope this you understood this is very important piece of information ok. So, optional storing of R 14 a link register along with lower registers mention in the list on push and then R ok restoring the value which was loaded from R 14 ok into R 15 ok that is you cannot write while restoring back there is a pop operation we cannot write R 14 we have to say it is you want to pop into PC only ok. May be assembler will give an error if you do that ok fine. Now, I am giving you the details how to use it ok this is the syntax of the push and pop operation. So, we have to have just a flower bracket with the values ok this is the syntax. Now you see the bit which are chosen when we have L R this bit is set ok and then when we have PC this bit is set push or pop whether load or store is chosen based on this ok and then automatically inside that who does this conversion if you recall the decompressor ok decompressor inside the decode logic of the processor ok this is a decode logic decode stage of the processor this is fetch and then execute. So, during this decode stage this instruction what we gave as a thumb state instruction like this push let us converted into this internally and then from here onwards this is typical ARM instruction and then with this syntax. So, now you see R 13 is assumed everywhere and then write back is also assumed everywhere with the stack operation we will not do without a write back right. So, and then R list is just copied from here to this. Now what happens this R list will have a mention of value from R 7 to R 0 it is just expanded here ok. So, this instruction allows from R 6 15 to R 0 in ARM mode ARM state only these values will berestored and then rest of it will be 0 ok that is the way sorry the conversion happens ok. So, push will be changed to and then STM DB. So, decrement before ok decrement before and increment after after. So, this is the see full decrement you saw that that is a stack operation ok LD we could do that, but when we are have using the LDM we can this is the format could be used ok. If you recall the ARM ARM state we had a instruction to stack operation and then the load store operations will have this different combinations right. So, always in the push operation it thinks that it is decrement before that means, what it is a full it is pointing at the full load content and then decrement it before you store the value. So, that means, what it is not in it is not going to over it on the location where currently the stack pointer is pointing at it will decrement before pushing the value into it that is are storing the value into the stack. Similarly, when it is popping out it will increment after that means, it will take out this value and then increment it ok. So, these two I have explained in detail in the you know in the session where we talk about stack operation. So, so while storing decrement before while loading the value it is a increment after and this is understandable and you see here only R 15 could be there R 14 is there. See we are not here we are mentioning that and that is getting implicitly transferred here. So, it is communicating that information by setting this bit ok to the processor. So, you have to have only these values in here. So, I have explained you that reason why this is required ok, when you want to save the written address and then representing the stack we need this. So, ARM state has allowed only mentioning the additional high register only these registers can be used in this instruction. So, this instruction ok now I am not going to go into the details of instruction cycle times for the thumb state because it is identical to that of equivalent ARM instruction. So, if suppose you want to know what is the number of sequential cycle number of non sequential cycle or internal cycle ok. If you know the value of this ok whatever is the cycle the same thing is going to be for this can you reason it out think over why is it same as the equivalent ARM instruction. If you recall the instruction cycle times ok instruction cycle time is calculated based on how much of time that instruction spends in the execute stage. If you remember that that was the definition of instruction cycle time. Now I just now explain to you after the decompressor the ARM instruction is what is generated from the decode stage equivalent from thumb state to ARM state and then that is what is getting executed. So, do you see any difference between a push or a pop between the time taken for push and pop with the equivalent ARM instruction you would not see the difference because this only is converted into ARM state and this executed here and our calculation of instruction cycle time is based on the time it spends in the execution stage. So, it is as good as executing this ARM instruction EQ and ARM instruction that is why this this can be reason it out ok you can reason it out why it is same as this because once this is converted ARM in the execution stage it does not even know whether it is executing this or not though it it can make out from the CPSR value, but what I am saying is from the hardware perspective it is same as executing this instruction. So, it will take the same exhibition time as the a equivalent ARM instruction. So, good now let us see an example now suppose if you have this what does it do R 0 to R 4. So, all the 5 digits are same as along with L R and this is what it assumes ok and then similarly this is what is assumed in certainly and then it is restoring the values. See the above instruction can be used to store the working register ok suppose you want to use this registers in your subroutine or something then you can save them and then start using them and then return address you can restore it from R 14 ok. So, it was saved by the BL instruction and you want to call one more subroutine then we should save the previous return address otherwise it will be large. So, that needs to be saved in the stack and then restored before it comes back to the recursive you know suppose you want to call a call a function from this function one more function is called and this function is calling one more function. A function call is same as a jump branch with link register to a some label which is the sorting of the function. So, this is F 1 ok let me explain this ones ok recall suppose this is what you want to do into your code and then after this you want to come back here and then you want to come back here how do you do it. So, suppose functions are written this is a code F 1 is starting here ok and F 2 is starting here from this location to this location ok and F 3 a function another function which is starting from this to this location now currently the code is somewhere here ok. Now you say BL ok to F 2 sorry suppose you know we I am calling it as F 1 is calling this F 2 right. So, let us assume that the code is here ok and then it is calling branch to F 2 ok BL 5 2 what happens this from this particular place it goes to this function call. Now R 14 here would have had the value which is next to this address assume it is something ok some address you know 108 something ok. So, that value is written into 108 ok R 14 is having right now. Now in this function you are calling one mode BL ok BL to F 3 what happens from this location it will jump to F 1 F 3. Now what happens this also saves in F R 14 the value because it is in you know we are always assuming this is a lower address and this is a higher address ok. Assume that this is some 206 ok please remember it is in some states. So, I can write as 6 here instead 2 byte boundaries ok core also can be 16 bits ok whereas, in arm state I cannot write 206 right it is not a 4 byte boundary address. So, assume R 14 is 206 what does it mean after calling this F 3 it is supposed to come back to this address which is 206. Now what happens this R 14 if it was not saved in the stack it is overwritten now with this address. So, when you return from here you say that you knowyou save R 14 value into PC then what happens it comes the control comes here, but you cannot now bring the control back to F 1 because we do not have a previous address which was written in the R 14. BL automatically saves that value in R 14, but it does not know whether one more BL is called or not. So, this R 14 will be not if we do not preserve it in the stack that is why I am saying the reason for preserving the R 14 value in the stack is to if you want to have a function calling another function and we want to return back to the original caller. So, what happens if suppose you have saved this R 14 into the stack then this would not have overwritten that value. So, you can after you come back from here we can save it restore that value from the stack here and then call another copy that R 14 into PC ok move back to the original caller. So, this kind of a function calling is possible only when we save the R 14 into the stack that is the reason the arm state also has to support this particular saving of this into stack ok. Otherwise come state we will not be able to call functions inside a function or exception between a network set good. So, I hope this is clear to you if you do not this is very critical point of you know thing understanding. So, please pay attention to this. So, this is how BL is used to save the value in R 14 and then restore it from PC. So, POP can be executed from the return from a function call to calling ok. So, note that while loading the R 14 value it is moved into R 15 to transfer control back to the calling. So, while loading the value of R 14 is there in the stack and the same thing which was copied from R 14 is restored into R 15 ok. I have explained this in the previous lectures also that I thought I will stress on this point again because you may wonder why is it there in arm state because they want to support the calling of functions from inside a another function. Now I will show you some conditional branch instruction ok in term state again remember this is the system of 16 bit value and the offset value is restricted to only 8 bit because of the tie you know number of bits that you have is reduced now. Now there is a conditional flag if you recall in the arm state ok the conditional flags were always at the high end of the instruction it is user 31 and this 0. So, this high 4 bits right they were having the CZNV ok it is not CZNV it is a that value that EQ or NE you know those are the conditional things based on this the CPSR CZNV was looked at and then the particular instruction will be either executed or dropped based on this what is the condition you have mentioned. If you recall add EQ ok could have had some value here and then this instruction will be executed only when 0 flag is set ok it will check this 0 flag in CPSR and then decide whether to execute or not. If you recall arm state it supports but thumb state does not support this conditional execution for all instruction ok only except for branch conditional branch instruction this conditional execution is not supported in thumb state why because there is no space for storing this conditional you know EQ or whatever no 16 you know conditions are not possible to be stored in the 16 bit of encoding we have, but conditional branch is required. So, if they have introduced that particular conditional execution of branch instruction here. So, these are the 4 bits which are used for that purpose and then based on the conditionalstatement here whether EQ or whatever is mentioned in the instruction the corresponding flags will be verified and then based on that the instruction will be executed or that means, the branching will happen or it will not happen now one more important difference you should remember. If you recall in arm state ok whatever is the PC value when the current instruction is executing will be PC plus 8 is not it if you recall that is what we were been told so far. Because the 3 stages of the pipeline the instruction will be 4 bytes down the line it will be accessing it right that is why 4 plus 4 that is why 8 bytes ahead of the current instruction which is getting executed. Whereas in thumb state the the scenario is different because it is going 2 bytes at a time ok because it is all 16 bit byte instruction here 32 bits byte instruction. So, if suppose this is 100 the next instruction will be 102 and the other one will be 104. So, the PC value will be this is plus 2 and another plus 2 so, 4 bytes ahead of the current instruction. So, this offset value is computed assuming the PC is 4 bytes ahead ok and what is the offset value stored here it is a 2 byte address 2 byte aligned address. So, we can you know leave off the lower LSB bit of the offset because it is always anyway 2 byte bound bit. So, effectively this could be shifted to left by 1 bit and then this 0 can be added here because this is anyway always 0 in a thumb state earlier if you if you recall an arm state it was shifting it by 2 bits because lower 2 bits of the address are where always 0 in the arm state. So, that is the difference. So, it will be shifted by 1 bit ok. So, effectively we are getting a 9 bit offset ok and then it has to be sign extended because sign this is a signed offset because we need to provide a support for either higher suppose if I am showing the higher address is toward this side plus we have to show for going into the higher address and minus we have to give offset to go into the lower address if suppose I am writing the address in the this order ok. So, that is the reason 4 bytes. So, these are the typical examples of how do you write a branch instruction in the thumb assembler ok and then these are the equivalent conditional flats which go into this 4 bit go location and then equivalent arm will be this. So, you would not see the difference between these two because internally it will be expanded into the 16 bit a particular bit instruction that is all and the function is the same and the offset will be expanded because originally in arm state it is a 12 bit offset whereas, here it is 8 bit offset. So, it will be sign extended to 12 bit and stored in the arm instruction ok and stored at arm before going to 8 bit state. So, let us see an example this please remember this is a code 16 is assumed why these are all thumb instructions ok thumb state instruction is already in the thumb state. So, we are saying that you know some compare with some value constant 45 and then if it is greater r 0 is greater than 45 go to this place. So, this will be here thumb state. So, it will move there ok it is half word aligned because 2 byte boundary ok that is all while the label specifies a 9 bit 2s complement address this was always be half word aligned. So, originally it is a 9 bit offset which is written into a instruction as a 8 bit offset because it can always left shift it by 1 bit because the lower bit is always is 0. So, here bit 0 is always set to 0. So, it will do a arithmetic shift line ok ok while performing ok 8 bit value ok sorry 9 bit value offset value to be stored in inside the instruction as 8 bit ok. So, originally it was originally you will know that it will be 0 some offset is there if it is negative it will be 1 and then some value bits are there 9 bits are there it needs to be stored as a 8 bit offset in the instruction. So, it has to do a ASR because this sign bit has to be preserved ok it is a sign arithmetic. So, it will be shifted into 8 bit the lower 0 will go off and then the remaining 8 bit will be stored in the instruction that is what I am showing it here ok. And these two combinations are not valid here ok that is how they have defined it ok you cannot have a always when you have either you do not mention anything or you say data 10 or some other very good. So, let me quickly cover thecompense section set summary okad with carry have a lower registers only it will use there is no high registersonly some instructions of as will allowhigh registers to be mentioned. So, please remember whenever it is allowing a high registers not typically it will be R 14 and R 15 which are assumed based on the particular context of the instruction ok. So, rest of the other registers are not normally allowed ok because you know that internally the instructions are decoded as a 3 bit registers are decoded as a 3 bit value. So, there is no possibility of storing a 4 bit value of other registers. So, some instructions assume a standard R 14 or R 15 typical example will be a push and pop ok. So, I want you to go through all the instructions in the thumb state and then see the differences of all of them between arm and thumb ok that is an exercise as anassembly as an assignment ok. So, I am not going to go into the details of this this and only just giving you where each of the registers now instructions support a typical height. If you see it is allowed here in move because we want the R 14 to be R 15 to be used in the instructions ok then wherever we want a return from effectively we want to use the stack value of R 14 or R 15 to be used. So, move oreven the previous branch or compare may use this I higher registers as a one of the operands ok and then this all the instructions one more a minor difference is I mentioned it all this R O R and then O R R it is all barrel shifter operation which happened to be part of the instruction earlier in the arm state whereas, they are all separate instructions in the thumb state that is under difference we should be aware of ok. So, that is it we have done with the thumb state instructions ok. Now, we are moving into a exceptions and associated modes though I have touched upon this earlier I am using this particularsession to just brush up what we learnt in the earlier earlier discussion. So, that you will be ready for understanding the implementation of exception handlers ok. So, I want you to pay attention to this and if you have any doubts or clarification you need refer the arm document or refer to this lecture again. So, that you are familiarized with this particular modes and how exceptions are handled because I have mentioned it in so many occasions. So, that you you get this idea because when we see actual implementation this background this knowledge is a must ok. This these are all the different exceptions ok all of you are by now aware of all this ok, but I am just showing you they are all mapping onto which modes ok. These are the different modes which have different bank registers please remember they all have some different bank registers, different set of registers are bad ok. Now, see that couple of things map on to a single one ok, abort mode data abort and prefetch abort both map on to single abort mode. That means, what a single abort mode registers ok bank registers ok are used by both the data abort access prefetch abort. That means, when you are in data abort if you are knows or if you are in prefetch abort if you are you know servicing a data abort because prefetch abort is a lower priority compared to data abort high priority ok. So, if you are here and then you are servicing this then what happens is the same bank registers are used. So, we have to have some means of saving those values into their respective you know within the stack pointers ok within the stack. So, that when one abort is handling the other abort we do not may you know lose these values which were previously saved. Let me explain this once ok again the example is R 14 which is very very important ah ok. Now you see I will explain you this is the user code ok. Let us assume you are we are executing the arm is executing in the user mode suddenly one prefetch abort has happened ok prefetch abort has happened ok. Now it will come to the abort mode and it will start using this R 14 register and in this R 14 the return address ok where after this is ok ah this abort handler has been serviced it should come back and execute the same instruction because this instruction was not completed because of the prefetch abort. So, it came here to the abort mode and then the automatically processor would have saved the return address that is this address in this place of R 14's R 14 of the abort mode bank register ok. Now and then remember that SPSR also of this mode has also been saved with the SPSR value here SPSR was there ok in the user mode which got saved into the SPSR of abort mode. Now assume when we are in this handling this prefetch abort ok this is a prefetch abort a data abort happens ok. So, what happens it will go to data abort handler ok. So, now data abort handler also uses the same abort mode because you see that prefetch abort also map onto the same mode abort mode. That means, they will also use the same mode register same SPSR same R 14 same R 13 these are the registers which are banked. So, now what happens when this abort is recognized and then it goes to the abort handler it has to save currently what it is being doing. So, it is executing the prefetch abort handler and then what will happen this will be over written with the new written address that that means, suppose prefetch abort was here and then during that handling of this instruction the data abort has happened because it was trying to access something in memory and then which has resulted in the abort. So, it comes here now this address has to be come executed it has to be saved. So, now what will happen this will be over written this address which was earlier saved is over written by this address. Now we cannot come back at all the R processor cannot come back here. So, what is the what is that need to be done in the prefetch abort handler we need to save this R 14 and R 13 into the stack pointer into the stack. So, stack is growing downward. So, it will be saved here and then now new abort happens this can be over written no issues because anyway we have saved these values in the stack. So, after performing this data abort we can always come back and then restore it from the stack and then come back here ok. So, this is what is a a sequence of abort happening might overwrite this register. So, which needs to be saved ok this way I will be explaining in the handler class in the next maybe in next session, but I just want to tell you you should understand this particular thing in your mind you can you know if you do not follow this please read up more have clarity on this. And similarly, this this supervisor mode has the both SWI instruction as well as reset brings it here ok. So, anyway after reset we do not have to come back at all no problem, but SWI can have a one SWI ok may call another SWI inside you may write the code like that. In that case what will happen the same bank registers of the supervisor will be used. So, we have to save it in the stack and ok that is why we need to have a stack for each mode ok please remember ok. I will explain you a sample code here in this session. So, that you understand that the need for a stack because stack is going to keep the registers which are likely to be over written in the stack. So, that you are not losing those values and then the programmer as a handler writer we should remember to pop it out where whatever we are pushing the stack. Please remember stack is always not going to be over written as long as it is you have a sufficient space in the stack we can always read back the value that we are pushing the stack that is why we want stack in each mode. So, that a recursive function call or a handler calling another handler you know about one about you know during the one about being handled another about handlingcoming coming up all these things can be managed if we have a values saved in stack. So, each of the above modes have its own bank registers all the above modes are privileged modes ok they are all privileged mode. What I mean by privileged mode? In the privileged mode you had a write access to the mode bits of PPSR. That means, when we are in a system mode we can you know write into mode bit to go into any other different mode ok I will explain you with the code. So, but you cannot do that in a user mode once we are in user mode we cannot write into the mode bits of PPSR effectively we will not be able to change over to any other mode ok. So, only system mode we will be able to do it that is why on reset the process that comes up in system mode ok it is a you know sorry it is a supervisor both the supervisor mode ok. So, supervisor mode also has a I will explain about the system mode separately supervisor mode has the it is a privileged mode. So, you will be able to write into the mode bit. So, when on reset when we enter the supervisor mode the OS will take a control ok typically on reset the initialization code of our embedded processor or if you are using a OS that OS will come into action first. So, the OS will decide where the stack needs to be for each of the mode ok and then they write into the R 13 of each of the mode because R 13 is the stack pointer right default. So, those registers are used to point to different stacks. So, that when we come to user mode after that if IRQ happen to interrupt happens or FAQ happens or any other about happen we have the stack already initialized ok. So, we can save the values into those stack if like I mentioned previously. So, that we can get back those values later on. So, user mode does not have right membership to the mode bits ok. Now, I am just recalling you know the you know bank registers please remember the fast interrupt has some more bank registers. That means, what these registers are masked ok by this set of registers. So, we can always we do not have to bother about saving them in the past interrupt request handler because they are masked by its own registers. So, we can use them without any problem we do not have to worry that whether user mode registers have been overwritten or not. Similarly, in this cases we we have our own mode registers sorry the individual bank registers. So, we it will be used for individual modes in the in the individual mode for its own purpose. And then SPSR is to save the CPSR value here ok. So, please keep this in mind always when we talk about what you have to remember that when the processor enters from user mode to this or from maybe you know it is in you know prefetch of what it is handling and then it is supposed to come back to you a past interrupt the time past interrupt happens and it comes here then this will be more it will not be accessed. Now, it will come this registers will become active. So, whichever mode the processor is in those mode registers that registers become active automatically and then the balance user mode registers become active. That means, they are visible always. In this case only this will be visible and this this is shadowed in the past interrupt whereas, in other cases up to this point the user mode registers are visible. That means, your whatever value is here you will be seeing it here also and here also. Unless you save them you cannot use it in this handler because you will be overwriting what the user has kept it there you may not even know whether user has used these registers or not. So, handlers need to always assume that these registers are used by somebody else. So, whenever we are trying to use this register in the handler we need to save them ok as a programmer writing the handler routines ok. So, you have to have a clear idea of all this ok. The system mode is little bit different from other mode. So, I thought I will explain you see if you see here user and the system modes use the same set of registers ok. They have a you know view of the same set of registers then you may wonder what is the difference that is what I am going to tell you in the next section ok. All the modes except user mode can change the processor mode bit ok by writing directly into the mode bits of CPSR whereas, user mode you cannot touch the mode bit. Now, if the system mode what is the user mode all processor mode except system mode have a set of associated bank register what I mean by that C let me go back except for the system mode all other modes have a set of some bank registers right whereas, system mode do not have does not have any bank register it has the same user mode registers visible to it in the system mode. Now, you may wonder what is the difference that, but even the user mode and system mode the difference is system mode has the same set of user mode register, but it can also change the mode bits in CPSR whereas, user mode cannot do that. So, that is the major difference between a system mode and the user mode though they have the same set of registers visible to them and system mode does not have any bank register, but it can change the mode bits ok. It has got some right permission to the CPSR that means, what in system mode processor it it can change the mode bit to get into any of the different mode IRQ mode or FIQ mode any mode. So, that is why OS is residing in system mode whereas, user code will be in the user mode ok. So, that means, what user cannot change the mode whereas, as a OS code running in system mode can change the mode bit ok that is the major difference. System mode cannot enter cannot be entered by an exception another difference in system mode is it cannot be entered through an exception what I mean by that suppose you know that pre fetch abort happens it will get a it will go into abort mode. If data abort happens it will go to abort mode if external IRQ interrupt happens it will get into IRQ mode correct and if FIQ interrupt is happening from the external system FI it will enter FIQ mode. So, we can enter through different you know SWI that is why executing SWI instruction it will go to super user mode. So, we have different means of entering into these modes whereas, system mode cannot be entered through any of these external thing only varies by changing the CPSR value ok. So, there is a separate mode bit the 5 bit values 0 to 4 correct 5 bits in the CPSR is reserved for the mode bit by changing some value which is equivalent to some system mode we can go into the system mode by not by any other mean that is what I am saying ok. So, corruption of link register. So, this I have already told you in case if you want the you know registers to be preserved the system handlers what they do is they move to system mode ok. That means, abort handler is there ok I explained you some way that if suppose you want doing the data abort mode you know prefetch abort mode if you want a data abort to be handled the one way of doing it is you save this register and then you come to system mode and work on it ok. What is the say why we are thinking that system mode is safer to execute because through different external event we cannot get into the system mode only by changing mode bits we can get into system mode. So, this is little bit safer ok ok, but at the same time any other handler can also come into system mode by changing the mode bits because all the previous modes have the right to change the mode bits. So, system mode is used for handling a higher value you know if suppose you want to execute more amount of information you know more amount of code then the abort handler normally come to system mode ok. I will do not want to explain so much in here you may not understand it. Now, we will go to the when we come to the next session we will have a more detailed discussion on this ok. Only remember that system mode is also used by other handlers to come into system mode to execute it because we allowby changing the mode bit we can always allow any other mode to come to system mode and use the user mode registers freely ok, but we need to save them in the stack before using them ok that is very important ok of course, very good. So, system mode cannot can can run task that is a privilege that is a. So, because I told you that system mode has the right permission to CPSR ok good exception handlers typically an application runs in user mode, but handling exception that way privilege mode and we have already you know talked about this in detail earlier also. Whenever exception mode it enters it will it will get its own stack pointer its own you know link register its own SPSR and FYQ will get more bank registers that I extend you in detail by showing the bank registers ok. These are all we are talking about bank registers here ok nothing new. Each exception handler must ensure that other registers are restored if used by handlers I told you that also. If suppose you are using any other registers apart from what we have in bank registers that needs to be saved otherwise it will be overwriting on the previous value. It can be saved it can be done by saving the contents of any registers into the stack on its own stack ok and then restoring back while returning them. Now I will explain you what I mean by own stack. Before that let us just see that how different processor how processor responds to exception. So, it saves the CPSR into SPSR of the mode and if it is in some state it moves to arm state because exception can be handled only in arm state and then it changes the CPSR CPSR modes to the mode it is going. Suppose IRQ mode it is jumping because of interrupt it will change the CPSR to IRQ mode because it has already saved the previous value in the SPSR it can happily say change the value. And then I I explain this also that whenever it goes into some register IRQ is always disabled whenever it enters any other abort mode ok IRQ interrupts are disabled always whereas, FIQ is not touched unchanged except for when it is getting into FIQ mode it is disabled ok. So, this is why is it then because one interrupt calling I know when it is handling one interrupt I this does not want to be interpreted by the same interrupt. So, IRQ is disabled always and FIQ is disabled only when it is servicing FIQ interrupt because FIQ has a higher priority than IRQ. And then it also sets the appropriate link registers with a return value ok and the PC to the vector address this is anyway it is jumping to the exception handler by going to the particular PC address ok. So, now that is the way it is responding to the ARM processor is responding to the any exception. Now, I told you that we need to have a stack for each of the mode ok how can it be set up I am giving an example ok. Now, these are the bank registers these are the R13 registers of each bank ok they need to be initialized with the different values ok. That means, what different locations in the memory are used memory are used for each of the stack because we cannot have all the stack point into the same location otherwise we know every mode will be writing the same location we will get a we will not be able to save the values. So, they need to be saved in different stack. So, before any of the mode are enabled or IRQ or FIQ is enabled this stack pointers need to be initialized this is one of the job of the reset handler ok. On reset these are the teams of each mode should be used with the different values so that they have a different stack otherwise the user handler should be aware of it ok the stack or save they are all pointing to the same stack which is very complex in implementation as well as it is very difficult to debug also if your code is not running or your application is crashing ok. So, each mode having different ok friends. So, we we have different mode bank registers with a different registers R13 pointing to each by each mode ok. So, these are the teams are easily used for stack. So, whenever you do something you want to write into the stack then we will be using the R13 to push the value right. So, now we need to make sure the stack when we are pushing it is decremented and then values push into that that means the stack is growing. So, in a different different modes suppose different handlers may be there different IRQ or FAQ may happen and each of them may be using the stack it may be pushing some value values into the stack. So, they cannot be pointing into the same location in the memory in that case what will happen all of them will be pushing into the same stack then restoring will be you have to be handled properly and then we also make make sure that if suppose there is a problem in thisprogram debugging would be very difficult because each mode every mode is using the same stack. So, to avoid that each of the stack registers R13 can be initialized with the different addresses ok allocating some space a sufficient space space in the stack. So, ok suppose if you think particular IRQ mode you you are you need only 10 k bytes of stack then you have to make sure that the handlers in the IRQ mode do not push so much into the stack beyond 10 k if it is thus so, then there is no direct hardware implementation of checking whether this is exceeding the stack. So, what will happen if IRQ is exceeding it will get into FAQ stack and then start adopting this stack. So, different stack supports easy to manage so that you know we have a different memory allocated for each of the stack and the same thing we have to also make sure that the stack does not overflow into the next location ok. So, so before enabling this any of this interrupts or any of this mode we should come and then make sure that this R13 of the registers are all initialized with the proper values ok because on reset they are all having a different and and different values. So, we do not know what it is having so, we have to initialize them. So, that is the job of the reset handler ok ok. Let us see each of the exception modes have their own stack and then initialize by the reset handler ok. I will show you an example code and we will we will end this session today. So, these are the different ways the in memory can be mapped ok. So, you with the you know you use of linker we will be able to reserve different spaces in the memory and then initialize the relevant registers ok if it is a stack space any initialize the different registers of different modes. So, that we have those initialized values so, that those memory locations can be used. Suppose if we say that this is the location we are reserving for IRQ stack and this is the location we are using for SVC stack then the R13 of that particular mode should be initialized with this value first because once this is the starting address it will be anyway growing downwards ok. Let make sure that it grows always downwards. So, in that case we can always use as long as it is used within this limit it is fine that is the how the memory has to be handled ok to manage the different handlers different modes of the processor. Now, how do we set up the stack ok I am giving a sample code here this dot EQ you may not be able to see the from distance it is dot ok EQ that is the syntax used by the our ARM SIM that we use for ourlecture here. So, what we are saying is it is equal to hash dependent C this much of this much value that means, we are saying that this much of stack is required for IRQ this much of space is required for the effective stack. Now, these are the different mode bits which are defined by the ARM processor ok. These are the lower 5 bits need to be this if you want to enter into these modes then what is this mode mark this is a lower 1 you know 5 bit value ok that is all 1 F is stored and then you remember dot that is a starting of the dot dot data segment because the stack is a read write segment right it needs to be read write we cannot have a ROM map to the stack because ROM is only read only. So, it has to be a data segment where stack is pushing into it that means, it is writing into it and then when it is popping it is reading from the stack. So, stack location is a read write location it is similar to a data location right that is why we have to choose a data segment with a read write permission and then this dot skip gives a indication to the you know linker that this much of space needs to be this you know reserved for it. So, it cannot use this this location whatever is the starting address wherever it is starting up this segment in the memory ok it may decide to start from some location then from that type place onwards the 0 x 8 should be reserved for 8 k should be used for IRQ. So, it cannot allocate the same location for may be another FIQ stack or some other data segment or some variable. So, it is an instruction to the in linker to reserve the space for this particular usage ok, but this is not enough if you say IRQ stack processor does not know that it is used for IRQ we have to initialize the R 13 of the IRQ mode ok that should be initialized with this value then only actually the processor will know that ok I can use this particular space for my IRQ handling ok. So, this needs to be done by whom by the reset handler that is what I am going to show you that piece of code ok assume that the currently the mode is system mode why I am assuming this is in system mode only in system mode or some other privilege mode we have a option to access the CPSR mode registers ok. Otherwise we will not be able to write into the mode register if you cannot be in a user mode and try to execute this code it will not work ok it needs to be in the system mode or a supervisor mode where you have a write permission to the CPSR the mode bit values you can write into the CPSR. Now let me ok do one thing let us not continue here I want you to spend some 10 minutes ok I hope that will be sufficient to understand this code before I start with the explanation that I want you where I explained you what it is I explained you what are this now you should be able to understand what is happening in this code. I am telling you this is done prior to enabling any interrupt and it is in system mode maybe you can assume it is a reset handler now this background is enough for you to know what is happening here because you are all now experts in understanding the ARM instructions hopefully right. So, please do that I am sure you will be able to understand ok take a 10 minutes break ok friends I hope you had a good understanding of this particular code let us see ok I will explain it now what is happening here we are just copying the value current CPSR value into R 0 ok and then this is what it will use this value mode mask which happens to be a 1 F it will invert it when it inverse this 1 F what will happen the lower 5 bits will become 0 ok lower 5 bits and the remaining bits out of 32 will be all once ok and that will be and with ok big and ok it will do a and operation after this inversion with R 0 whatever may be the value of R 0 which was copied from CPSR ok now what happens assume CPSR was having something ok some bits conditional this was there and then some interrupts were there and then lower 5 bits were there. So, we want to preserve the lower bits ok we want to preserve whatever may be the previous value we want to not to touch it we are interested in only in this 5 bit value to be changed ok 5 bits. So, by anding this CPSR value which is now moving to R 0 what happens this all this thing will be untouched ok when you and it with now this is the R 0 value which has come from CPSR now we want to and it with all once followed by 5 zeros when you do this this force believe this bits will be in R 0 will be made 0 and rest of the bit will be untouched you agree ok. Please remember we are just doing it with the R 0 only not with the actual CPSR which happens to be here CPSR we are copied into R 0 and then modifying the CPSR value only modifying the lower 5 bits to 0 ok now that is what is done by this instruction. Now, what are we trying to do here IRQ mode we are Ring it now the R 0 previous content R 0 is R with this bit this bits anyway it is a low 5 bit value only ok. So, one of the modes may be we are picking up the IRQ mode 0 x 1 2 that we are Ring it with now what happens we got in the R 0 ok R 0 was up to 5 bit ok it is same as what was there in the CPSR originally you agree ok this are conditional facts are here and then rest of it is anyway unused, but this lower 5 bits now becomes IRQ mode ok, but still the processor is not in IRQ mode why because CPSR has not changed. So, only R 0 is changed that does not mean that CPSR you know the processor will move to IRQ mode. So, it will it is continue to be in system mode up to this point please remember up to this point the processor is in system mode let me erase. Now, here we are writing into the CPSR what value we are writing into the CPSR by changing only the lower 5 bit to IRQ mode now what happens this process where now up to the at this point after this instruction it is in IRQ mode what I mean by IRQ mode suddenly if you say the processor is in IRQ mode all those it matter what does it actually what you should keep in back of your mind you have to remember in the back of the mind the bank registers are visible now which is meant for IRQ mode which are the registers R R 14 ok let me write it in the order R 13 and SPSR they are all visible now ok. This particular R 13 is visible not what was there in system mode because I told you system mode uses the same user mode registers it was having CPSR right. Please remember this register has become visible now ok, but this is also there, but this R 13 and R 14 are not visible which happens to be in the system mode or user mode register this is masked by this register. So, when we in this instruction we use R 13 we are actually writing into this register not the R 13 which is here ok R 15 is here. So, I have not shown this R 15 is here which happens to be same we are not writing into this register we are writing into this IRQ bank register R 13 that is what you should remember and please remember it is we are not going to write R 13 underscore ABT or IRQ all those things ok it is assemblers may not accept that you have to say R 13 only, but we should remember in the back of the mind this R 13 now corresponds to the IRQ mode because we change the IRQ mode here by writing into the CPSR. This instruction you know what is the C mean it is writes only the lower 8 bits ok lower 8 bits of the value lower 8 bits to CPSR only is modified this is not touched. So, when it is writing into it is actually we have changed this to IRQ mode 5 bits. So, it has moved into IRQ mode ok I hope this is clear to you. Now, what happens we are initializing it is the IRQ new stack whatever is the label which is starting here ok linker would have reserved some space we do not know ok. Once you see after the linking and all the done based on your you knowconfiguration you have given to IRQ it would have reserved some reserved some space for this. So, that address will be written into R 13. So, LDR is a load instruction you know that and then it is whatever the label correspond to which address it corresponds to that will be written into R 13 of the IRQ register IRQ bank register. Now, we are continuing here ok IRQ mode itself we are continuing we are copying the CPSR value into R 0 and then mode mask we are doing we are masking the mode and then with the same big instruction which I do not want to explain again. Now, FIQ mode is R with this. So, now, we are changing to FIQ mode once this is written into FI into CPSR C now the processor enters into FIQ mode. Now, what happens earlier it was in system mode ok and then it came to IRQ mode now it is come into FIQ mode. Now, FIQ mode has a 2 register right 13 R 13 and R 14 now these registers will become visible its own SPSR will be visible this will not be visible even this R 13 in the user mode will not be visible. Now, when we write into R 13 we are writing the this particular physical register which happens to be for the FIQ mode we are initializing it. So, like this from the system mode we can move any other mode by changing the CPSR value because CPSR is visible in all the modes ok. Though SPSR is coming into each mode ok, CPSR is also visible remember that only this these are the bank register which are now masking this, but this is visible. So, we can always write into CPSR and move to another mode and then write the new value. So, this is how here the stack of different mode are initialized. So, please try out this particular you know instructions in your with the simulator because you can use the simulator for this please try out and learn how it happens. So, what how can you verify it is using different registers what you do you do this you modify the R 13 value here right you now change it to system mode ok. Now, you will see that R 13 is having some different value not this value what you have loaded then come back to the system now effective mode you will see this again go back you will see this or go back IRQ mode you will see this value. So, you will be really understanding it by seeing in in the simulator ok then you will understand how the bank registers function please do this as a part of the lab exercise exercise ok. So, I am just explaining this it is common for a user mode stack to be initialized at the end why ok after doing all that initialization user mode stack has to be initialized it can be done only at the end because once you come to user mode ok there is no way to go back to other modes ok because user mode does not allow CPSR mode which to be changed. So, you are locked on. So, you can only execute software interrupt or some other exception needs to happen for you to move to other mode. So, from reset from before coming to reset user mode all the stack pointers should be initialized then last user mode you know you change over to user mode in the reset handler and then change this R 13 because R 13 of this user mode should also be initialized. So, that it points to different user mode stack ok. So, otherwise you force the processor into system mode to set up the user mode stack since both modes share the same register with that from the reset you can come to system mode ok and then R 13 of the user mode can be initialized because R 13 is shared among system mode and user mode and then come to user mode ok separate steps to each mode rather than using a single stack as a main advantage. What is advantage? Air and task can be debug and isolated from the rest of the system. So, suppose there was a bug in the pre pre pressure bot code ok because of that the stack is corrupted, but of data about our FIQ ok can have can function properly because these stacks are different and they are not corrupted ok. So, you can isolate the problem to a particular mode. So, that is the advantage of having different stack for different modes because safety reasons are always required to enable IRQ and FIQ only after their own stacks are initialized of course, it is a very valid it is not only safety reason it is it is a logical reason right. Without any using the initializing the R 13 of each mode if we enable the interrupt and if the interrupt happens it will assume that R 13 is already initialized, but it will be pointing to some random location and if you try to save anything into that you will get something out of it ok. You may have an abort because it may not be pointing to a valid memory. Please remember in your system a particular memory only will be valid not all the 32 you know 2432 addresses are valid in your system. So, we need to first initialize the you know R 13 of all the mode then only you should you know enable the interrupts . So, how do you assign interrupts? System designers can decide ok based on which hardware peripherals need to be connected to what. So, accordingly the they should be initialized they should be connected to the particular IRQ or FIQ ok. Standard arguments are various inputs are given below SWI are used for you know this is software interrupt is used for OS routine IRQ sorry used for different purposes like you know serial port or timer because IRQ is a physical interrupt input coming to the processor and FIQ is another interrupt which is a fast response. So, normally it is a single source is used because inside the handler we do not want to find out which interrupt source has come ok interrupt can happen because of multiple sources if you connect multiple sources to a controller and then the interrupt is generated. So, FIQ is always connected to one particular source. So, that the handler will always assume we will know that it is from the particular handler and it can serve the interrupt without any delay ok that is a normal convention. Handling of interrupts ok it is a time in ok interrupt latency you know that when a interrupt happens from the time it is generated to the first instruction which is executed in the handler is what is time elapsed between this is called time interrupt latency. So, based on the criticality of the source of the interrupt latency needs to be minimized. So, two goals are to be achieved by the system manager ok which one of the interrupts should be connected where and then how to minimize the interrupt latency ok ok. You need to handle the interrupts simultaneously at the same time you have to handle the latency also to be to be minimum. So, nested handling means suppose you allow one interrupt to IRQ handler it comes into IRQ handler and then inside that you enable IRQ it will again interrupt the processor and then one more handler will be called the same handler will be called and it will be serving that different source ok. So, when you want to have a nested interrupt the time taken will be more ok and then another way is you can write a priority among different sources that you are connecting to IRQ and then you can set them differently. So, do not worry about this particularI am just giving you a heads up here ok this will be discussed in detail in the next class ok. So, do not bother about this if you do not understand what I mean by nested interrupt priorities if you are if you already know well and good otherwise let us talk about it later ok. So, we are come to end of the class here today. So, we learnt about push and pop of thumb state we learnt about conditional branches and then summary of instruction please go through this all these instructions in the thumb state and this is the assignment ok assignment and then we talked about different exceptions and modes and then how to set up different stack ok. This is a particularly very very important if you have understood this then understanding the next class will be easier. If you do not understand this it will be tough please spend some time because this is a very important part part of the course if you follow this then only you will become a successful embedded engineer because you should be able to write your own handlers ok. It is not enough if you write user code then you will remain as a application developer, but if you want to become a system developer system engineer you need to know how to write handler how different bank registers are used how recent handlers are written these are all very important part. So, to become some application engineer to a system engineer we need to have an understanding of a good and a clear understanding of how different modes work and how different handlers are handled how interpreters interrupts are handled. So, understand this part of the course today tomorrow or maybe next session we will cover up the cover the interrupt handlers ok. Hope you had a good site you knowtime here I enjoyed sharing this information with you and see you in the next class all the very best with your lab sessions. Bye bye.