 Namaste, welcome to the session design of dimultipleisure tree. At the end of this session, students will be able to design a dimultipleisure tree. Now before proceeding further, we have already discussed dimultipleisure. So, take a pause here and recall what is dimultipleisure. So, multipleisure is also a combinational circuit which distributes a single input binary information to one of the 2 raised to n number of output lines using n number of selection or also known as control lines. Dimultipleisure are also known as data distributor because it distributes the same information to all of the output one by one. It has exactly reverse process of multipleisure. So, this is the block diagram of 1 is to n dimultipleisure where you can see there is a single data input line and 2 raised to n data output line whereas, we have n number of select lines which selects one of the output which is get connected to the input line and hence the data is get distributed among all of the outputs. Applications of dimultipleisure. Dimultipleisure are most widely used in communication field. So, along with multipleisure, dimultipleisure are both used in communication field. In serial to parallel data conversion to produce the parallel data from incoming serial data stream dimultipleisure are used. Dimultipleisure are also used to design combinational logic circuit which is very easy to design. Dimultipleisure are used in arithmetic and logical unit to store the data in multiple registers. Now, let us see design of multipleisure. So, let us have a example of 1 is to 4 dimultipleisure. So, very first step is to draw the block diagram. So, as we know that we have to design 1 is to 4 dimultipleisure, it means that we have single data input and 4 output lines. So, we have to find out how many select inputs are required. So, there is a formula 2 raised to m is equal to n where m select inputs are there and n number of data outputs. So, we know that in 1 is to 4 dimultipleisure, so n is 4 data outputs. So, we require 2 select inputs. So, m becomes 2. So, let us draw the block diagram. So, here input single input is there denoted as i and 4 outputs are denoted as y0, y1, y2, y3 and 2 select inputs are denoted as s1 and s0. So, in our truth table we include all these inputs along with outputs. So, i is a single input where it may be 0 or 1 or it may be stream of 0s and 1s. So, here we have select input s1 and s0. So, based on s1 and s0 combination we have 4 outputs. So, let us consider i may be 0 or 1. So, when s1 and s0 both are 0 0 then y0 is get selected and others are not selected. So, here input is get connected to the output y0. When we have s1 0 and s0 1 then again i may be 0 or 1. Now, this time y1 is get selected. So, input is get connected to y1 here when s1 is 1 and s0 is 0 then according to the truth table y2 output is get selected. So, here the input 0 or 1 is connected to the y2 output and when s1 and s0 both are 1 1 when input i may be 0 or 1 then it is get connected to y3. In the next step we are going to write logic equations for all the outputs of demultiplizer. So, here in 1s to 4 demultiplizer we have 4 outputs y3 y2 y1 y0. So, the equation here for y0 we are getting y0 when s1 and s0 are both 0 0 along with y. So, equation becomes y0 is equal to s1 bar s0 bar i then y1 we are getting y1 because when s1 is 0 and s0 is 1 along with i. So, y1 becomes s1 bar s0 i. Similarly, y2 equation having y2 is equal to s1 s0 bar i and y3 we are getting when s1 and s0 both are 1 1 along with i. So, y3 is equal to s1 s0 i. In the next step we are going to draw logic circuit for 1s to 4 demultiplizer. So, to draw logic circuit we require equations of output. So, based on these 4 equations so, 4 AND gates are giving 4 outputs as y3 y2 y1 y0. We have common single input data line that is i and s1 s0 are select lines. Now, let us discuss how to design demultiplizer tree. A larger demultiplizer can be implemented using a tree of smaller demultiplizers. So, let us have example here to construct 1s to 4 demultiplizer using 1s to t demultiplizer. So, here we require 2 numbers of 1s to 2 demultiplizer 2 select inputs. So, in 1s to 4 demultiplizer we have y0 y1 y2 y3 outputs and here we are considering d in as data input. So, this is the block diagram construction of 1s to 4 demultiplizer using 1s to 2 demultiplizer. So, this is the first 1s to 2 demultiplizer and this is the second 1s to 2 demultiplizer. So, each one of these demultiplizers giving 2 outputs. So, total we have 4 outputs, but these having individual input. So, there will be 2 inputs. So, these 2 inputs are combined together and made single input line denoted as d in. Then we are using s1 and s0 select inputs s1 is used as a enable input. So, one of the demultiplizer is get enable at a time. Then s0 is used to select one of the output of each of these 2 demultiplizer. Now, let us see how it works. Now, consider that input is already there, d in input is distributed to the d in input of both 1s to 2 demultiplizers. So, when s1 and s0 are 0, 0. So, this s1, 0 is converted to 1. So, whenever 1 input is given, the first demultiplizer is get enable and because of that second demultiplizer is get disabled as e2 having here 0. Then due to the s0 as it is 0, the first output of each of these demultiplizers are get selected as second demultiplizer is already disabled. So, the d in input is directly connected to the y0. So, in the second case when s1 is 0 and s0 is 1. So, in this case also, due to this s1, 0 the first demultiplizer is get enable and second demultiplizer is get disabled. So, as s0 is 1, but here first demultiplizer is enable. So, we are getting input connected d in to the y1. So, in the next case s1 is 1 and s0 is 0 due to this 1 as it is s1, it becomes 0 to e1. So, first demultiplizer is get disabled and due to this 1, the second demultiplizer is get enable. So, when s0 is 0, so in this way y2 is get selected and it is connected to input. When s1 and s0 are both 1, 1 then s1 is 1 which is enabling second demultiplizer and disabling first demultiplizer and when s0 is 1, it is selecting second output of second demultiplizer. So, hence the d in input is get connected to the y3. So, in this way demultiplizer tree works. Now, let us have example of 1 is to 16 demultiplizer using 1 is to 8 demultiplizer and 1 is to 2 demultiplizer. In this example the block diagram is. So, both demultiplizer will produce totally 16 outputs. So, that will fulfill our 16 output, but which are having single input. So, here 2 inputs are there which are connected to one more 1 is to 2 demultiplizer. So, there will be only 1 data input denoted as i. And we know that in 1 is to 16 demultiplizer we require 4 select inputs. So, out of 4 select inputs the first one is used in the 1 is to 2 demultiplizer and remaining 3 are commonly used for both 1 is to 8 demultiplizer. So, in this design we require 2 number of 1 is to 8 demultiplizer and 1 is to 2 demultiplizer. Here we also require 4 select inputs to select one of the 16 output. So, we have here y15 to y0 output and single data input denoted as i. So, in this way we can construct a larger demultiplizer using smaller demultiplizer which is known as demultiplizer tree. So, these are references. Thank you.