 Hello and welcome to this presentation of this DelayBlock module. The DelayBlock module integrated inside STM32H7 microcontrollers is used to tune the received data sampling clock for the SD, STIO, MMC card host interfaces or SDMMC and QuadSPI memory interface or QSPI. It is mandatory for use with SDMMC ultra high speed or UHSI interface cards having a variable delay. A wide input clock frequency range from 25 up to 208 MHz is supported. The delay on the output clock is controlled by the firmware and may require re-tuning due to voltage or temperature drift. Applications benefit from being able to support SDMMC UHSI cards having variable delay and easier integration of the high speed SDMMC and QSPI interfaces. In the STM32H7, a delay block is available with the SDMMC1, SDMMC2 and the QuadSPI modules. Located on the AHB bus, the DelayBlock module consists of an AHB interface containing the delay line control, feedback information and output clock selection registers with the delay line and output clock multiplexer parameter values. The DelayBlock module consists of 12 delay units with programmable unit delays. The delay line feedback information is used to tune the delay line to one period of the input clock. The output clock phase is selected by the phase selection register. Before selecting an output clock phase, the delay line must be tuned to span one input clock period. To do this, set the SEN bit to 1 to enable the delay length sampling. This will at the same time disable the output clock. Then set SEL 3 to 0 to 1100 to enable all delay units. Select the smallest unit delay by setting unit 6 to 0 to 0. Writing the register unit field will trigger the delay line sampling. Firmware must pull this bit before checking the delay line length feedback in LNG 11 to 0. When the LNG field is not 0 and either LNG bit 11 or bit 10 is 0, the delay line spans one input clock period and the delay line length tuning process is finished. Otherwise, the unit delay is increased and a new check is performed. When the maximum delay unit is reached and the check is still false, the input clock is too slow to fit one complete period in the delay line. Once the delay line is tuned, you can determine how many delay units span one input clock period. Starting from the LNG 11 to 0, most significant bit downwards, the first bit set to 1 determines the number of delay units that span one input clock period. Number of delay units equals bit index plus 1. That is, if the first LNG bit set to 1 is bit number 10, then 11 delay units 0 to 10 span one input clock period. To determine the eye diagram, all peripheral interface data must be received and verified for all selectable output clock phases. From this, a pattern with good and failing output clock phases will be obtained. Subsequently, the best phase among the good ones is selected. To select a new output clock phase, first set the SEN bit to 1 to disable the output clock. Once the output clock phase is selected via bit's SEL 3 to 0, the output clock can be re-enabled by resetting the SEN bit to 0. The SD specification provides a special tuning block to tune the received data sample point. Following a unit delay update in unit, the LNG F flag informs the firmware that the delay line sampling has finished, and the delay length feedback can be read from bit's LNG 11 to 0. Here is an overview of the peripheral status in specific low power configuration modes. The delay block module is not able to change state in sleep mode and lower. However, the input to output clock delay is functional down to and including stop mode. In standby mode, the delay block module is powered down. Here is a list of peripherals related to the delay block module. Users should be familiar with the relationships between these peripherals to correctly configure and use the delay block module.