 Once again, welcome to our advanced VLSI design course and we have been discussing right now about the power away design and essentially as I discussed earlier in my earlier two talks, I did say that the current need of every system is to have low power dissipations, a variety of uses particularly for the handheld or mobile systems, the power is low power is very, very important, but so is the power requirement for higher MIPS requirement of a normal microprocessor as well. So with this, that low power microprocessor will be required in variety of applications on field including, for example, wireless networks, wireless nodes. One is really worried about these days about the low power designs. So I continue with what I have said earlier discussed about generalities, then I will discuss about the power dissipation in a CMOS circuit. In particularly, we said there are three possible powers, one is due to the capacity of charging and discharging, the other is short circuit power which essentially also can be clubbed into switch power and then finally, we talked about the third one which is the most important worrying right now is the leakage power. Now if you see the two powers, switching power or the leakage power, what we observe now that both of these power are dependent on the power supply voltage VDD and therefore, switching power has square dependence of the, square dependence on the power, I mean switching power is proportional to VDD square, C VDD square F and therefore, VDD square is the term appearing in the dynamic power. So is this appear in the case of switching power that is the short circuit power. However, in the case of leakage power the since the power is nothing but I leakage current into VDD. So obviously, P leak is linearly proportional to VDD, but the fact about all this whether it is proportional to VDD or VDD square, if you want to reduce the power dissipation, one is it is quite obvious to us that we must reduce or we must scale down the power supply and as we scale down the power supply voltage, we can achieve the low power dissipation. There are number of ways in which power reduction can be done by voltage scaleings. The one of the technique shown here is gate delay. Please remember if I reduce the power supply voltage, we know that the gate delay TD increases. We also know this occurs because if the power supply voltage goes down, the charging and discharging current available for capacitor becomes smaller and since that becomes smaller, obviously the time taken to charge or discharge of the load capacitance will be larger. So if you reduce the power supply, then the speed of course is the something which you have to give up. So obviously, this is a figure which I have shown you here is essentially talking about delay versus power supply and one sees that if you have lower power, the delay starts rising and if you go have a lower than say around 1.5 volt or lower, the delay actually rises very, very sharply. Now this fact has to be understood that one cannot scale down power supply voltages so very easily because the speed is also one of the major criteria. However, there are circuits as I discussed earlier which are only called low power or low standby power circuits which actually are not really worried about the speeds they may be working on less than 500 megahertz or even lower sometimes and those circuit power may be the major criteria. In that case, power supply voltage can certainly be reduced. The additional power reduction methods which will allow this low power design possible is the preserving circuit speed and computational throughput mandatory. Now if you have a criteria that you have to have same speed and also you do want the data to be available to you at the given throughput rate, in that case what can be done? There are two possible solution when of course is threshold voltage scaling. So, you can reduce the threshold voltage because after all the current in the mass transistor is proportional to Vgs minus Vt. Since it is proportional to Vgs minus Vt, if you reduce Vt and Vgs can go to even lower Vdd, but Vdd minus Vt then can be higher and therefore, current can be made higher and if higher the current larger is the speed we know and therefore, the speed can be preserved by keeping lower power supply voltage, but also reducing the threshold voltage. The second possibility or second solution to get the same speed and same throughput for the logic you are implementing is the architectural driven device voltage scaling based. There are two possibilities in which one can have pipelining or one can have parallelization in either of this architecture techniques. Though the speed of the net circuit does not remain to be lower than what you are expecting, but the individual components do as if running at a higher lower clock rates or you can say running a higher clock, but the net circuit speed is what is desired and individually therefore, by pipelining or parallelization we may be able to reduce the net power and this is very interesting because that is the only way circuit way we can actually reduce the power dissipations. Of course, some cost whenever you achieve something we will have to give up something and let us see what happens when we go through such architectural driven voltage scaling. Now, first in the foremost method which most people believe is to reduce the power is reduced threshold voltage while reducing supply voltage. Say example, there can be two possibilities the circuit A may actually have VDD 1.5 volt and threshold of 1 volt and a circuit B may have a VDD of 0.9 volts and threshold of half a volt and if you see the if you calculate the using this VDD and threshold voltage values if we calculate the propagation delay and therefore, the speed and hence we call the performance they seem to be almost identical. So, now we can see that I reduce VDD, I reduce threshold and I can still attain the speed. There is a this is some same similar graph shown here Td increases as VDD approaches to threshold that is where how much VDD can be reduced. So, here is a figure shows threshold voltage versus delay and we are varying a threshold voltage from say 0.2 volt to 1 volt and we are also varying VDD from 1 volt to 5 volt. Of course, 5 volt hardly anyone is working, but at the same time if you see that if your threshold voltage is of anything less than 1 volt and if your power supply voltage is large the delay of course, in normalized delay is very very small around 1 or 2 normalized delays. Whereas, if you start reducing the power supply voltage from 5 volt down upwards you can see as VDD goes to 1.5 we already under normalized delay of around say even at say threshold voltage is reduced to say 0.4 or 0.5. So, it is around still slightly higher, but if you go when the VDD approaches threshold voltage which is your say point this is 1 volt and if they I make it 0.4. So, one can see that as I approach this threshold voltage power supply voltage goes near to threshold voltage then the Td starts enhancing and this is very very important because essentially which means that the difference between threshold voltage and the power supply voltage had to be maintained higher so that the speed is not lost. Alternatively, speed will be lost if VGS minus VT reduces. What I am going to say about this is during this threshold voltage scaling if threshold voltage scaling is required low threshold mass devices must be used for the design. The limit on threshold voltage scaling is imposed by the noise margin and the increase of sub threshold current as we some of these problems we shall see little later. At least the noise margin part can be understood let us say I have a I reduce my threshold voltage to 0.2 volt or 0.25 volt and I have a supply of 0.8 volt or even less than 0.8 say 0.6 volt. So, my VGS minus VT is sufficiently high to create good amount of current, but when I go below 0.2 volt which is my threshold one can see from here that 0.2 volt is hardly 8 kT by Q as room temperature and therefore anything below this voltage the if you have to reduce your output to lower than VT which will be around close to 50 millivolts or so you are well within the noise levels and therefore it will be very very difficult for us to maintain noise margins because then thermal noise or even other noises may actually start dominating at those points and therefore the noise may actually dominate if threshold voltage is very very low. However, please remember as long as your VGS minus VT are therefore VDD minus VT is large the speed certainly can be met. However, we also worry later as we shall see that the sub threshold current that means when the VGS goes below VT we know the current continues to flow and you know the reduction in voltage less than threshold has a slope of IV characteristic there ID VGS characters there and one finds that a small change in even threshold actually changes the sub threshold currents. So, obviously if that 60 millivolts per decade as what we say so one can see from here that large sub threshold current can also lead to leakage currents and therefore too much reduction in threshold voltage is not very much advisable unless otherwise you do some more tricks to really ward off this issue. So, therefore tradeoff between say p-switching or dynamic power which certainly p-switching decreases if threshold decreases and p leakage which increases at threshold decreases. So, one has to tradeoff between the dynamic power and the leakage power in the in the regime in which threshold voltage is scaled on. Showing the same thing what I said about power reduction method in threshold voltage scaling technique instead of showing you power now I am showing you energy which is normalized energy versus threshold voltage plotted at three power supply voltage VDD 0.5, 0.9 and 1.7 and we believe that they as you reduce your threshold voltage down for the energy minima to occur and energy we can show you energy is nothing but power per unit time energy is power into time energy per unit time is power. So, if we integrate over the time for which this period for which you want to know energy it can be figured out by writing such an expression for energy minima that around 0.4 volt of threshold and at that time the VDD being 0.9 will give you the minimum energy. So, for a given technology and given device structure which you use you may get an energy minima and for which there will be some kind of an optimal threshold voltage which will give you the lowest power dissipations. Now, people keep saying that I also said my first few talks we keep saying that as far as moods law every technology node is nothing but the reduction of lengths and widths and every other thing by a scale factor by 0.7 and if we reduce or scale down all the parameters by 0.7 to follow moods law that every every year components if the doubles because 0.7 into 0.7 is 14.49 which is half. So, obviously if you reduce the component density will double which is very obvious by moods law. However, what it impacts on is C load scales by 0.7 VDD also scales by 0.7 let us assume right now we are scaling by same what is called constant field scales. Energy consumed per clock cycles scales by 65 percent active power is given by we have already derived it alpha and Cv square and is the n is the number of components per this. So, it doubles every generation. So, frequency increases by 43 percent. However, if you do this calculation at the end of the day one interesting result one observed that if you scale down by just 0.7 volt everything then overall active power remains unchanged. So, you are trying to reduce the power you thought you have active power reduced but this alpha and Cv square term actually does not change very much when you scale down. So, the p active power is essentially is equal to n t is the number of gates C average is the average capacitance of the gate or load which is seen VDD square is the power supply voltage square f clock is the frequency at which data is flowed and alpha is the activity coefficient this we already derived earlier. So, if we write the period for one data cycle then it can be written as Ld which is the logical depth that is if you have a three series components three series gates in one cell driving the other then Ld is 3. So, Ld is called the logical depth. So, if you see this term Ld into C average VDD by your own is the cycle time which is nothing but one f clock. So, one can see if I substitute this part if I reduce the this is interesting if I reduce the logical depth from here my clock frequency goes up. However, if I substitute this in case of power which is nothing but n t VDD ion upon alpha I just substitute this term inside here for f clock 1 upon Ld C average VDD by ion I substitute here and I get a term n t is active power is n t that is the number of gates VDD which is power supply voltage on current which is the on current from the transistor alpha is the activity coefficient and Ld is essentially the logical depth. So, if you reduce the logical depth the power does increase and therefore, one interesting feature is if you do not scale Ld then p active remains same. However, to get higher speed we need to scale down Ld and if you show active power. So, you will actually to improve your this you reduce the Ld because then only yours by logical effort we have seen if that occurs then the speed will go up and if you scale down Ld then obviously, the p active power will increase with the scaling. Now, there are variety of CMOS design styles and we like to see each of them in light of their low power performance. Now, if you take a static CMOS which is the most standard CMOS circuit which essentially let us take a representative inverter which shows you have a p channel transistor and you have an n channel transistor which is connected and this is your power supply, this is your VSS ground, this is your input and this is driving a net load of capacitive CL which is load capacitance and this is your V0. So, if you look at this the logical power we know it is proposed because the charging through the power supply or discharging through the ground essentially leads to power dissipation and in between when the input changes state high to low or low to high both transistor on for a while which essentially gives the static power on that and that is also because of the scaled down devices both n channel and p channel are never really turned off fully and which means there will be a leakage path throughout. Now, if you see dynamic power and short circuit current applies mismatch delays can lead to glitching. So, the problem is this this one we shall see it depends on this logical input you give which is 0 to 1 in a pulse form and depends on the sizing you do and depending on the currents you can you are able to switch in this transistors there may be a possibility of switch occurring something like this sorry glitch occurring something like this and any such glitch can lead to a high power high dynamic power dissipation. However, if you do this is occurring because transistor this was initially say at 0 it was on and this was off when this goes to 1 this became off and this became on they switch actually. But if they do not switch as in the case of dynamic let us say I have a p channel device which is given to a clock or phi bar phi and I have a dynamic logic in which I may keep another transistor or I may not keep I may actually put this also at clock phi phi bar let us say I this is independent. But if you see in a dynamic system the when the clock bar is 0 or when the clock is 1 a clock is 0 clock bar is sorry this is phi. So, if this is 1 this is 0 and that p channel conducts and charges this this is called pre-charge. But when phi goes to 1 p channel turns off and this capacitor discharges or does not discharge depend upon the input on this logic which essentially means there is no short circuit path between power supply and ground and therefore dynamic logic eliminates glitches because they are no time they really switch on the same times. So, the short circuit power and glitches can be minimized if you use dynamic logic that is what I say when we say only static power due to leakage. Now, fully complementary design has a high noise margin we know if we keep VOH is VDD and VOL is ground in which case design style more scalable to low power supply voltages because one can then reduce because any one is ground the other is power supply. So, scaling down is much easier and the full swing is also possible which essentially implies that lower the threshold voltage can be used if we have a fully complementary design static CMOS. The PMOS devices may degrade performance simply because high input capacitance slow series p stacks actually if you are large number of p stacks in this they can actually slow down because of you know their mobility is being lower stack in a stack case the net capacitance may increase and also you may have a slower series p stack and therefore, they may degrade the performance in the case of static CMOS as far as performance I am talking about speed. The other possibility of you know looking for a power low power design is to use differential cascode voltage switch logic. Now, this is very interesting logic which creates both out and out bar simultaneously. One can see from here there are two p channel devices cross connected to the outputs and PDN 1 and PDN 2 are n channel logical this only thing is the criteria is that when this is on PDN 2 is off or when the PDN 2 is on therefore, PDN 1 is off. So, if this let us say for given inputs PDN 1 requires this output to go to 0 in which case at that time anyway this was not receiving any data. So, one can see from here that since this is 0 this turns on the output becomes high which is complementary in the same go. In case this PDN 1 essentially is requires this to be 1 that is this turns off and this turns off what are the last state this must this high mean this must be acting which means this must be 0. So, 1 0 is retained. Now, please remember PDN 2 R pulls out low and turning on PMOS which pulls complement high this pulls complement high. So, this differential cast out voltage switch logic has one advantage essentially that both out and output and there is no additional power required in actually getting both true and complement outputs. The only problem which I see here is you are two such blocks to work on additional hardware and though power wise it does not add to a power, but it is it has an additional area and additional area additional component density which you have to pay for. Now, what I said I may repeat again differential logic style generating both polarities of output can improve the speed because there are no inverters. See basic problem in all the time taken as we know we define the propagation delay is going from 0 to 1 and 1 to 0 average delay is TPHL plus TPLH since there is an inversion in this case there is no inversion and since there is no inversion the speed is very high as does not have inverters. Since it is a extra noise immunity to common mode noise or say it is a differential circuit. So, obviously common mode noise is eliminated which is standard for a differential amplifier kind of system. The third possibility advantage one sees in the case of DCV cell is convenient for self-time or asynchronous logical design because then PDN, PDN 2 can be asynchronously concerned because there is no really clock requirement. However, please remember it is still a ratio logic style even the output transition is rail to rail. PMOS must have to be sized carefully to ensure going to 1 and 0 properly or pull down pull up ratio has to be such that 1 and 0 can be fully at the full rail voltages. And therefore, to pull down network must overcome the PMOS on the other side because you know now they will actually the other side PMOS will actually will also draw current from the PDN 1. And therefore, one has to pull down network has to really ensure that it receives that much current to make it 0 or 1 as desired. The third point which is of interest is short circuit current flows while outputs are switching pull down fighting opposite PMOS. When the outputs are switching pull down fighting you can see from here if I go back if we see here you know the when this is pulling down this is essentially loading it or for this this is essentially loading it. So, one can see from here that the short circuit current flows while outputs are switching pull down fighting opposite side and PMOS. Twice the number of NMOS inputs because you want both out out bar you are to PDN 1 and PDN 2 compared to single ended ratio logic style and therefore, it is to higher capacitance, but it certainly gives you low power. So, what are the advantage of dc dcb logic? It is the following that for the low power the advantages are lower physical capacitance is fewer devices used to implement given logic function input loading lower since now dual PMOS devices gets must allow only one transition for correct operation and therefore, no glitching no short circuit power since sorry I am sorry. This is we are talking of dynamic logic and not dcbl. In a dynamic logic as we discussed here in this figure you can see in a dynamic logic lower physical capacitance is fewer devices you only you have all N logic and only P channel and channel as a complementary for 5 5 bar. So, we are fewer devices so obviously, the net capacitance seen here will be smaller input loading lower since new now dual PMOS device. So, actually you do not this is only loaded here. So, one does not require additional loading case must allow one transition for correct operation since it is only one input should occur when the clock bar is available or clock is not one at that time since your input has to settle which has half the cycle roughly you can say therefore, no glitching requirements. No short circuit power since pull up path can path not enabled when you see when you when this is on. So, when this is on this is off when this is on this is off and therefore, short circuit power is minimal since pull path no and not enabled when evaluating power output. However, every good thing has some disadvantage as well there are disadvantage for in the light of a low power requirement higher clock power since guaranteed clock more transitions you know since you are using fine 5 bar you need a power which will guarantee leak make this on off of these two devices. So, that means you require driver for clock clock and this driving of the clock essentially means that you are consuming additional power. More than minimal number of devices for implementation because you can see if you have a static CMOS I would have required only 2 I will require 3 and of course, it does not mean correctly what I meant was that if you need extra clock and clock bar and that means the net number of devices are not smaller though logically number of devices may be smaller higher switching activity as shown earlier and because of that the dynamic this though looks to be good in some cases though may have because of the clocking system may actually show higher switching activity and we know dynamic power is proportional to switching activity. Now, the other possible way of implementing logic we all know is essentially coming from CPL. So, for example, if you have one complimentary this is a CMOS pass gate another CMOS pass gate this may be phi this may be phi bar and this may be input or even normal pass transistor logic without CMOS can be shown equivalently something like this and if I connect this one can see from here if it is a b a bar b bar this output could be a b plus a bar b bar this is essentially x naught which we are trying to implement from here. So, what essentially pass transistor logic allows is to create any combinatorial logic can be implemented and using feedback paths or using a loop paths even we can create sequential blocks using pass gates. Now, since there you can see from here there is no power supply there is no inversions going on. So, obviously one feels that it should create a much low power and it will also have much lower transistor count. Since there are number of devices are dramatically lower than static CMOS one can say no static power is circuit designed to maximize swings extra routing overhead implies extra capacitance you will have to run a bar and b b bar. So, you need some extra capacitance to drive performance worse than other styles specially when gates are cascaded of course these are acceptable when aggressive voltage scaling reaches limits then only one way to reduce power is to reduce switch capacitance. So, in some case when you are scaling down technologies to 45 or 32 or down CPL may become very dominant design style or CMOS style of implementation of logic. One of the biggest advantage it will give you power delay product lower than for any other style we had earlier discussed to you in my earlier figures that it is if I plot tau versus power this line is called power delay line and if you want better design you should go from here to here which has let us say this is p 1 this is p 2 tau d 2 such that p 2 tau d 2 is less than p 1 tau d 1 tau d 1 is the delay and power is the delivered by the gate. So, one if you can see if you come down lower than this at higher speed you have lower power and CPL does improve power delay product which is less than or which is called also switching energy is always less than any other design style using CMOS or NMOS circuits. So, essentially this is good however it has extra routing implies extra capacitance power is lost somewhere there it is not very easy for a switch to act ideally and therefore, there are problems of KT by C noise or sharing of charge or feed forward of course, CMOS takes care of feed forwards, but otherwise it does have its own problem as a pass gate. So, when I am scaling down over the years that is what Mohr's law is suggesting. So, we look into the problem which we are now getting we are already discussed earlier that the larger larger node technologies 0.25 0.5 or even higher the channel links were very high say the channel links were very high and doping were also smaller relatively between the substrate and the ratio. So, what used to happen then that the diode leakage currents or any other leakage mechanism leading to the leakage power was much smaller even the sub threshold slope was such that the net leakage current does not change drastically. However, what has happened over the years as I am scaling down I see now if I plot powers per stage shown here millivads on this and I plot against delay here in nanoseconds. So, if I change the technology say from 0.25 down to say 90 nanometers are like this 0.13 or even below if you go below one is finding that the delay is decreasing definitely delay is decreasing, but the leakage power at any node you go for any delay say for example, for 90 nanometer or 0.13 for the same decay you know the leakage power per stage is higher. So, essentially what is happening here the same thing can be shown here if this is your n minus 1 node this is your n th node and this is your future node as you scale down the power will keep on increasing irrespective which node you are working at lower the this the though it is not very obvious, but the slope of rise of a leakage power is much higher compared to these two if you go even further it will actually rise much faster here. Now, this it means the new metric of performance one should now worry about if you are looking for gigahertz applications of your CMOS chip you must also be equally worried about the leakage power which is wasted without being used utilized in any sense. A typical semiconductor is industry association roadmap shows there are two currents of interest one is called the on current in which when the transistor is on VGS is minus VT is greater than VGS is greater than threshold once say it is a on current particularly the on current is normally defined in the device is in saturation and off current includes all the currents like sathrasual current the diode leakage current and also the other any kind other dependent leakage currents which we shall show you later seven of them in fact they all contribute to off state. So, off current to on current is very important to maintain larger on current and smaller off current is what is ideally required you need a very large ratio of ion to ion off so that you have a no leakage power very very low leakage power and can adjust your on current to suit your performance requirement. We also know there are three kinds of circuit I already discussed one is high performance then other is low power and the last is low standby power. For the high performance low operating power and low standby power devices which will of course this is a 2002 road map I could not get the latest one from ITRS this in this format. However, this shows the trend from this it is the channel length physical length. So, you are going from in a nanometers you can you can see what is the requirement of this EOT essentially is called equivalent oxide thickness because the gate thickness also is going to be reduced as you scale down. So, if you see this is 0.4 to 0.6 micron, 0.6 to 1 and 0.7 to 1 point equivalent. Please do not think real life it would be less than 10 amperes on current is defined as per micro ampere per microns or we require 1500 this for LOP is 5900 this is 700. Off current required is 10 micro ampere micron this is 1 and this is 0.1. So, ratio is we want larger for as you go from high performance to low standby power. This is something we are requiring in the all circuit which we are going to design for three such applications as I say this is one typically mobile or a even a what we could say is the iPads or tablets which are running on a battery power you are looking for LSTP circuits in many of them are LSTP circuits. Now, looking at the technology side just to give in some quick glimpse of this this is a figure which according to ITRS which is the technology roadmap society which shows on current micro ampere micron versus sorry off current versus the on current which is micro micron and this shows you a figure of a different technology CMOS 180 my nanometer down and this green one is high performance circuit in which the on current is very high and the correspondingly sorry on current is constant and off current is. So, if you really look for high performance circuit in this figure somewhere around 900 or 1000 micro ampere micron of this the off current has gone from this two orders up to this. So, our idea is somehow in technology to stem this height going suddenly jumping this is the actual technology graph CMOS 65 nanometers. If we go for newer technologies we must do some kind of what you would say work function engineering or something and you use metal gates instead of poly silicon gates. You can see poly silicon gates are not as good as metal gates because what we are really trying now is to increase the on current at least this side. But should not increase the off current in that ratio if you can improve the this at least the high performance circuit data can be required and similar argument can be given for low power and low standby power. So, now also the another issue of circuit design for low power or low standby power is that the technology which is going to be used for all individual for each of those process will not be identical. You have to tailor your technologies one scale for what the kind of application you have in mind for that particular design. There is an interesting figure a table shown to you here this is Cauchy-Cauchy-Kreiber University. They have shown of course some when they showed it the technology has not scaled down to 35 nanometer then, but it is still valid actually they evaluated as the scaling was going down they expected that the net from 70 nanometer which is essentially 65 nanometer 45 and 32 they are just rounded up for calculations by them. This is 65 nanometer node this is 45 nanometer node this is 32 nanometer node at those nodes of technology the total power they save 41 watts at 65 nanometer and 128 almost triple at 32 nanometer this is one and half times. So, 45 to 65 that is not very much, but when you go 0.7 of that further then we find it almost doubles of 64 and 3 triples compared to this. Now, of this total power dynamic power total power of 41 watts at 65 nanometer node the dynamic power is 78 percent whereas, the leakage power is just 22 percent, but if you scale down to say 50 nanometer or what called 45 nanometer node the dynamic power reduces to 56 percent and the leakage power enhances to 44 percent. And if you go further down which is 32 nanometer this become 33 percent the leakage power is 67 percent and if you further scale down if you can extend this value it may happen that the leakage power will be 80 percent and this may be useful power to you will be dynamic power will be on current power will be 20 percent. What it essentially is trying to say of course, they are assume 3 mm by 3 mm chip size the chip size may die size that may change in real life. And therefore, this data is not the actual data or exact data for real measurements, but it does show you the trained. Now, just to make little this lecture little interesting I mean now see you that as most of the newer iPods or iPhones or including from Samsung or Nokia or Sony or anyone you name even the Chinese one they are already working on 32 or below 32 nanometer processors ARM processors or any other processors. Since, they are working and low technology nodes the power dissipation is major worrisome for all of this circuits mobile phone for example, now if this leakage power becomes higher which means the battery will drain faster if you are not really operating it at the mobile phone is not on. The advantage of this things not happening good for you is that if you keep your mobile on all the time that means you keep talking on your mobile your battery may drain less power compared to if you would have just kept in a standby mode. And I think one such reason now I figure out why younger colleagues of mine who are an undergraduate graduate studies they keep talking on mobile phone incessantly when they walk on the roads or they are in the room or wherever they are probably they knew this file better than me they realize that the battery drains slower if they keep talking and if they just keep the mobile on the last standby mode the power dissipates faster dissipation is higher and they have to recharge the mobile oh this is a fun but that may be possible may be reasons why people talk so much on mobile these days. The another problem in technology when I scale down technologies there is something a word which ITRS has said which is called the electrostatic integrity E 1 or EI sorry EI if you look at short channel effects and the Dible which essentially controls the threshold voltages and the currents in the mass transistor therefore the mass transistor currents in the mass transistor it can be shown that this 5D which is called the source to channel built-in voltage and VDS of course is drain to source bias okay. Then we see that the short channel effects is can be starts when it is 2 5D times EI Dible is 2.5 times VDS EI so if where EI is essentially given by 1 plus j square by 11 square T ox equivalent oxide thickness by channel length T depletion by L channel length electron actual equivalent channel lengths. So, one if you see from the technology side if you scale down this okay equivalent channel length and since you are scaling down x j goes down and this is square term which is increasing now this means the short channel effects and the Dible coefficient will be directly proportional to the technology you use and since they both affect the threshold in way some way they actually reduce the threshold voltage well the leakage paths will be much stronger sub threshold path will particularly very strong and therefore lot of leakage power will happen if you have lower nodes of technology. Now, there are other ways of for high performance circuit in particular if you wish to I am talking of high performance because we are saying their power is not a criteria as much as the speed. So, for this there are performance booster technologies available and they have been gradually introduction in the following way Intel has started working on strain silicon channels you have silicon germanium as instead of source drain silicon you have a ultra thin body single gate FETs UTV that they called then you are using metal gate electrode with high kid gate oxide instead of silicon dioxide your ultra thin body double gate FETs which is dual gate FETs which we will call this the modified version is nothing but a pin fit and we will look into the power using pin fits little later. Then there are other devices possible which are quasi ballistic or ballistic transport possibility reducing the fringe or end or overlap capacitances and metal source junction instead of silicon source drain junctions these are of course technology details. However, the worrisome part which I just now discussed in the MOS transistor as you scale down the technology nodes particularly below 45 30 to 20 to 16 11 7 and where I do not know where lower will be these are the various contributors to leakage power there is of course if I will show you the figure little later because two things are not showable here to me I did not prepare properly the first and the foremost if you have a MOS transistor if you have a MOS transistor shown here this is your source this is your drain that is N channel and this is your substrate this is your bulk this is your insulator this is your gate this is your drain this is your source this is your N channel MOS FET. So, if you see this this is essentially a diode same of course here there is a diode between source and substrate. So, particularly source is grounded bulk is grounded even then the diode has a leakage current very small if you see this in N channel this will become VDS which is higher this is heavily reverse bias diode and therefore leakage current is very high in this. So, the first contribution to leakage power is the reverse leakage current of these two diodes then we believe that when VGS is less than VT there is no channel here. The channel does not exist VGS is less than VT no current is because we say there is no electron channel, but in reality we know that the threshold voltage is defined as VGS is equal to VT when the band bending we say phi s is equal to 2 phi f where phi s is the surface potential and phi f is the Fermi potential. Now, in reality the inversion starts when phi s is just greater than phi f less than sorry I mean yeah it is greater than phi f value wise. So, which means the band has already bent for this. So, we say that reverse leakage current of the diode essentially may be one sorry sub threshold current essentially will occur when phi s lies between phi f and 2 phi f and that means even if VGS goes below VT the IDS VDS characteristics small VDS do show some characteristics like this and that means this current may not be very very small and in fact the slope which we are going to use here which is called sub threshold slope may actually increase that means the number of the change in current or change in voltage for large change in current will be different and in which case one has to worry about leakage currents being stronger at lower technology nodes. Then since this is also thickness of oxide is also scaling the there is a oxide tunneling directly carriers scan tunnel which is called normal tunneling band to band tunneling one can see. Then there is a possibility that if this channel length is very very small as the scaling goes the electric field across this E y we say this is y direction is very high carrier somewhere here at the drain end may actually pump inside the oxide and in which case there will be a hot carrier injection in the gate which may constitute the current. There is also if you increase if the channel length is very large this electric field is larger this is also larger the gate can influence the drain end electric fields we believe that it is only gate introduces the channel but drain and together may induce the leakage path much stronger and this we say gate induce drain leakage. The channel points through current the two depletion layer with associated with this diode and this diode may merge in which case function can occur. So, these are possibilities of leakage power and these are what they are shown here I 1 essentially the diode leakage I 2 essentially I 2 I 3 and I 6 are all are between this I 17 tunneling and gate induced drain leakage are through this and then there is of course there is a current part of this current the griddle may come here and this hot carrier effect is also part of this. So, one can see in a deep sub micron podivan animator down technologies these currents may dominate I already written the names which are the currents and these each currents are essentially contributing to transistor leakage mechanisms. So, what it affects the leakage change in substrate body bias affect the threshold voltage we are very interested to know how to control leakage. So, we are now looking into way we say change in substrate body bias affect the threshold voltage and so the leakage current. There is another issue which is very interesting it is called Dibble drain induced barrier loadings we always thought that gate controls the channel depletion layer, but essentially if the channel length are smaller the source drain also have large depletion layers and drain can actually therefore, contribute to electric fields and reduce the barrier at the drain end and therefore, currents can increase essentially the threshold changes because of the Dibble coefficient changing. However, we know higher the threshold V d d V th will be smaller reduces the threshold voltage because then in that case since threshold is lower currents are larger one can say. Then there is a last but not the least higher temperature raises the leakage currents which is obvious diode currents are e to the power q by n k t. So, t lies in temperature is very strongly increasing the currents and that increase in currents leads to increasing temperature and since increasing temperature a different technology is increasing as we already discussed over the years. Now, if junction temperature rises over the ambient temperature which is essentially called thermal resistance into power please remember that junction temperature increases 1.45 per generation times the last one. And therefore, if you scale down one node then you actually increase one and half times the leakage thermal temperature junction temperature and therefore, to maintain junction temperature within a limit. So, that the junction remain junction one has to worry about cooling which is called we must change the thermal resistance from junction to ambient such that heat is dissipated faster. We will come back to it next time and we will show you that if we want to control so called these leakage currents what circuit techniques lastly of course, it is not circuit lastly we will say different channel length which is also to some extent circuit technique. We will say if we use these techniques probably one can still play with reduced leakage currents. Thank you for the day.