 Hello, and welcome to this presentation of the STM32 General Purpose I.O. interface. It covers the general purpose input and output interface and how it allows connectivity to the environment around the STM32 and microcontroller. The general purpose I.O. pins of STM32 products provide an interface with the external environment. This configurable interface is used by the MCU as well as other embedded peripherals to interface with both digital and analog signals. Application benefits include a wide range of supported I.O. supply voltages as well as the ability to externally wake up the MCU from low power modes. The general purpose I.O. ports provide bi-directional operation according to the input memory map. I.O. ports are directly connected to the HB buttons. This allows fast I.O. pin operations, such as toggling and output, with an independent configuration for each I.O. pin. They are shared across eight ports named GPIOA to GPIOK, each of them hosting up to 16 I.O. pins. After reset, all GPIOs are in analog mode to reduce power consumption. I.O. ports support atomic bit set and reset operations through the BSSRR and BRR registers. It allows I.O. toggling every two clock cycles. Most of the I.O. pins are 5 volt tolerant when supplied from VoltDD above 1.62 volts. The general purpose I.O. pins can be configured for use in several operating modes. An I.O. pin can be configured in an input mode with floating input, input mode with an internal pull-up or pull-down resistor, or as an analog input. An I.O. pin can also be configured in an output mode with a push-pull output or an open drain output with an internal pull-up or pull-down resistor. For each I.O. pin, the slew rate speed can be selected from four ranges for the best compromise between maximum speed and emissions from the I.O. switching and to adjust the application's EMI performance. I.O. pins are also used by other embedded peripherals to interface with the external environment. Alternate function registers are used to select the configuration for the peripherals in this case. The configuration of the I.O. ports can be locked to increase robustness of the application. Once the configuration is locked by applying the correct write sequence to the lock register, the I.O. pins configuration cannot be modified until the next reset. Several integrated peripherals such as the USART, TIMERS, SPI, and others share the same I.O. pins in order to interface with the external environment. Peripherals are configured through an alternate function multiplexer, which ensures that only one peripheral is connected to an I.O. pin at a single time. Of course, this selection can be changed while the application is running through the GPIOX AFRL and AFRH registers. During and after reset, the alternate functions are not active. Only debug pins remain in AF mode. JTAG SWD debug pins remaining in AF configuration mode are listed on this slide. When the external oscillator is switched off, pins related to this oscillator can be used as standard I.O. pins. This is the default state after device reset. When the external clock source is used instead of a crystal oscillator, only the related OSC in-pin is used for the clock and the OSC out-pin can be used as a standard I.O. pin. This cell is used to control the I.O. commutation slew rate, T fall or T rise to reduce I.O. noise on the power supply. The cell is split into two blocks. The first block provides an optimal code for the current process voltage temperature, or PVT. The code stored in this block can be read when the ready flag of the SysConfig CCSR register is set. The second block controls the I.O. slew rate. The user selects the code to be applied and programs it by software. The I.O. compensation cell features two voltage ranges, 1.62 to 2.0 volts and 2.7 to 3.6 volts. Optimizing the I.O. speed when the product voltage is low is allowed by setting the high speed I.O. configuration bit in the SysConfig CCSR register. This bit is active only if the I.O. HSLV user option bit is set in the Flash OPTSR register. It must be used only when the product supply voltage is below 2.7 volts. Setting this bit when volts DD is higher than 2.7 volts may be destructive. Some pins or balls are directly connected to PA0C, PA1C, PC2C and PC3C ADC analog inputs. There is a direct path between PXYC and PXY pins and balls through an analog switch. Connections are handled through the system configuration controller or SysConfig.