 Hello, and welcome to this presentation of the STM32 Analog to Digital Converter Block. It will cover the main features of this block, which is used to convert the external analog voltage-like sensor outputs to digital values for further processing in the digital domain. The analog to digital converters inside STM32 products allow the microcontroller to accept an analog value like a sensor output and convert the signal into the digital domain. There are up to 20 analog inputs available across the three ADCs. The ADC module itself is a 16-bit successive approximation converter with additional oversampling hardware. Due to the noise level, only 14-bit equivalent performance is achieved. To have more than 16-bit performance, it is necessary to use oversampling methodology. Under certain conditions, the oversampled output can have a 21-bit result. The sampling speed is 5 mega-samples per second for 14-bit resolution. Each ADC module integrates an analog watchdog. The data can be made available either through DMA movement or interrupts. This ADC is designed for low power and high performance. There are a number of triggering mechanisms, and the data management can be configured to minimize the CPU workload. Three analog to digital converters are integrated inside STM32H7 products. The input channel is connected to up to 20 channels capable of converting signals in either single-end or differential mode. The ADCs can convert signals in 5 mega-samples per second in 14-bit mode. There are several functional modes, which will be explained later. There are also several different triggering methods. In order to offload the CPU, the ADC has an analog watchdog for monitoring thresholds. The ADC also offers oversampling to extend the number of bits presented in the final conversion value. For power-sensitive applications, the ADC offers a number of low power features. This slide shows the general block diagram for the three analog to digital converters embedded in the STM32H7. The STM32H7's ADCs support a deep power-down mode. When the ADC is not used, it can be disconnected by a power switch to further reduce the leakage current. The co-delayed mode makes the ADC wait until the last conversion data is read before starting the next conversion. This avoids unnecessary conversions and thus reduces power consumption. The power consumption is in function of the sampling frequency. For low sampling rates, the current consumption is reduced almost proportionally. The ADC supports up to 5 mega-samples per second of 14-bit conversion. By using dual interleaved mode, it can be extended to 10 mega-samples per second. The ADC includes the oversampling hardware, which accumulates data and then divides without CPU help. The oversampler can accommodate from 2 to 10 24-time samples and right-shift from 1 to 8 binary digits. The sequencer allows the user to convert up to 16 channels in any desired order. Also, each channel can have a different sampling period. The ADC offers an auto-calibration mechanism for the offset and the linearity. It is recommended to run the calibration on the application if the reference voltage changes more than 10%, so this would include emerging from reset or from a low-power state where the analog voltage supply has been removed and reinstated. The ADC needs a minimum of 1.5 clock cycles for the sampling and 7.5 clock cycles for conversion for 14-bit mode. With a 50 MHz ADC clock, it can achieve 5 mega-samples per second. For higher sampling speed, it is possible to reduce the resolution down to 8 bits. Then the sampling speed can go up to 8.3 mega-samples per second. The sampling time can be programmed individually for each input channel of the analog to digital converters. The sampling times listed in this slide in ADC clock cycles are available. Longer sample times ensure that signals having a higher impedance are correctly converted. The ADCs have a selectable clock source. When the system needs to run synchronously, the AHB clock source is the best selection. If a slow CPU speed is required, but the ADC needs a higher sampling rate, the dedicated ADC clock can be selected. The ADC-KERCK source can be selected from the independent PLL. There are three different types of inputs. Direct channel, where IOs are connected to the ADC input without series switch to get the fastest sampling time. Fast channel, where IOs are connected to the ADC input with low-resistive switch to get faster sampling time. And slow channel, where IOs are connected to the ADC input with standard resistive switch for slower sampling time. The ADC performance is dependent on the package type and on the number of channels working at the same time. The figure shows that the BGA package technology is offering the better performance, especially at high resolution. The ADC speed also depends on the sampling time and the conversion time. During the sampling time, the hold capacitor must be charged to the proper LSB voltage with an error lower than a half of the LSB voltage to ensure a correct accuracy. And the higher the resolution, the longer the sampling time. This is why it is sometimes more efficient to use a lower clock frequency with a low sampling period to get a higher sampling rate. The ADC supports several conversion modes. Single mode, which converts only one channel in single shot or continuous mode. One mode, which converts a complete set of predefined programmed input channels in single shot or continuous mode. And discontinuous mode, converts only a single channel at each trigger signal from the list of predefined programmed channel inputs. The ADCs support hardware over sampling. They can sample by two to 1,024 times without CPU support. The converted data is accumulated in a register and the output can be processed by the data shifter and the truncator. 16-bit data can be extended to be presented as 32-bit data register. This functionality can be used as an averaging function or for data rate reduction and signal-to-noise ratio improvement as well as for basic filtering. Each ADC has an integrated analog watchdog with high and low threshold settings. The ADC conversion value is compared to this threshold window. If the result exceeds the threshold, an interrupt or external signal can be generated or a timer can be immediately stopped without CPU intervention. The ADC conversion result is stored in a 32-bit data register. The system can use CPU polling, interrupts or DMA to make use of the converted data. An overrun flag can be generated if data is not read before the next converted data is ready. For injected channel conversions, four dedicated data registers are available. An injected conversion is used to interrupt the regular conversion, then insert up to four channel conversions. Once an injected conversion is finished, the regular conversion sequence can be resumed. The injected conversion result is stored in dedicated data registers. These and interrupts are available for the end of conversion or end of sequence. The choices for an injected channel can be reprogrammed on the fly. Even if a regular or injected conversion is in progress, you can add a different channel to the queue so that the next injected channel can be different from the previous one. Each ADC can generate nine different interrupts, ADC ready, end of conversion, end of sequence, end of injected conversion, end of injected sequence, analog watchdog, end of sampling, data overrun and the overflow of the injected sequence context queue. DMA requests can be generated at each end of conversion when the ADC output data is ready. The ADCs are active in run and sleep modes. In stop mode, the ADCs are not available, but the contents of their registers are kept. In standby mode, the ADCs are powered down and must be re-initialized when returning to a higher power state. There is a deep power down mode in each ADC itself, which reduces leakage by turning off an on-chip power switch. This is the recommended mode whenever an ADC is not used. Note the ADC 3 located in the D3 domain can run while other domains are in standby mode. The following table shows performance parameters for the ADC. All values are preliminary. The ENOB of 16-bit mode is saturated when less than 14 bits due to the noise level of the system. By using oversample mode, the ENOB can be extended further. These peripherals may need to be specifically configured for correct use with the ADCs. These refer to the corresponding peripheral training modules for more information. The STM32H7 embeds three ADCs. ADC 1 and ADC 2 can be configured to work together in dual mode, so that each analog to digital conversion can be synchronized between the two modules. ADC 3 works as a standalone converter. Several application notes dedicated to analog to digital converters are available. To learn more about ADCs, you can visit a wide range of webpages discussing successive approximation analog to digital converters.