A Self-Repairing Bio-Inspired Fault-Tolerant FPGA Architecture (By Hasan Baig)





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Published on Apr 22, 2012

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The most complex thing in any FPGA architecture is its routing network, and to propose a new FPGA architecture means to keep all the routing issues in mind while developing a new FPGA architecture. Also it is difficult for the commercial FPGA vendors like XILINX, Altera etc, to refine their existing routing architecture according to the newly proposed schemes to incorporate the fault tolerant capabilities. This arises the need to develop such a design that can easily be integrated with the existing routing architecture. In this research, we have developed a complete homogenous fault-tolerant FPGA architecture with self-repairing capabilities. Unlike previously proposed architectures, the present one can not only be implemented on the existing island-style FPGA architecture but can also be able to fabricate entirely as a new device utilizing the existing routing network strategies. The developed architecture is unique in a way that it is able to identify transient and permanent errors (at LUT level) both at the same time. A generic fault-tolerant Computation Cell is developed which along with its self-checking circuitry also consists of an internal router to route un-faulty function out of the cell. The proposed fault-tolerant FPGA architecture is comprised of Computation Tiles each of which consists of N computation cells which are able to heal from transient or permanent errors all at once. This architecture is centrally controlled by an on-chip fault-tolerant core whose main responsibility is to communicate with the external PC software, via UART interface, if an error occurs in any of the computation tile. The external PC software identifies and partially reconfigures the stem cells of faulty computation tile without intervening the functionality of rest of the device. The robust operation of a proposed architecture is implemented and verified on XILINX Virtex-5 FPGA device. The ratio of the hardware overhead to fault coverage in our approach is much lesser than that of TMR, [1] and [2]. From our proposed fault-tolerant scheme of utilizing the existing routing strategies together with partial reconfiguration of stem cells we achieved a number of benefits as compared to recently developed fault-tolerant FPGA architectures.

[1]. P. K. Lala, B. K. Kumar, and J. P. Parkerson, "On self-healing digital system design," ELSEVIER Microelectron. J., vol. 37, no. 4, pp. 353--362, Apr. 2006.

[2]. Kim, S. et al. "A Hierarchical Self-Repairing Architecture for Fast Fault Recovery of Digital Systems Inspired From Paralogous Gene Regulatory Circuits", IEEE Trans. Very Large Scale Integr. (VLSI) Syst. vol. PP, Issue. 99, pp. 1--14, Dec. 2011.
Digital Object Identifier: 10.1109/TVLSI.2011.2176544


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