 We will continue with our talks about and lectures about power estimation and controlling CMOS VLSI circuits and I repeat I am from IIT Bombay. Actually before I go to this what we did in our first talk was the following, we talked about generalities in which we showed the importance of power in case of CMOS and other CMOS circuits. We just discussed that systems like say mobile or many other systems do require low power performance, low power circuits and we also have circuits which requires high performance that is high speed circuits. But in either case one has to accept that the power reduction is always beneficial from variety of reasons as long as you do not lose on the given performance. So, in generalities we talked about many of these things particularly we talked about the power density increase as we scale down was increasing due to as we scale technology node. As technology node goes down from say 90 nanometers down or 0.13 micron down to 22 nanometer and below one of the worries right now to all of us is to increase in power density. So, in any case whether it is high performance or low power or low standby one has to reduce the power dissipation in the circuit for other reasons that the package which can remove the heat probably has to be now must get larger attention because at the end of the day the cooler the chip better is the performance. Today we shall continue with our system and we move now to our today's lecture and we will start with where the power dissipation is components of CMOS power dissipation and ok. So, we start with the CMOS power dissipation today and we will continue with this in the my next lecture as well particularly the effort to reduce the power dissipation. The four kinds of power are visible are written here which actually consumes power in the circuit which can uses CMOS circuits. First one of course is the dynamic power charging and discharging load capacitances. This of course which we will see soon that basically dynamic power is nothing but a switching power that means when the input of a CMOS circuit changes from 0 to 1 or 1 to 0 the output capacitances charges or discharges the load capacitance and charging a discharging current which is nothing but the displacement current due to the capacitor CDV by DT that into the voltage essentially gives the power which is consumed from the battery and how much is stored in the capacitance and how much is lost in the capacitance afterwards during other transitions is what is we discuss about in the case of dynamic power. The second and the one of the other important current which is worrying these days more often than earlier times is when the transition occurs from 0 to 1 or 1 to 0. We know in case of 0 to 1 inputs initially n channel CMOS transistor if you see this figure again. If you see the typical CMOS circuit which is shown here and this is my output load and this is my output this is my input and let us say I am going from this transition to 0 to 1 at that time initially the n channel transistor was off and p channel was fully on charging this capacitor to 3 D D. However when the transition occurs this transistor also turns on and this transistor starts from saturation starts to go to non saturation mode this wakes up into saturation and goes towards non saturation mode. So, at times when both transistors are on there is a connection between VDD and ground and this power dissipation essentially we call it short circuit current power descent due to short circuit current. That means both n channel p channel are turned on their status may be a saturator non-saturated depends on the input. However they will continue to till the transition is completed. Once the transition is input transition is over then there is no current really from the VDD to this except for the dynamic power current which is due to the capacitor charging or discharging. So, essentially we are saying that short circuit current will always occur in any CMOS circuit because of the transition itself. So, one can understand from their very simple thinking that if the transitions do not occur obviously there will be no short circuit current. So, it is no dynamic power. So, one of the method of reducing the power dissipation in circuit is to see that your data is such that it gives lesser transitions compared to the data which has larger transitions. Now, this of course how to code it is another area where low power circuits can be designed. The third possibility of current flowing in a CMOS circuit is bias circuit in analog circuit particularly which is not so much in digital or it does occur in even digital when we have an NMOS inverter which is rarely used but could be used. We have VG here, we have V in here, we have output here, we have VDD here, this is my output. This of course VG can be larger than VT of this N channel transistor. So, that it turns on but if VGS minus VT is less than V0 VDD we say it is in non saturation and if we connected to something like this the N channel load will always be in saturation. So, this is something NMOS inverter and in NMOS inverter except for when the V in exceeds below V in slightly lower than VT when both devices are off for all other case we can see a constant current can flow and that is called the static current in NMOS circuits. However, in CMOS this situation does not occur and therefore we can say always CMOS circuits are low power circuits compared to NMOS circuits. The fourth and the most worrisome current mechanism which is flowing in a CMOS circuit particularly which is worrying us most in a less than 90 nanometer nodes of technology circuits this is called the leakage current. What we assumes in a normal transistor if you have this transistor and let us say you are applying VG this is your drain as long as we say VG minus VS is greater than VT we say transistor is turned on. So, essentially what we say is on but we can also think of a case when VG minus VT is less than VT but greater than 0 under this case one assumes that device should have been switched off in in real life this does not occur this is essentially means this occurs as I said last time discussed that because the device is in sub threshold region and in sub threshold region they reach a current flowing even if VGS minus VGS is less than VT. Now this sub threshold current is essentially we shall discuss later it depends on the kinds of certain technology we use and at the temperature at which device operates and it increases in both cases. Now sub threshold leakage is a one of the major worries but the other leakage currents are always present in a MOS transistor. If you look at a typical MOS transistor one can see that a MOS transistor there is a source let us say it is an n channel transistor and there is a P substrate this is your gate oxide and this is your gate contact this is your drain and this is your source this is your bulk. So, we say if even if we ground the bulk this and if we apply VD drain positive voltage for n channel device at VDS and if source is also grounded you can see there is a NP diode here this is the N plus V diode here and this diode if you see clearly even if at 0 bias or this device is reverse bias and there is a leakage current in this device which may be essentially close to generation currents whereas in the case of heavily reverse bias diode there is a leakage path which is essentially the reverse bias diode leakage. So, whatever technology one uses this diode currents are going to be always present and at lower technology node the P may actually P doping may increase and in which case the leakage current will be further higher in the case of lower technology devices lower technology node devices because a lower technology node devices the substrate doping has to be increased to keep the VT within your check and that actually enhances the reverse bias diode leakage. And one can say that this diode current is essentially e to the power q mu by n k T minus 1 and this current is proportional to temperature larger the temperature larger is the current and therefore, larger the power dissipation in the chip this current also enhances over the time. So, this issue of leakage current is not trivial and the third possibility which is as we shall show you figure little later this since everything is scaling this oxide or insulator thickness is also scaling and if that is scaling below is less than say 20 or 30 amstrons which may be required for say 22 or 45 32 nanometer nodes then this gate oxide and since voltages are normally not scaling the field across these insulators are very high and prompting some carriers to tunnel through from the gate to the substrate or substrate to the gate and these are called tunneling through gate oxide. There is of course, additional current which is called gate induced in leakage which we shall see little later. So, we can see there are four kinds of power which we are worried about first is the dynamic power which as I say if you look at this dynamic power is essentially charging and discharging of the load capacitors. So, essentially current in this or current going out of this is C l d v 0 by d T and if you multiply it by v d d this is the power dissipation which is dynamic since it is time dependent it is called dynamic power dissipation. In the short circuit as I say except when the transition occurring at the input the current flows from v d t to the ground and that current we called short circuit current and the third of course, as I say static current which I keep saying is much smaller in the case of C mass there is a possibility of some current in the case large static current in the case of n mass and the fourth of course, is as I say diode leakage plus the sub threshold leakage plus the tunneling oxides they all constitute the leakage current. So, if I want to reduce the power dissipation obviously I must control all of them and try to see how much of these currents can be minimized at the technology nodes of our choice and that will decide the power dissipation. This is what I said already. So, here is a figure which shows dynamic power consumption we define a effective capacitance as alpha times the C 0. Now, this C 0 is the output capacitance at this node, but we have now introduced another term which is called alpha. Now, this alpha as we shall go ahead and look into this value this is essentially called the activity coefficient. So, what it means that depends on the input change whether it is 0 to 1 or 1 to 0 or no change when the data stream appears on this there will be transition in this or there will not be any transition yet. So, alpha essentially means how much times the capacitor in a cycle charges or discharges that how many times word is taken care through a factor called alpha which is called activity coefficients. Now, if you see activity coefficient we take care of that through the load capacitance we call effective load capacitance which is the net capacitance which we can define as the output capacitance times the alpha. Please remember alpha is not a constant quantity it varies with the data and therefore, C effective also varies with the data. So, for a switching power or the dynamic power is can be called essentially can be figured out and we will derive this expression in short while that C power dissipation due to dynamic power consumption is half C effective square V dd into fclk where fclk is the clock frequency at which the data is changing or 1 upon fclk is the period for which this input is actually retained or changed. Now, to reduce the dynamic power consumption this expression which we wrote half C effective V dd of course, one cannot reduce fclk because ultimate aim of any circuit these days is essentially the increase of clock frequency larger speeds is what is desired. Therefore, this essentially is going to increase as the technology is improving. So, we are trying to go for higher and higher frequency gigahertz and few gigahertz to higher gigahertz. However, if you reduce if you wish to reduce switching power then there are two terms which you must care take care of one of course, is the power supply. If you reduce V dd then of course, the square term and therefore, switching power will immediately go down as its proportional directly to square of V dd. However, we know in scaling of technology the everything else can be scaled, but it is not a constant voltage scaling it is not a constant field scaling it is a constant voltage scaling and voltage does not scale as much as the other dimensions and since V dd cannot be scaled down very much because of the noise considerations this V dd term is also not you cannot reduce very much because otherwise you will not be able to have enough currents also. Now, if you look at the third term which is C effective. So, obviously, one can reduce the power dissipation by using switching power dissipation if I say that I can reduce the C effective and essentially C effective also cannot be reduced directly as you see because C 0 is something fixed for the circuit. However, what we can change by a variety of ways is to change this alpha should go down and if alpha goes down then C effective goes down and if C effective goes down the net switching power will also go down. So, a typical CMOS inverter the power can dynamic power can be controlled or switching can be minimized by reducing the V dd and reducing the activity coefficient alpha. Now, of course, this word essentially why I wrote will be clear after I at the end of this this I will talk about other kinds of energy dissipations or other kinds of circuits which are called adiabatic circuit. This circuit which I am showing is called non adiabatic. Non adiabatic circuits are those according to law of thermodynamics. The adiabatic changes actually will always consume energy irrespective of because of law of thermo conservation of energy. Whereas, in the case of a non adiabatic in the case of adiabatic probably you know some thermodynamics what we are doing is we are reusing the energy stored once and therefore, one can say as if the net loss of power is much lower or you can say even theoretically saying it can be even 0 because we are reusing the energy ahead and therefore, you are never consuming or dissipating it. However, such adiabatic circuits were tried hard in many years ago and including this I myself have worked earlier with some few students. However, there are many issues in making adiabatic circuits they are better in as far as power is concerned, but they are not as good in speeds. However, in the case of DSP based circuits some of those can certainly can be implemented using adiabatic circuits. So, coming back to non adiabatic change when the power is going to dissipate here is a circuit shown here. This is some kind of a non linear storing non storing element this is like shown as a switch. This switch is essentially what we replicated by a MOS transistor or any other transistor and this is of course I keep saying it is a non linear and non storing element and whatever capacitance is associated with this or club apart from the external capacitance into a node external capacitor C plus the capacitance is due to whatever called non linear element used is C L. Now, the way transition occurs let us say I want to charge this capacitor. So, obviously, protrudes V d d I switch on the switch. So, I have a path from V d d to the capacitor. So, its current will flow through this and as its current through it will start charging this capacitor and the typical transient is shown here as t is equal to 0. So, there is no voltage on this capacitor and as you increase this is V t graph. So, as you increase time the capacitor and switches on you can see from here capacitance start charging and it reaches the voltage maximum reaches to the V d d that means whole V d d then will appear across the capacitor. Table wise we can say in time at t is equal to 0 V t at this capacitor is 0. There is no charge stored in the capacitor and there is no stored energy anywhere. Please remember capacitor is a storage element of the charge and therefore energy. Please remember Q into V is capacitor, but Q into V is energy and therefore any Q is equal to C V. So, essentially we saying C V square will be energy term. So, we can see from here this figure at t is equal to 0 V t is 0 and no energy storage no charge on the capacitor. However, as the transient goes from 0 to time t which is the period the capacitor charges to full V d d at t is equal to t therefore V t is V d d and the charge is Q is equal to C V, C is equal to this capacitor into V d d and the energy stored on the capacitor as we can easily find out by integrating this is half C V d d square. So, this is how the transient will actually lead to. So, you have a when your output is charging from 0 to 1 essentially you are storing an energy of C V d d C V d d square the word which I said can be derived mathematically as well. This is the same figure again this is my power supply this is the switch which is turned on at t is equal to 0 and please remember I repeatedly saying it is a non-linear because most transistors which will use the switch have a non-linear characteristics, but they do not store and the storing element part of that has been taken care in this net output capacitance. So, initially if you want to know how much is energy stored over a time t then we know the method is Q V is essentially the energy and stored from charge is stored going from let us say total charge at the end of t is equal to t is Q then we say energy stored in time t is 0 to Q V t d Q, but we know Q is equal to C V. So, if I substitute there d Q is equal to C d V. So, if I get this d Q replaced by C then the voltage goes from for the getting from 0 to Q is a voltage goes from 0 to V d d. So, we integrate it from 0 to V d d times V t V d V and if I integrate this simply then it becomes half C V d d square. So, energy stored from by connecting the power supply to the capacitor through a switch in time t stores an energy which is equal to half C V d square. However, this is not the power supplied by the battery. Let us look at the battery power, battery is here which has a power voltage of V d d. So, we want to see what is the supplied power in given time. So, it is a voltage is always full going up to this and the net charge at this point when it reaches full charge then the energy which actually power supply is going to give you is V d times Q, but Q is essentially the capacitance into V d d. So, which is C V d d square. We have said that the energy supplied by the power supply is C V d d square whereas power stored in the capacitor is half C V d d square when the transient goes from 0 to 1 at the output. So, one can see that supplied this is almost double that what is being stored which essentially is trying to see where the rest of the power going. So, obviously this energy is getting dissipated you are actually supplying C V d d square you are storing only half C V d d square which means rest of it half C V d d square energy is dissipated in this now where does this dissipation can take place. Capacitance is essentially we call non dissipating element as far as the heat is concerned I am not saying there is no ionization loss, but practically that loss is much smaller. So, obviously the power which is being dissipated if it is not here obviously it must be here because if the power supply is giving C V d d square half C V d square coming here the non-linear non-storing element must dissipate a power of half C V d d square and I already said that this non-linear non-storing element is nothing but going to be your MOS or any other transistor switch. The power is dissipated in your device which is your acting as a switch which is equal to half C V d d square. Now, many queries are asked that why C MOS? So, we already seen few minutes ago that in N MOS there is always a static current flowing when the transistor is then channel transistor is driver transistor is on and for all the rest of the transition it continues to conduct the current. So, since N MOS will always be high power dissipating circuit full N MOS circuit therefore, we look for circuit which are intrinsically low power dissipating circuit. So, it is found that since input in the case of input is static there is no power consumption if there is no transient the V d d to ground path is always broken in the case of C MOS when V in is 0 P MOS is conducting, but N MOS is switched off therefore, no current at least no leakage a leakage current exist, but no dynamic current or no static current flows if V in is 1 then this device turns off this device turns on, but since there is no connection between V d d v s in either case. So, if the input is either 0 or 1 there is no power dissipation as far as switching is concerned. Now, our static current is concerned however, we know when the transient occurs this status will change and then there will be a short circuit current. Now, why C MOS is the other reason is that the world over last 30 years has switched over from N MOS to C MOS for main majority of course, was because of the power and it has become a standard technology for almost all VLSI systems in the market barring exceptional there are some by C MOS circuits there are also by bipolar circuits also in the market for very very strategic application where speed is the only criteria that is high performance circuits. Other than this for almost every circuit you are actually looking into many systems which you use everyone is using C MOS what we probably are changing is the material possibility for instead of silicon we may use something instead of silicon dioxide we may use high case in the case of instead of silicon we may try germanium we may try gallium arsenide or a host of 3 5 2 6 compounds. We can modify the structure of gate P MOS or N MOS by making it fin fed, but in either case the basic circuit component will remain P MOS N MOS as a complementary and this basic block will remain constant for this. Now, having worked 30 years almost everyone of us have now realized how to design circuit using C MOS and therefore, the ease of design the availability of cells already are IPs available in C MOS everyone will still continue to use C MOS for next 10 to 15 years take a word from me. Now, to summarize before we go ahead individual power let me tell you what are the power consumption in C MOS. Net power consumption is divided into two parts one we call as active power the other we call standby power. The active power essentially has two part one is that so called dynamic power which is capacitor charge disturbed which is essentially what we say switching power and other of course, when the transients goes through both N channel P channel turns on for a while during that transient and we have a short circuit current. The capacity current also stands from the variety of regions of a C MOS circuit for example, the capacitance contribution comes strongly these days from the interconnects interconnects are of course, are the lines metal lines which are running on an insulator. For example, if this is your silicon I may have a insulating field oxide on the top and on the top of this my interconnect line metal line may run please remember the current is or the signal is going in this metal line, but it does see metal oxide semiconductor. So, you have an MOS capacitor sitting for this and the capacitor value will be decided by the length and the thickness and the width of this metal line. For example, if you see three dimensional picture this is your metal line this is your metal thickness. Now, the resistance is decided by rho L by A of this the current may be flowing on this, but there is an insulator below here there is a semiconductor below here this is your metal. So, depending on the length of this and also the width of the metal line this is the area of the metal line of sitting on the oxide. So, a MOS capacitor which may called C interconnect will be epsilon 0 into K s K s is that of whatever semiconductor used into upon the oxide thickness or insulator thickness whichever insulator I use multiplied by area of the metal which area here is L into W. So, one can see from here that larger the larger the current larger the L and W or longer the length of interconnect I use larger capacitance will be actually occurring at the node of the output and therefore, large capacitive effect can be seen and hence larger the capacitor we already said larger the capacitance and larger is the active power dissipation. The other of course, is the gate has an capacitor sitting there C ox and therefore, that capacitance is also contributing to the net capacitance and finally, as I said there are other parasitic capacitance MOS transistor which are essentially due to the diodes there and those are called internal diffusion capacitance. So, drain to bulk source to bulk or the capacitances or gate to drain and gate to source or the other parasitic capacitances which also will be attracted we also be connected at the output node or any capacity output node and therefore, add to the net capacitance larger the capacitance larger is the consumption. If you look at the other side which we called as a standby power we are two possible two source of power dissipation which standby standby essentially circuit is on, but not acting what does that mean like a mobile you keep it on a standby mode whenever thus you actually send the you talk on your phone or mobile phone or you receive a phone any call at that time the circuit is switched on fully and the power is as much as active power. However, even if you are not using the phone for any such purpose the device remains on for a while because otherwise you cannot bring the on state faster than when the someone calls or you want to call. So, this has to be kept in standby mode and that standby power is essentially because the two leakage meant of course, there are multiple leakage as we shall see later, but there is a sub threshold current and the diode leakage current which actually keep constantly leaking the current and battery has to keep supplying that power this is called the standby power. So, in a normal CMOS circuit I would say there are three components the total power dissipation can be due to switching due to short circuit and due to leakage. In our older technology and that is why I brought this numbers please remember I repeat switching power is essentially charging discharging of capacitor which is essentially dynamic power consumption then this half CV square into of course, time for which it switch we shall see that the P short circuit is essentially due to the direct path between power supply and ground when the transient goes through the input of a CMOS circuit. And finally, there is a leakage due to leaking diodes and transistors, but you can see till very late till as to as till 95 to 98 kind of times we the technology was just we are going below 0.13 or around that time we are still below 100 nanometers above 900 nanometers. The most of the power one sees is essentially the dynamic power which is 75 percent. The short circuit data dependent power dissipation is 20 percent and finally, there is a diode leakage current which was 5 percent and actually it is here we shall see later when the technology node is going down from 90 nanometer to 22 or below this power actually may over power both of these and our worry starts then because if this is larger than the sum of the right now this is 95 percent and this is 5 percent. It has been observed that this may become 66 percent and that these two together may give 33 percent which is very bad because essentially you mean even if you are in a standby mode you will consume much more power and the effort has to be reduction in leakage powers. However, till such time we come to that we will discuss right now as if to reduce dynamic power we must work out because this is 75 percent power which is going in the dynamic power or switching power. Of course, we also should look for how good we can reduce this 20 percent power though in many a time this power reduction is not so very easy as we shall see later. So, a typical basic CMOS gate is shown here a CMOS gate is driving another CMOS gate which are same size W Y L for both N channel P channel and can be circuit wise made equivalent of a capacitance at the output node is equal to CDD as capacitance bunched at the output node equal to CDD to the power supply and other capacitance is the C G and D which is to capacitance going this is equivalent of net capacitance which includes parasitic and every other capacitance at this node because of this because of this because of the bulk to this because of this plus the capacitance due to this at this node. So, and the interconnect all these capacitances are can be taken care by two such capacitance we say one going from output node to the power supply capacitance the other is going from output node to the ground which we call C G and D. So, if you do an inverted analysis as shown here if we are doing a transition from 1 to 0 as shown here and the output going from 0 to 1 due to the inverter action one can see there are three energy consumed energy dissipated and energy stored. So, power supply is going to give the C ground V D D square as the power supply give due to charging then we can say half C V D D square will be stored this dissipated and half C ground V D D square will be essentially stored on this other power is lost on this whereas, if you have a discharge transition this is the only power. So, we say dissipation is only this much that is half when the output is going from 0 to 1. So, this is the only loop which we can see. So, we have the power dissipation of C ground V D D square. Now, continuing with this if the transition is opposite C V in 0 to 1 and this is 1 to 0, but the numbers do not change because essentially we are saying there it was C ground here it becomes C V D D and in most cases these two capacitances are same by design and therefore, one can see the C even if you call it C D D as C ground does not matter. So, we call C V D D square half C V D D square half C V D D half C. So, essentially if the transistor are identical and matched to a W by L. So, that the mobility difference is taken care or mobility ratio is taken care irrespective what you do whether you make a transition from 0 to 1 or 1 to 0 at the output or the input the power given by the power supply is C V D D square and power consumed by the devices half C V square and power stored on the capacitances is half C V square. So, we are just talked about energy consumed due to complete cycle going from say 0 to 1 and 1 to 0 this is the complete transition. So, in a one cycle time we have one transition powered energy dissipation due to 0 to 1 and the other dissipation is due to 1 to 0 and we add this C V square terms C ground plus C D D into V D D square and typically this is what the C 0 term which say output capacitance at that node which is nothing, but some of C D D plus C ground and one can also see from here that this C 0 multiplied by the activity coefficient. How many times the input changes 0 to 1 or 1 output changes 1 to 0 or vice versa we call one cycle time in one cycle time the power essentially is C 0 V D D square this remember we are talking of one cycle time, but if the data is coming in number of cycles what is the power dissipation or E cycle available to us. Now, the next term for all power people is essentially called power delay product which is we say that average power multiplied by the average propagation delay T P D the product of these two is called the PDP and it is normally for a given gate topology and for a given technology this may remain constant. This is very important because we actually PDP is something if I show you some interesting figure which shows if I plot power or whatever we say power versus delay tau then when I say it is P tau constant we are essentially running on this line which essentially means if you have a larger delay that is slower speed and this is your power if you have a smaller delay obviously power is larger if you have a larger delay or slower circuit you have a lower power. This is essentially the figure of merit because once now whatever you do you can move on this line only and therefore larger the power smaller is the delays larger the delay smaller is the power. However, the effort should be you know maybe some other technology may or somehow method we may have larger P tau you may have even larger P tau or you may have technology in which you have reducing P tau and if that occurs one can say for a smaller delay you will have relatively is compared to this smaller delay itself you may have a smaller power. So, the effort in low power circuit is not only to look at other options all other options depending on the topology see a switching transient something we also look into different technology nodes or different technology methods like using one can say using H HEMS you can use it using gallium arsenide indium arsenide kind of H EMTs or you can use other technology semiconductor technologies to reduce this P tau lines from the let us say if this was your CMOS standard silicon I want to go below so I must do something in which PDP remains which is essentially joules this energy PDP is essentially energy. So, this is a energy constant energy graph shown to you here per switching event and therefore, the effort in the technology or effort in this all low power circuit design is to reduce if possible in a P tau, but in a standard CMOS circuit P tau will remain constant and therefore, the worries start that if then if I want to reduce power and do not want to given in speed that is I want to keep PDP is constant what are the methods of what can I do that I can fool the circuit and therefore, it can say I have lower power a lower energy consumed. Now, let us look at the dynamic power once again which is related to battery we can see that average power consumption by node cycling at each period T that is each period we call it first transition 0 to 1 and the next is from 1 to 0 that means, you are coming going from 0 to 1 and returning to 0 is called one transition or one period of a transition. So, we switching which is we are just calculated switching energy which is we call E cycle which is C 0 V d d square and if you have T cycles in which average has to be figured out we divided by T and 1 upon T is nothing, but the clock frequency T is the period means 1 upon T is the clock frequency which is changing the data or the period of the pulses coming in. So, we say the switching battery a switching battery power is C 0 V d d square into FCL key, but this is essentially coming from the battery. Now, average power consumed by node with partial activity I already talked about this term alpha which is called the activity coefficient if alpha is not 1 that is every clock cycle there is no transition that means, one cannot say that every data which is let us say I have 1 1 1 0. So, the if first input is 0 it gives some power the next transition is next input is 1. So, there will be a transition from 1 to 0 at the output and 0 to 1 at the input. However, next 2 bits 1 and 1 will not change input or not change the output and therefore, there will not be any charging or discharging of capacitors and therefore, there will be activity will be 1 out of the 4 possibilities and therefore, alpha will be very small may be 1 4th sometimes 1 3rd sometimes 1 half depends on the how much activity it happens in a given cycle. Now, this essentially alpha is the only thing which probably we should look very carefully in our power design a low power design because this we cannot play too much this of course, is essentially decided by W Biles which we are kept for transistors for noise margin consideration for the speed consideration power. So, if f c l k is some way connect is already fixed then the only way switching energy can be minimized or power supply has to give lower energies to make alpha smaller. So, we therefore, we started with this slide we say therefore, the capacitance which this output node has to see for an inverter is alpha times c 0 and the switching power then can be half instead of c 0 we write half c effective V d d f c square. So, we come back now and say to minimize this switching power or dynamic power all that we can do is to make this V d d across power supply which is charging this capacitance to full V d d if that is reduced square times the power will go down under root of that or since clock we want to increase. So, we cannot do much on this the only way you can reduce power switching power is reducing the c effective and reduce c effective essentially because this is also constant. So, only thing we reduce is the activity coefficient which is alpha. So, there are four factors which influences c if alpha I was just talking of one of them one of course, is called circuit function the other is circuit technology the third is input probabilities and the fourth is the topology of the circuit you lay. So, depending on the four such functions c effective can be different and if the c effective is different then the power dissipation will be different. Before we continue with this activity part we like to first define few basic terms two terms of interest for us in a case of data flowing from input to output which we call signal. If we have we call a term signal probability of a signal g t is given by p g which is probability term of g of the signal can be if t is the period then limit of t tends to infinity 1 upon t minus t by 2 to plus t by 2 g t t t. Now, this essentially means g t essentially is the signal it is 0 1 1 0 whatever it is. So, if you average it in any one time period that is called the probability of getting 0 or probability getting 1. So, this is p g which is most important because signal can be either 0 or 1. So, one can get a probability of getting output 1 or output 0 by using this kind of simple calculations or simple averaging. The another term which we use often in the power dissipation valuations for c effective or alpha is signal activity of a logic signal g t is given by a g which is limit of t tends to infinity 1 upon t again because averaging you are doing n g of t. Now, n g is essentially we call activity the word I have said n g is the number of transitions of g t in the time interval between minus t by 2 to plus t by 2. How many times input changes at the or output changes is called its activity. So, we have a signal activity of a logic signal g t given by a g limit of t tends to infinity n g t by t whereas, we have signal probability of a signal g t is given by limit t tends to infinity 1 upon t minus t by 2 g t d t. So, what is why we are looking because we want to calculate the probability of any gate of for their transitions and if that we evaluate then we know how much is alpha and if we know our alpha we know our c effective. So, here is before we go further things quickly few of the things may be of interest to you. Assume that there are n mutually independent signals that is g 1 g 2 g m or that means, if g 1 changes g 2 or 2 g m need not change or vice versa. So, each is independent signal which is normally will appear data may appear independently from variety of at variety of inputs. Now, each of have a signal probability p i that is p 1 p 2 p 3 p n and a signal activity a j a i which is i has to be less than n where n is the number of input gates input of that. Now, we define further for a static CMOS the first because they are different variety of CMOS possibilities static dynamic among dynamic also we have variety of choices C domino CMOS modifier domino zipper and variety of them. So, we first look for static which is most basic CMOS circuit and which gives you basically the idea how to reduce or how to understand the CMOS circuit behavior. So, for a static CMOS the signal probability at the output of a gate is determined according to probability of 1 1's or 0's in the logic description. For example, here in inverter if you have 1 here you are going to get 0, but since it is a binary number 0 is nothing but 1 minus 1 and therefore, it is a 0. So, we say probability of occurring at input 1 at inverter then the probability of getting a 0 at the output is nothing but 1 minus probability of occurring 1 at this input. Please remember 0 is complementary of 1 and therefore, in the binary system therefore, if this is the probability of occurring 1 1 minus p 1 is the probability occurring 0 at the output. So, inverter is essentially acting like an inverter if there is a probability of 1 here to occur then there will be 1 minus p 1 probability is to occur 0 at the output due to inverting action. Look at the gates you have a simple 2 input NAND and let us say p 1 is the probability of having 1 at the input or p 2 which is probability of having 1 at the input then the probability that 1 will be occurring will be p 1 into p 2. Now, this can be understood easily you can see from here in a AND gate if your 2 inputs you have a AND gate x and y and you have z. So, if I write it to table x, y and z possible combinations is a 2 bit number. So, 0 1 1 0 1 1 and it is a AND function. So, this is 0, this is 0, this is 0, this is 1. So, you can see from here AND gate has only 1 probability only 1 out of 4 possibility of getting 1 only when inputs x and y are 1 whereas for any other inputs combination 0 0 or 0 1 or 1 0 1 c is the output going 0. So, if we have a probability of p 1 getting 1 is this and p 2 getting 1 then the p 1 p 2 is 1 if any one of the probabilities for p 1 is 0 then the output will be 0. So, essentially we know this is like a Boolean algebra probability is multiplied. So, for a AND gate this is a intersection of p 1 and p 2. Therefore, we say if p 1 is the probability of first input having 1 if the p 2 is the probability of getting second input 1 then the probability of occurrence of 1 at the output is p 1 into p 2 which is the product of the two probabilities and which is visible from here that if you have only 1 1 1's if any one of them is 0 the output is going to be 0 which is what AND gate function is. By similar logic one can see if you have a OR gate to input OR gate again x y and y z and I make again table say z AND we said we now z OR we write. So, we now we know x and y for a OR gate 0 0 is 0 0 1 is 1 1 1. So, in a OR gate occurrence of 0 is very little whereas, occurrence of 1 is more likely to have an except only once when x z 0 and y 0 the output goes to 0. So, if you look at the probability p 1 and p 2 are the occurrence of probability occurrence of 1 at inputs then the occurrence of output being 1 is probability 1 minus and 1 minus p was is the 0 1 minus p 2 is another 0. So, whenever there is a one of them is 1 the other term will essentially 1 minus p 1 let us say p 1 is 1 then that becomes 0 p 2 is 1 that becomes. So, p 1 output is 1 for all other cases one can see the output may become 0 which essentially means the probability of occurrence of 1 is 1 minus 1 minus p 1 into 1 minus p 2 which is occurrence of 0. So, you subtract the occurrence of 0s out of from the occurrence of 1 probability wise occurring. So, it is 1 minus the product of 1 minus p 1 into product of 1 minus p 2 which are the probability of getting 0s due to p 1 and p 2 you subtract that probability the remainder is getting a 1 at the output. Now, this is very important because now we are trying to see that the probability of which kind of inputs you have will decide what kind of what is the probability of getting 1 or 0 and if there are no transitions therefore required then in that case there will not be any power consumption. So, let us look at some numbers some theory again if you have a NOR gate shown here then we see this is x 1 x 2 for p channel inputs and x 1 x 2 in a OR mode for the n channel inputs and we call this node 1 this node 2 this node 3 and we are taking an output at 3 and this is 0th node which is ground. Now, what is a NOR function as long as any one of this input is 1 the output is going to be 0 only when this is a NOR function only when both of them are 0 the output at that time both p channel will be on and therefore output may go to 1. If any one of them is 1 the VDD is taken away if any if both of them are 0 of only then 0 is taken away. So, it is more likely that if either x 1 is 1 and x 2 is 1 both are conducting if x 1 is 0, but x 2 is 1 this will conduct if x 2 is 0 x 1 is 1. So, this will conduct, but in either case either this conducts or this conducts. So, power supply is removed for the three cases from the output node whereas in the case when x 1 is 0 and x 2 is 0 there is no path from output to the ground fortunately because of complement reaction both p channel receives input 0 0 which makes this transfer turn on and VDD is then transferred to if 3 or 1 is transferred. So, we now see the transistor connected to the same input are turning on and off simultaneously when the input changes. Please remember transistor connected to the same input are turning on and off simultaneously when the input changes. The capacitance load of static CMOS gate is charged to VDD at any time when the 0 to 1 transition occurs when 0 to 1 transition occurs the capacitor is pre charged to this. CL of a static CMOS gate is discharged to a ground by any time 1 to 0 transition occurs if this was 1 and we want to go to 0 either through this or through this or both together I can bring this to turn to 0. So, now you can see the effective capacitance at x 3 in the different kinds of input will have different kinds of are available to it essentially means the time constant will be different for each cases and therefore the currents will be different and if the currents are different then the dynamic power will be different. Take another example from here we see you have a two input NOR gate which is shown here which has two inputs A and B another output pi assume only one input transition per cycle is allowed that is A may go to 1 and that time B may not in that transition. So, allow only one input transition per cycle is allowed assume inputs are equiprobable that means there is a possibility of change of inputs is equal that is getting one on A and one on B is equal because they are same inputs that is they may not be, but in this case we assume they are same. So, we say each has a probability of occurrence of half the probability half because other time it may be 0 either it is 1 or either otherwise it is 0 and therefore the probability is half for both P A and P B. The probability for the output to be 1 which we call P y is since it is going to be NOR function. So, you must get probability of occurring 1 is 1 minus P A is for the 0 1 minus P B is for the 0 which 0 should probability we find out for that this is 1 minus P A is half 1 minus P B is half and therefore output becomes 1 by 4 probability is 1 by 4 at y. However, if the probability of finding a 0 at the output you are looking for then just subtract 1 minus P y from this we calculated. So, remainder probability of getting 0 is 3 by 4 you can get from here for the same circuit if I put Z NOR for this. Now, one can see this is what is the Z NOR since this is Z NOR you can see out of 4 you have probability of getting 3 0's. So, you have a probability of getting 0 is 3 by 4 whereas probability of getting 1 is only 1 out of 4. So, it is 1 by 4. So, why we use we can always see it from the truth table. However, since the functions may not be 2 input or 3 input may be larger inputs evaluation of such probabilities with best left to a simple formulation rather than actually looking at the truth table and then finding the is that clear if for a Z NOR occurrence of 1 out of the 4 possible output is only 1 by 4 whereas occurrence of 0 is 3 times that. So, 3 by 4 and therefore, one now knows that a probability of output to be 0 is 3 by 4 probability of occurring of 1 is 1 by 4 for a NOR gate. We actually now look into factors influencing C effective continuing with that and we still believe that we are working on static CMOS. Here is what the same NOR gate representations can be shown on a finite state machine kind of transition table or transition diagram. Let us say there are 2 states in this system you are in a state 0 or you are state at the state at 1 and O is output. So, if you see you are in a state 0 then and you are making a transition to state 1 please remember 0 to 0 occurrence as a probability of 3 by 4, 1 occurrence as a probability of 1 by 4. So, we say when you are making a transition between 0 to 1 the net probability is 3 by 4 into 1 by 4 which is 360. If you are going a transition from 1 to 0 which is again same 1 by 4 into 3 by 4 360. However, if you are making a transition from 0 to 0 since 0 has a probability of three fourth then the probability of going from 0 to 0 is 3 by 4 into 3 by 4 which is 916 by same logic. If the probability is you are going from transition of 1 to 1 then the probability of occurrence is 1 by 4 into 1 by 4 is 116. So, obviously you can see getting 0's are much larger probability 9 by 16 compared to 1 by 16 for 1 to 1 transitions. So, if we want to define our activity coefficient one can say that occurrence p y dash which is 1 minus p y times p y plus p y times 1 minus p y in if I substitute from here 3 by 16 plus 3 by 16 then it is alpha is 3 by 8. So, I can evaluate the activity coefficient of a NOR gate which as I said by the truth table has the largest probability of getting 0 whereas, smaller probability of getting 1 the activity coefficient is 3 eighths. Please remember this 3 eighths will now get multiplied to see effective and in all our effort is to see for different kinds of gates we may evaluate alpha and whichever gives smaller alpha then one can see from here smaller is the alpha, smaller is the see effective and smaller is the switching power. So, effort in design you can now understand is to see to it that the transitions are such that the gates you use are such that their activity coefficient for the same data inputs is smaller and that is one way of reducing the power dissipation. Now, take a dynamic circuit which we have talked about so far only static, but when can see from here a dynamic circuit a slightly better dynamic circuit has been shown here typical CMOS dynamic circuit looks something like this you have p channel device you have for a NOR gate you have 2 n channel devices 2 inputs x and y and then you have another CMOS device n MOS device and this is your p MOS which is dynamically controlling through a clock which is phi this is your power supply and this is your v out of course, you have a capacitance here. Now, one can see from here the z output here is decided by dynamic circuit in the same sense because when phi is equal to 0 this n channel is off when phi is equal to 0 we call it say m 1 m 2 m 3 m 4 for any input m 2 for any input m 2 m 4 for any input x and y if phi 0 m 1 is off and m 2 is on. Since this is off and this is on the and it this may conduct or may not conduct depending on x and y value, but the ground is removed because phi is 0 and if that occurs there is the current may start from power supply through m 4 and will charge the load capacitance. So, you have a charging transient when phi is going from 0 to 1. So, you will it will go to v d d towards v d d when phi goes to 1 and your x and y can now change or earlier whatever they can now change and that occurs between phi 0 and phi 1 then now m 4 is off 1 means logical ones m 4 is off m 1 is on now fully on. So, this depending on the logic requirement whether you want a 0 or 1 if let say you want 0 that means x must be 1 or y must be 1 or both may be 1 only then 1 of the 2 transistors or both of them will be on and the capacitance will discharge through this path, but if say x is equal to 0 and y is equal to 0 m 2 m 3 will be switched off anyway and for whatever this charge it will retain the charge which was v d d due to the v d d therefore, 1 will be retained. So, now you can see in a clock cycle phi is equal to 0 this is dynamic in that sense the power is decided by it is not just decided by this logic, but also decided by the timing given to phi and because this is dynamically at no time these and these 2 are on that is m 4 and m 1 are on clearly one sees that the power dissipation will be smaller at least transition there will not be any switching because at no time all 4 will be actually acting and therefore, the chain will be always be broken and therefore, there will not be any what we call as switching not switching this short circuit power. Now, this is called pre charge mode when phi is 0 m 2 is on you should be pre charged to v d d and when depending on x and 1. Now, this the circuit shown here in my figure you can see I have removed the lower end channel the reason why we remove end channel anyway end channel was providing you a ground path. So, we kept them ground directly to the the only problem little more power it may consume at some once a while because if either of the input x and y is 1 and even if your phi is 0 part of the power will go to the ground through x or y inputs or those transistors because any one of them is 1 logically so, then the important thing there is that whenever such circuits are used the inputs are always initially 0 and they are changed when the phi goes to 1 for the pull up if that occurs the power pre charged occurs when phi is 0 and when phi is equal to 1 the pull up transistor switches off and the logic is s per x and y. Now, this dynamic CMOS has lower number of transistors sometimes little more short circuit power it may create, but it has overall low power compared to many other dynamics gates. So, this circuit which is a NOR gate again with as I say the lower transistor has been taken off can also give you comparatively lower c effective because now the transitions will be smaller and for a NOR gate and if that occurs the net c effective with a lower per cycle transition can lead to a lower c effective and therefore, low power dynamic power. So, this is very interesting that you use a dynamic power dynamic circuit then you have much lower comparatively lower power compared to static CMOS. If you are using a dynamic CMOS and you have in again the same circuit as I shown here and we still assume that they have a occurring 1 at here is probability of half and we also know in the case of dynamic there is only 1 input transition per cycle is allowed you cannot change all of them only 1 at a time. The probability of our output to be discharged is 3 by 4 because 1 of the input may be 1 and therefore, they it will create a path to create a 3 4th if both of them inputs are 0 only then the output is high remains the probability of c l to be recharged in the next cycle is p gamma dash which is nothing but 1 minus p gamma p y. So, essentially it is 1 4th. So, in nutshell what we can say about the dynamic circuit versus static circuit following things can be thought of. We say alpha dynamic CMOS alpha means activity coefficient for dynamic CMOS may look to be little larger compared to static CMOS. However, the c effective of a dynamic CMOS even if because the net capacity is only smaller in this case. So, c effective for static CMOS is always larger than c effective for dynamic CMOS. So, what is our important is that c effective should be reduced. So, in a dynamic CMOS circuits since we are reducing c effective overall we figure it out that it can become little low power compared to static CMOS. Now, power due to glitching is much smaller in dynamics at the glitch does not occur because all transitions are not allowed during the phi or whether the when the phi is constant. If phi is 0 or phi is 1 only then the inputs are allowed to change and because this is a constraint at no time we did it to ground path can be created. So, there is no glitch is possible in a dynamic CMOS which in a static CMOS it can occur because as soon as any input changes both n n channel n channel and combinator p channel will change its status and because of that there is a possibility of glitch. In static CMOS the transition probability depends on both input probabilities and the previous state where we are just calculated that. In the case of dynamic CMOS the transition probabilities essentially only depends on the input probability and nothing to do with the output probability because you are already in the pre charge mode either to charge or not to either to remain charged or to discharge is only one possibility and therefore, one can say that in a dynamic CMOS transition probability depends only on the inputs and not at the output. In static CMOS the gate output does not switch if the inputs do not change that is most important between the cycles. In dynamic CMOS the gate output may still switch if the inputs do not change between subsequent cycles because 5 5 0 that is p channel n channel dynamic part may still switch on and off and the output may still go to 0 to 1 or 1 to 0 in either case. So, there is some disadvantage in dynamic CMOS that input change even if input do not change output can change whereas in static unless input changes output cannot change. By similar logic one can use a complex gate not simply NAND nor or anything any of the complex circuit using CMOS and we can always biological effort can see its equivalent inverter action and then for can calculate the alpha the main difference is the switching activity for any complex gate. So, we must evaluate alpha for such gates switching activity is strong function of logic. So, which logic you are implementing that decides the switching activity and energy drawn from the power supply when output transition is low to high that is how charging we can say for static CMOS please remember power supply only gives in the half cycle when the it is charging the capacity. So, energy is only drawn when you are pre charged in your pre charged system in during the evaluation phase there is no power supply requirements and therefore, you are reducing the power supply supplied by the power supply in the case of dynamic CMOS. For static CMOS with independent inputs probability of low to high transition is probability of output low in n times probability output high in the n plus 1 time this we shall see by example and you will understand what I meant. Now, here is a for any complex gate activity we say alpha is activity coefficient for CMOS complex gate alpha going from 0 to 1 if you have probability of getting 0 is P 0 and probability of getting a 1 is P 1 then and we know P 1 is nothing but 1 minus P 0. So, we say alpha 0 to 1 is P 0 1 minus P 0. Now, again same assumption we make assuming inputs are independent and they can be separately controlled and they are uniformly distributed in an n input static gate has transition probability from 0 to 1 where if n 0 is the number of 0 then n was the number of 1 in the 2 table column output column that is z or y whatever we say then we can see from here n 0 by 2 to the power n multiplied out of 2 to the power n let us say you have a 2 bit number. So, n is 2. So, you are 2 to the power 2 means 4 if n number of 0s are let us say you have a 2 bit possibility is you are 0 0 0 1 1 so, 1 can see n 0 divided by how many 0s you have at this columns divided by the 4 because as I said last time in an OR gate we are 3 0s and 1 1s or vice versa OR gate. So, in which case out of 4 possibilities only 1 0 or 1 3 times 1 is possible. So, the product of getting 0 or 1 out of 2 to the power n possible combinations is called alpha since n 1 is nothing but number of 1s in 2 table which must be total possible combination of bits minus the n 0 so to the power this. So, I now can evaluate for any input let us say n is 2 2 bit number the 2 to the power 2 is 4 we can see from here. So, it is 2 into 2 to the power 4 that is 16 let us say number of 0s are 2 3 then this is 2 to the power 2 is 4 4 minus 3 is 1. So, it is 3 by 16 is the probability of alpha going to 0 to 1 by similar logic for a NAND gate it will be n 0s will be different. So, whatever number of inputs you have whatever complex gate you create alpha 0 to 1 and similarly alpha 1 to 0 can be attained in this simple formulations. Please remember n 0 is number of 0s in the 2 table output column that is y and n 1 is number of 1s in 2 table at the output. Since I can therefore fundamental activity factor alpha for 0 to 1 or 1 to 0 can be found per cycle I can find out the c effective and if I know my c effective I can get minus. So, we may actually stop here for today, but we may just give you the last this slide which I repeat I will repeat next time. We have first time we looked into whether to use static CMOS or to use dynamic CMOS now to improve the c effective that is reduce the c effective or impact we looked into. Now, next thing which we like to look into is the topology of the circuit has anything to do with the c effective to some extent we have worked out this kind of chain and tree circuit in our logical effort part. Now, we like to see this and this may give you same logic. However, we like to see what is the activity coefficient alpha for this and what is the activity coefficient for this if this gives you lower alpha or this gives you lower alpha then we can use one of this chain or see tree circuit to implement your logic. Please remember logic remains same from input to output in either case either you can represent in this tree form or you can have a chain of circuit as shown here and the output can still be same function as you are looking into. Now, this is a 4 input NAND gates you can have your 2 input 2 input or your 2 input 2 input 2 input now assume therefore, inputs a b c d. So, as I say a b here c d here or a b first then output with c and then output of this with d and then final output and we right now take a case when assume all static CMOS assume all inputs are equiprobables and can evaluate the alpha for these 2 circuits. Even if alpha as we have just I will do it again they seem to be same for either of the case, but one interesting feature of these 2 circuits probably if you have done logical effort properly. We have seen that if you have a chain of circuit the delays are larger whereas, because this has to wait to evaluate c into this there will be delay from this whereas, in this case this is equal delays this and these 2 will come together and therefore, the delay is minimum this is the 3 unit delay system this is 2 unit delay system. So, in even if their power is essentially similar as c effect is similar at least the speed wise this circuit will be larger as faster compared to this. So, depending on the power and speed requirements we not only look into the which kind of gates static or dynamic or complex dynamics we should use please remember dynamics are many possibilities as I said one is of course, static this simple dynamic then we call it domino then we call modified domino we have a norah or we have a zipper any possibility of dynamics CMOS can be tried and we will look into at least some of them later other possibilities of difference way of doing the same logic. So, with this we will conclude for the day and we will come back next time and we will start again influence of c effective on the circuit topology and influencing c effective which coming from circuit topology and we will see whether which one of the circuits should be chosen. So, that of course, there are issues which as this slide is showing which I will discuss it is called as Q problems. So, if the data is one particular you may line into skew though you may get better result otherwise with this kind of circuit we will look into the power again and therefore, we stop here today and we will we have learned so far in this this that the there are three kinds of power of or other four sometime but please three one is the dynamic power the second is the short circuit power and third is the leakage power we are still working right now on the dynamic power and to some extent inter automatically we are also looking into switching power I mean short circuit power we will look into more details about the leakage power separately with this thank you for the day and we will meet next time bye.