 So, today we will look at capacitance voltage characteristics of MOS capacitors. First we will consider an ideal MOS capacitor and hence we will first consider ideal CV characteristics and then we will consider a whole range of non idealities that one may encounter in capacitance voltage characteristic of MOS capacitors. So, in ideal CV characteristics we will look at two kinds of capacitance voltage curves one what we call high frequency CV and then low frequency CV. So, the device that we are considering here is as usual p type substrate silicon with a gate oxide Si O 2 of certain thickness T ox and a gate electrode of certain area. So, this is where you are applying your gate voltage and you know the substrate is at ground potential right this is a simple structure that we are considering and we are also making an assumption when I say ideal CV all it means is that I am making an assumption this capacitor has a flat band voltage of 0 volt ok which essentially means that I have a fictitious gate electrode whose work function is exactly aligned with the work function of silicon. Silicon being p type material you know its work function will be the electron affinity which is the distance between vacuum to the conduction band then half the band gap of silicon because permeable in p type silicon is below the mid gap and whatever that bulk potential is right. So, that is your work function on silicon I have chosen a metal which has exactly identical work function let us assume that and hence and also oxide is also ideal and hence V f B is 0 that is what I mean by ideal MOS capacitor CV characteristics. So, when I am measuring the CV characteristics essentially what I am really interested in is you see I am actually interested in variation of the capacitance with applied gate voltage. In other words if you have to think of a measurement setup what you really have is something like this ok this gate electrode is being excited by a DC voltage V DC plus an AC voltage and hence your V G is equal to V DC plus V AC. Now, when we say high frequency and low frequency capacitance all it means is that the capacitance is an AC quantity the frequency of measurement here you see can be very low or it can be very high what is low and what is high we will see in a few minutes little later right. So, what we are doing here then in order to do this kind of a measurement is that we will apply different DC gate voltages and at each DC gate voltage we will apply a very small signal AC. So, in other words if you were to look at your gate voltage V G as a function of time what you will see is that let us say I start from 0 and go towards positive right I mean we will typically start from negative and go towards positive right just for the illustration. So, at 0 this is a DC voltage and I have a very small AC and I do the measurement of the capacitance take a next step and apply again an AC and do the capacitance measurement and go to the next step and so on and so forth you see and hence at different DC values which is different gate voltage value on this MOS capacitor I am measuring the capacitance. So, this frequency of the measurement can be either low or high and that in turn gives you two different capacitance voltage curve which is H F and L F C V characteristics. Now, let us start from the very basic that if I have a V G applied on this structure as we have seen in one of the earlier lectures what you will essentially have in this structure it is can be treated as oxide in series with silicon right. So, the applied gate voltage has to draw across these two elements part of that will drop across the oxide that is what we call V ox and the rest of the gate applied gate voltage will drop across the silicon which is what we call psi s or the band bending that we have in silicon when we have flat band condition psi s is equal to 0 then whether you are applying positive gate voltage or negative gate voltage the bands will either bend down or bend up accordingly your psi s will becoming become non-zero becomes positive or negative. So, this can be further written as what is V ox you see V ox can be written simply as Q G divided by C ox plus psi s. Now, remember that this is a capacitor whenever I put a charge Q G on the gate that charge will be balanced perfectly by an equivalent charge in the semiconductor. So, we can also write Q G is equal to minus Q S where Q S is the charge in silicon because it is a capacitance right positive charge is balanced by the negative charge and this negative charge is in the silicon for positive applied gate voltage. Similarly, if you apply negative gate voltage you have negative charge in the gate that will have to be balanced by an equivalent opposite charge in the silicon. It is know sometimes you see in the books this notation either as Q S or as Q silicon one and the same right. So, I can now rewrite this as minus Q silicon divided by C ox plus psi s. So, let me just do a very simple mathematical operation on this equation what I am going to do is that differentiate this equation with respect to Q S. So, that is d V G over d Q S right is differentiate this right hand side with respect to Q S you know because Q S is again Q silicon right I mean I am using doing them interchangeably. So, this is Q silicon by C ox differentiate this what you get essentially get minus 1 over C ox first term correct because differential of Q silicon with respect to Q silicon is 1 right and plus d psi s by d Q silicon. Now, this is interesting now. So, what we are defining now see this C ox is a insulator capacitance. Now, these two quantities are really the total gate capacitance and the total silicon capacitance. In other words what we are saying here is that we define C silicon as minus d Q silicon by d psi s and similarly, we define the total gate capacitance which is being measured in the external world as minus d Q silicon by d V G right. So, I am defining this as minus in reality the capacitances are being defined as plus d Q G by d psi s that is silicon capacitance I am my excitation as a gate I am looking at how the gate charge is changing with respect to change in gate voltage because Q G is equal to minus Q psi I am making that substitution here directly right. So, what this is telling you really is that when you know you are changing the gate voltage there is a corresponding change in the gate charge and that delta Q G divided by delta V G is my total capacitance that is on the left hand side and that consists of these two quantities. In other words you know if you now make use of these definition what you have really got is 1 over C minus 1 over C G because of this negative sign that I have is minus 1 over C ox minus 1 over C silicon in other words all this has told you is that you know C G is equal to 1 over C ox plus 1 over C silicon ok. So, what this is telling you is that the total gate capacitance that you would measure in the process at different gate steps by applying that small signal ac is going to be modeled as a series combination of two capacitances. One is C ox which is a insulator capacitance we can define C ox as epsilon ox by T ox ok. We are now presently dealing with per unit area capacitance eventually you are really interested in total capacitance when you do the measurement just multiply with that area that you have in the device then you get a total capacitance right. You know if you are using per unit area on the left hand side you be consistent and use per unit area on the right hand side ok. So, I am just defining all these values in my equation as per unit area capacitance to just keep it simple. So, area is a scaling factor for me now this is really you know when I say epsilon ox permittivity of the oxide in other words this really is epsilon r of oxide which is relative permittivity of the oxide terms epsilon naught divided by T ox. So, what is this telling you epsilon naught is constant epsilon r ox is constant T ox once you make a device is constant and hence oxide capacitance does not change this is a fixed quantity. However, C silicon which is defined as d q silicon by d psi s is not constant for a unit change in surface potential how much is the change in charge varies depending on whether that capacitance is an inversion region whether it is in depletion region or whether it is in accumulation region. So, hence what we essentially say is that you know this is a variable capacitance and my equivalent model now is C ox in series with C silicon and this is a voltage dependent capacitance and the total capacitance that you see is C g you are applying V g here and this is at the ground potential this C s i is a function of V g and as I said you know you can sort of say that the C silicon depending on the region of operation you know it is different as I mentioned this can also be shown as something like this one of this branch is active that is why I have drawn this as a dotted line depending on if it is in depletion region we call this a depletion capacitance and if it is an inversion region that capacitance will be different if it is in accumulation region that capacitance will also be different and this of course remains constant and more specifically right it turns out if you recall our discussion earlier that we had in depletion the charge in semiconductor is essentially depletion charge you see because all mobile charge electron and whole charge can be neglected right. So, in other words the change in charge is essentially be governed by how the depletion charge changes. So, what is the depletion charge in particular if you look at the C d the C d is really I will call it as you know C d will come from the depletion charge and this depletion charge is essentially right you have p type semiconductor and hence acceptor impurities which form this depletion layer that is number per centimeter cube and hence you multiply with the charge and multiply with the depletion width and hence you get coulomb per centimeter square correct because this is number per centimeter cube coulomb per centimeter cube I multiply with centimeter and hence I get coulomb per centimeter square right dimensionally consistent. So, as I said I am using all quantities as per centimeter square and it is negative because acceptor charge is negative. So, now what is W? W d I also had mentioned that you can make a depletion approximation right and then it becomes a one sided junction right in we have discussed this in the earlier class. In other words for in one sided junction your W d is essentially given as 2 epsilon silicon times psi s which is psi s is a voltage across the depletion region you see right because psi s is a voltage across silicon and why is the voltage across silicon present because as a depletion region and hence psi s is effectively voltage across the depletion region by q and a right. So, you know now you substitute this here and you get q d as a function of psi s right and you differentiate that you get depletion capacitance. Notice that q d is only a square root function of psi s in depletion region this needs to be contrasted little later for the condition inversion and accumulation and we will indeed see that the charge in inversion and accumulation will be an exponential function of psi s not a square root function of psi s. So, in other words what I am telling you is that in inversion or in accumulation the charge is not coming because of the acceptor impurities. The charge is more the acceptor impurity charge if any in inversion region is more than I mean sort of over shadowed by the large number of inversion electrons and in accumulation region anyway there is no acceptor charge because I have no depletion region anyway. So, in both cases we sort of ignore the depletion charge right and the charge is either due to excess electrons or due to excess holes. What do I mean by excess my initial concentration of the charge right electron and hole charge is n p naught and p p naught which essentially means that this is a p type semiconductor as I have already told you. The p type semiconductor to begin with may have a doping concentration of 10 power 15 let us say n a is 10 power 15 per centimeter cube it means that the equilibrium thermal equilibrium hole concentration which we call p p naught hole concentration in p type material at 0 meaning thermal equilibrium is 10 power 15 whereas, n p naught electrons are minority carriers and electron concentration in p type material under thermal equilibrium will be n i square by n a which will be about 10 power 5 or so. So, your if you look here your p p naught will be 10 power 15 per cm cube and your n p naught will be 10 power 5 per cm cube correct and as you know when I am going in accumulation the hole concentration continues to increase from 10 power 15 further up and when I am going towards inversion this 10 power 5 would have gone up to 10 power 15 and beyond that is why I am ignoring the n a completely. So, when I am only looking at the free carrier charge as you know the carrier concentration here will essentially be given by the surface potential. In other words your n carrier concentration will be given as n p naught e to the q psi s by k t when psi s is equal to 0 flat band condition this exponent term is 0 anyway and n is equal to n p naught and similarly your p is p p naught e to the minus q psi s by k t again when equilibrium psi s is equal to 0 v f b is 0 is what we have assumed p is equal to p p naught and these numbers. So, once we start applying voltages what is accumulation? Accumulation is when the bands are bending up it is becoming more and more p type you started with certain condition p type doping concentration right the Fermi level is already below the mid gap, but at the surface it becomes more and more p type the bands start approaching at the surface become come closer to Fermi level right and based on our convention bands bending up is psi s is negative when bands bend down psi s is positive. So, in other words when I am in accumulation this can be completely ignored because psi s is negative if anything this is going down whereas here psi s is negative p starts increasing how does p increase with respect to psi s exponential function. Similarly, when I am bending the bands downwards to convert this p region into n region once I reach inversion subsequent to that there is further band bending you see and psi s is now positive as you know that is why n is increasing and what is the functional relationship of n in turn your inversion charge. You see inversion charge is what related to n inversion charge is a exponential function of these two what does it mean a very small change in psi s results in a very large change in q s is it not that is what we mean by exponential function as opposed to a square root function that we had in depletion. In other words we say that the silicon capacitance is almost infinite it is not quite infinite right all we are saying is that silicon capacitance is very large compared to the insulator capacitance that we have. So, in inversion and accumulation condition because q silicon varies exponentially with psi s your d q silicon by d psi s you see this is differentiation of this is an exponential function is very large very large meaning sometimes in text book you see that it is treated as infinite you know it is treated as an infinite all that means is that c silicon is significantly large compared to c ox that is the meaning right compared to c ox my c silicon is huge and hence I say infinite. So, that you know when you have a series combination of two capacitors you have c ox in series with c silicon what happens to the equivalent capacitance. Remember the parallel combination that we had 1 over c g is 1 over c ox plus once I mean this is essentially given by this when c silicon goes to infinity your total capacitance is simply oxide capacitance right. So, what this is telling you is that in inversion and in accumulation if the semiconductor charge is an exponential function of the surface potential psi s then silicon capacitance is so large that equivalent capacitance goes to c ox. So, all it means is that if I now were to look at the capacitance voltage curve this is telling me this is a p type v f b is 0 flat band condition at 0 gate voltage and that will have some capacitance in fact it turns out we call it c f b flat band capacitance will come to the definition of flat band capacitance in a minute for negative gate voltages on a p type substrate we are accumulating more and more hole right negative gate voltage can attract more holes to the surface right meaning accumulation condition in accumulation condition c silicon is so large right and hence my capacitance should be constant right when I go to large negative voltage and what is this value this value is c ox that is the maximum capacitance I can have measured capacitance I can have in a you know m o s capacitor and of course, when I start approaching this right it is not quite that accumulated right I mean this little bit accumulation, but not quite exponential function if you see when x is very low exponential function can be approximated as a linear function right e power x is x when x is very small you see and hence when I have just started bending bands up or down up that is I have started going towards accumulation right and still the change in charge is not very huge compared to change in surface potential and hence I cannot make this assumption right and hence there is a finite capacitance which comes in series with oxide capacitance that will pull down the total capacitance and that is why the total capacitance starts coming down and this capacitance c f b is essentially defined as epsilon silicon by what is called lambda d and lambda d is called Debye length and Debye length is in turn defined as you know epsilon silicon k t over q which is thermal voltage rather than psi s we have thermal voltage here because psi s is 0 at flat band remember that we are trying to define a capacitance at flat band condition divided by q n a. So, this is essentially your flat band capacitance and the Debye length is also sort of referred to as the screening capability of semiconductor meaning if you apply an electric field what is the distance over which that electric field can be screened if you have a large doping concentration it can be electric it is like metal you know metal can screen the electric field you know electric field cannot penetrate inside the metal you see. So, high doping concentration results in low Debye length and low doping concentration results in large Debye length and accordingly flat band capacitance is epsilon silicon by lambda d of course this is flat band capacitance in silicon that again is in series with c ox and again you compute the equivalent capacitance. So, let me define this as c f b silicon understand. So, what it means is that when I have a flat band condition this is a silicon capacitance now this silicon capacitance as usual you see as I have shown here in this picture this is c silicon is in series with c ox. So, any time once you know the silicon capacitance you should put that in series with c ox and compute the equivalent capacitance because that is what you measure in the external world. So, this is defined with respect to silicon only you put this in series with c ox compute this you get a capacitance equivalent value which is lower than c ox right because this is not infinite this is finite beyond this I am going in depletion region in depletion region what is happening the charge is not of course changing as fast as it was in accumulation and even in flat band condition the charge changes only as a square root function of psi s. So, which means this silicon capacitance continues to go down in depletion region further and further and hence you would obviously expect this to continue to go down. So, this is what we call a depletion region right and this is really the accumulation region. So, in depletion region what is your capacitance again silicon capacitance as we have already seen c depletion in silicon is epsilon silicon divided by w d where w d is the depletion width this will be even lower than c f b silicon put that in series with c ox you compute the total capacitance and that is what is plotting here and eventually you reach inversion. Let us say this is my inversion voltage somewhere here what am I expecting inversion in inversion charge should again increase exponentially right and hence I would expect this capacitance again to go to c ox this is c ox. So, and somewhere here you make this transition. So, what this is telling you is that I have started in depletion depletion capacitance continues to decrease as you continue to you know have increased depletion width, but eventually depletion width gets pinned when I reach inversion and then the inversion capacitance is little more than depletion capacitance and that is why this starts going up right. So, you essentially you know reach the inversion condition somewhere out here and when you really are in deep inversion very heavy inversion you again have gone back to your maximum capacitance and what is that maximum capacitance you have c ox as a maximum capacitance right this is what you would expect and now very interestingly this happens only if the measurement frequency here is low frequency and we will come to that why that is the case. What is low if it is a silicon capacitance that you are looking at a very high quality silicon capacitance in order to get this kind of behavior your frequency should be less than a hertz it could be 0.1 hertz or something like that depending on how good is the quality of silicon. So, this is really really low frequency let me just sketch that again to avoid the clutter right. So, what I am telling you right now is that you have this v g and you have this curve here. So, here see what you get here is only under which we call c l f only under low frequency and the frequency could be less than a hertz very very low frequency for very good silicon high quality silicon high quality silicon high quality what I mean by high quality silicon it has no defects it is a very pure silicon crystal no defects in that kind of silicon you really have to go to very low frequency. If we do this measurement at 100 kilo hertz 10 kilo hertz these are called high frequencies what happens is that I do not see this instead I see a curve which looks like this and this is what we call high frequency c v in other words as I go deeper and deeper inversion typically you know somewhere here we say we have reached weak inversion weak inversion meaning the surface has become n like it used to be p like earlier because the bands have been so much electron concentration is more than hole concentration when electron concentration becomes equal to hole concentration that is what we call a weak inversion. And strong inversion is when I am sorry electron concentration and hole concentration become equal to each other what is that intrinsic concentration right and that is weak inversion right remember my electron concentration to begin with was 10 power 5 hole concentration to begin with was 10 power 15 as you know this starts increasing this starts decreasing somewhere in between the meet what is that that is a intrinsic condition beyond that my electrons are more than holes. So, that is the point which is called weak inversion from that point onwards until my electron concentration goes to 10 power 15 which is now is equal to the hole concentration that I began with and that is what is called strong inversion. So, the weak inversion is when n is equal to p is equal to n i till n is less than n a n a is your acceptor impurity concentration your strong inversion n is greater than n a that is your strong inversion. So, when I reach strong inversion that is when I reach maximum depletion bit that is what is called w d max that happens when my band bending is 2 times phi b right phi b is the initial bulk potential that I had to begin with. So, here this is really the strong inversion point this point here where capacitance reaches a minimum and continues to stay constant this is where your psi s is equal to 2 phi b phi b is your initial potential the bands have bent so much that p region has been completely converted into an n region at the surface and somewhere here you know you will also reach a condition where psi s is equal to phi b you see here psi s is equal to 0 that is why we call it a flat band condition no band bending psi s is 0 here bands are bent such that the fermi level and intrinsic level are coinciding at the surface and that is the weak inversion from here to here I have a weak inversion condition from here onwards I have a strong inversion condition. So, why is it that I get a different capacitance at high frequency let us think about it I mentioned that when I am computing silicon capacitance silicon capacitance is d q silicon divided by d psi s of course, this is a negative psi this is how I define silicon when I change the surface potential a little bit what is the charge that is coming in and I did mention that in inversion the charge is dominated by the electrons majority I mean the now they have become majority because they are more than n a and hence they change exponentially with respect to psi s and hence capacitance is very large because I made that assumption capacitance is very large the series combination went to C ox, but now we have to ask the question what are the prerequisite for that capacitance to be very large the prerequisite is that you need to have enough electrons, electrons remember are minority carriers. So, what am I doing I am just to sort of remind you the wave voltage waveforms that I had earlier I have at any point a d c and I have a wiggling ac waveform here. So, whenever I go from previous step to next step I always reach first a steady state condition I reach a steady state condition only under steady state condition right. If you have produced where are these minority carriers coming from you see minority carriers are not available there holes are already available in silicon because it is p type doped. So, minority carriers have to be generated in silicon it is a electron hole pair generation that should happen in silicon if you have generated electron hole pairs then electrons go toward the surface because the field is favorable for electrons to go to the surface and holes are of course collected in the bulk of the silicon. So, when I wiggle this gate voltage at high frequency you see there is a generation time just as there is some recombination time given any silicon material there is certain time it takes to generate carriers and again that generation time depends on how good is your silicon. If your silicon is not at all defective the generation time can be in seconds it takes a few seconds to generate these carriers. Unless you generate these carriers what have I done I have applied a DC voltage remember this let us say this voltage here corresponds to 5 volt and this point is 5 volt I am at 5 volt I have generated a steady state electron concentration which is required for inversion, but now instantaneously I am changing the gate voltage little bit higher, but in that could be of the order of microsecond or millisecond. If the generation time is 1 second or 10 seconds in microsecond you cannot generate those carriers electrons are not generated and hence whenever I am changing the gate charge the charge that is responding in silicon will not be minority carriers at the interface. In other words remember what has happened now this is the MOS capacitor that we have with certain area right and I have produced an inversion electrons here by applying 5 volt this 5 volt has put in some plus some q charge here and that plus q charge is more or less balanced by these electrons here you see. Now if I need extra electrons they need to be generated only when there is a charge compensation happens by these electrons the silicon capacitance is very large, but when I change this charge what is the meaning of more positive voltage instantaneously I have done more positive charge on the gate capacitance charge balance has to happen the charge is not coming from the electrons because electrons are not there so what happens? What happens is very simple what you really have in inversion condition is large number of electrons and large number of acceptors may not be as large there are acceptor impurities. So, if this instantaneous positive charge at very high frequency has to be balanced by an equal negative charge that can happen only by uncovering more acceptor impurities at the edge of the depletion region. So, meaning that the holes here which are out here holes go away and extend this depletion region a little more and positive charge is balanced by this extra negative charge. The extra negative charge is not coming due to electrons the extra negative charge is coming due to the edge of the depletion region responding. So, edge of the depletion region starts moving up and down because electrons are not able to respond instantaneously because there is a generation time and electrons have to get generated in depletion region only then more electrons will come here. If I take the next step because I am waiting for a long time again I reach for the next measurement let us say it is a 5.5 volt when I have a 5.5 volt steady state again I have a situation where in the depletion width looks exactly same as this depletion width there is no change in the depletion width because I have waited long enough. So, all that has happened when I went from d c 5 volt to you know d c 5.5 volt I had dumped that extra positive charge, but I gave enough time and hence large number of electrons got generated here and I have reached again a new steady state where in the depletion width is still same and now I apply a small signal. So, what happens this small signal I cannot generate electrons. So, edge of the depletion region moves back and forth right because the w d max has reached here and w d max has reached here in inversion the capacitance does not change and also the capacitance does not go to c ox because electrons are not responding it is only the edge of the depletion region the holes are uncovering and covering the charge. And hence you get a capacitance which is a capacitance constant capacitance first of all a constant value which is not the same as the oxide capacitance value which is much lower than the oxide capacitance value. What is this value? This value is essentially you know your c ox again in series with c silicon minimum when do you reach c silicon minimum when depletion width reaches maximum. In other words c silicon minimum is epsilon silicon divided by w d maximum. So, whenever I am in a steady state inversion I always reach a maximum depletion width and hence the maximum depletion width remember is dependent on doping concentration. So, if you have different doping concentration your c minimum will vary and then put that c minimum again in series with c ox and then you get your equivalent total measured capacitance. So, then the key here is that if I do measurement at any frequency which is let me get this here at frequency such as you know 10 kilo hertz even 1 kilo hertz could be reasonably high, but there could be a transition here you know less than 1 hertz is really low. So, that I am at the other extreme I am generating enough carriers enough electrons are generated. So, your charge in change in charge on the gate is balanced by electron charge which is changing and at other extreme electrons are not at all responding because it is very small compared to generation time, but when the generation life time and your frequency of probing are comparable you will have a transition region. In fact, you may see curves which would maybe let me just sketch it again. So, that you know there is no confusion here as I mentioned this is really high frequency and this is really low frequency and as I said you know this could be less than 1 hertz and this could be let us say greater than 1 kilo hertz for example, if the generation time is of the order of second for example, then as I go to let us say 500 hertz you know your CV may look like this why you have some electrons responding not as many as you would have desired it right when you go to 100 hertz you know you may get something like this you know 10 hertz may be something like this and eventually when the probing frequencies and hence the inverse of frequency is the time span that you are giving is much you know larger than the generation time then obviously you are in this region because now you know just to contrast this here again what is low frequency the low frequency is that it is varying. So, slowly you know I am still at the same step you see I have not changed the step because I have still not completed my measurement my frequency is very low and since going from this voltage to this voltage typically the AC signal is of the order of 20 millivolt you know 30 millivolt of that time that range because this this voltage is changing so slowly I am giving enough time at any given voltage for these electrons to respond right and hence you know you are at this extreme. So, this is very important point that you know often times I see students miss out completely why there is a change and how the transition happens right and why is it that at high frequency I continue to get the same minimum value why not different value because in steady state remember I go to a new value of voltage I am stabilizing everything and hence I am operating at the WD max I have saturated that depletion that is not changing and because of that change in frequency only the edge of the depletion region is responding and hence the capacitance flattens out. However, often times you may have also seen you will also see this in some text books right that if you are doing this CV measurement if you are not doing this steady state meaning if you do not give enough time then what could happen is that you see your high frequency should look like this it should you expect this to reach a minimum value and that minimum value is exactly governed by this WD max this WD max is exactly governed by a band bending of 2 phi b 2 phi b is a band bending so that you have generated enough carriers right. But if you are doing a very fast ramp right then remember there is a AC and there is a DC change that is the step the step or ramp whatever you want to call if you do the step and instantaneously apply the voltage right meaning your effective ramp rate is too fast to reach a new steady state then what you could see is that you see sometimes that your capacitance goes into what is called deep depletion and this is called deep depletion at high frequency. I should have got the flat capacitance once I reach inversion but what is happening is that when I go from 5 volt to 5.5 volt a picture that I showed you I am not waiting enough time for 5.5 volt so what has happened because of that when I was trying to do the measurement of the capacitance I actually had a depletion width which was deeper than what WD max would have predicted and that is why it is called deep depletion. Why is that because the positive charge has to be balanced by total negative charge total negative charge comes due to acceptor impurities and electrons you will get sufficient electrons only if you wait for sufficient time because you are not yet waited sufficient time instantaneously when I change from 5 volt to 5.5 volt in fact what happens is you would really have something like this when I go from 5 to 5.5 volt at time t equal to 0 when that step happens because I am not yet start generating the electrons once I start generating the electrons this depletion width starts collapsing because there are more and more electrons coming because of the generation and eventually if I wait long enough it will go and settle down to this value you see and that is what I call a steady state going to 5.5 give enough time you generate enough electrons so that depletion width is still WD max. But now you have gone to 5.5 you did not wait for enough time you instantaneously wanted to measure capacitance. So, when you are trying to measure that capacitance the depletion width was here. So, now this depletion width again will adjust itself to this high frequency because this depletion width is more than WD max the fundamentals are still same what is your total capacitance in silicon epsilon silicon divided by WD C silicon which will come in series with C ox but WD is more than WD max because you did not wait enough you wanted to do the measurement immediately. So, if you do that you know you may get an erroneous C minimum value C minimum value which will not correspond to the steady state WD max value and that is the phenomenon which is called deep depletion as I have indicated here. So, the message again is that when you are doing CV measurement you are step size when you take a step size from one voltage to the other voltage give enough time before you start applying that AC voltage. In other words have a very low ramp rate if you have a very low ramp rate then you have a low ramp rate. So, you have a steady state from one voltage to the next voltage and then you are doing the capacitance measurement. Now maybe at this time it is also important to mention when you do CV measurement you should do it in a properly covered dark probe station because you do not want any light to come in why remember the discussion that we were having so far in inversion especially you will have huge errors in capacitances in depletion and inversion region if you have an ambient light why because ambient light can also generate electron and hole pairs. So, your electron hole pair generation is accelerated by the light. So, if you do a CV measurement even if it is high frequency CV measurement if you do it with full blast light on the device you may actually see a curve which would look like this. If this you do a H F CV with light because by shining light you have reduced the generation lifetime. It is like photovoltaics and you have a light you generate electron hole pairs when you did not have any light that is a thermal equilibrium you know given the room whatever ambient temperature of the measurement that temperature has thermal generation. The generation is only due to the ambient temperature but if you have light you will again get erroneous capacitance and it is important to do a high frequency measurement and get the right minimum capacitance because subsequently when you build devices and you want to analyze a device this minimum capacitance has very important role in analysis because from this minimum capacitance we can actually extract the doping concentration. Although wafer manufacturer will specify 1 to 10 ohm centimeter resistivity 1 to 10 ohm is a large variation in doping concentration a particular wafer that you are using right did it have 10 power 15 or 5 into 10 power 15 doping concentration. That information you can precisely get if you do this measurement precisely if you get a precise minimum value of this capacitance this minimum value of the capacitance as we will see little later in CV analysis this minimum value H F CV C min value can give us information about doping concentration. Similarly it is important to get right oxide maximum value because this information either H F or L F it does not change accumulation capacitance will give us information about T ox because remember this is C ox C ox is epsilon ox over T ox whereas this is C ox in series with that silicon minimum capacitance because you know C ox you can take out the effect of C ox you can actually get minimum silicon capacitance. Once you get minimum silicon capacitance you also know that C silicon minimum is epsilon silicon divided by W d max and hence you get W d max correct. Once you get W d max you know W d max is related to doping concentration correct because we already said W d max is essentially given by 2 epsilon silicon psi s what is psi s psi s is 2 phi b because I have reached inversion 2 phi b by q n a this needs to be solved iteratively because I know W d max alright but phi b also has n a term phi b is k t over q l n n a over n i right that is your potential phi b right phi b k t over q l n n a over n i correct. So you have a n a term here n a term here and you know the total value right you need to solve it is not an explicit equation to solve but you can do an iteration technique and solve it. And hence if I have a precise estimate of minimum capacitance and precise estimate of oxide capacitance then I can get precise estimate of substrate doping right. And that is why when you do this measurement you have to be careful you make sure that you do not go into deep depletion you make sure that you do not have any other light interference and then do the measurement. And similarly you know if you are doing a measurement if the ambient I mean if you are for example you have a thermal check you heat the check right. If you increase the temperature you increase the thermal generation right again you would expect that as you start increase the temperature the HFCV may probably start going away from this point and maybe start going look like this because I am increasing the generation right. Anything that increases the electron hole pair generation rate will start increasing the minimum capacitance in high frequency and start it make it higher and higher. So, let us then summarize it for the day. So, we look at MOS capacitor which is an ideal MOS capacitor all it meant was I consider a capacitor which has fictitious metal electrode with the same work function as my substrate work function and oxide had no charges and hence VFP is 0. So, under that condition we looked at the high frequency response and the low frequency response the response is different simply because the charge in semiconductor comes either due to minority I mean the mobile charges could be minority or majority electrons are holds depending on whether your inversion or accumulation region and or depletion charge. So, when it comes due to depletion charge then you get a different capacitance and that is what happens in a high frequency because high frequency you do not give enough time for the charges to generate and that is only inversion you see not in accumulation because in accumulation I am looking at the response of holds in a p type semiconductor there are large number of holds there is no issue at all for holds to respond holds will instantaneously respond to any wiggle of gate voltage that you have on the gate right. Only in inversion your capacitances start deviating from each other only at low frequency you get the highest capacitance which is C arc similar to your accumulation, but at low high frequency you get a capacitance which is different which is determined by your maximum depletion region and that is true if you are doing this DC step under steady state. If you do not do that DC step under steady state you may reach this deep depletion condition and if you reach the deep depletion condition then your high frequency minimum capacitance will be much lower than what would the theory predict based on WD max right. And similarly any other aspects such as light or temperature which can influence the generation can also influence the minimum capacitance for the high frequency curve. So, let us stop here today and you know we will continue in the next class and we will start looking at all the non ideality such as fixed offset charge interface states and the slow called slow interface states and you know a whole range of non idealities how do they impact the capacitance voltage characteristics.