 Hello, and welcome to this presentation of the STM32G0 system configuration controller. STM32G0 microcontrollers feature a set of configuration registers located in the SIS-CFG module. The system configuration controller gives access to the following features. Enabling and Disabling I2C, Fast Mode plus High Drive Configuring the USB Power Delivery Interfaces Enabling and Disabling the Analog Switch Voltage Booster Configuring the Infrared Timer Module Remapping the PA11 and PA12 GPIOs to PA9 and PA10 Selecting the memory accessible at address 0 Enabling and Disabling Safety Features The two I2C controllers present in the STM32G0 support three speeds. Standard Mode, the maximum bit rate is 100 kilobits per second. Fast Mode, the maximum bit rate is 400 kilobits per second. Fast Mode plus, the maximum bit rate is 1 megabit per second. Fast Mode plus requires a high drive capability, which is enabled in the SIS-CFG module. Since high drive is controlled at pin level, it is also available for the other alternate functions. The high drive capability of the I2C1 pins can be configured per pin through the I2CPA9 to PA10 FMP and I2CPB6 to PB9 FMP bits or globally by setting the I2C1 FMP bit. The high drive capability of the I2C2 pins is controlled globally by setting the I2C2 FMP bit. The USB power delivery interfaces must be configured early in the boot program. Two timing diagrams are represented. The only difference between them is the initial configuration before power arrives, dead battery behavior required or not. The boot program initializes the ANA mode and ANA sub mode fields in the UCPD control register to configure the UCPD interfaces, typically as a source or sync. However, this configuration becomes active only when the UCPD X strobe bit is set in the SIS-CFG CFGR1 register. The STM32G0 supports a voltage booster that should be used when the analog inputs operate in low VDD voltage. It is activated by setting the boost EN bit in the SIS-CFG CFGR1 register. The infrared timer unit or IR TIM unit requires a modulation envelope signal that is provided either by USARTS or by TIM16. The IR mod field in SIS-CFG CFGR1 register controls the related input multiplexer. The IR pole bit in the SIS-CFG CFGR1 register selects whether or not the output signal is inverted. When the PA11, PA12, RMP bit in the SIS-CFG CFGR1 register is set, the PA11 and PA12 alternate functions are remapped to pins PA9 and PA10. This is useful when these alternate functions are needed while the PA11 and PA12 pins are not available in low-pin count packages. The mem mode field in the SIS-CFG CFGR1 register selects which memory is accessible at address 0. Three memories can be aliased to address 0. Main flash memory, system flash memory or SRAM. Note that the default setting of this field depends on boot pin, option bytes and control bit. The SIS-CFG CFGR2 register contains the control and status bits linked to safety and robustness. Four control bits direct certain error detection events to the timer's break inputs. This allows timer outputs to be placed in a known state during an application crash. Once programmed, the connection is locked until the next system reset. These internal events are the power voltage detector event, the Cortex M0 plus lockup state, the SRAM parity error and flash ECC error. The SIS-CFG CFGR2 register also contains a flag bit that is set when an SRAM parity error is detected. The SIS-CFG module supports 32 interrupt line status registers. They enable software to easily find the cause of an EXTI interrupt by collecting in the same register all pending interrupt sources associated with a particular interrupt line. In order to explain the benefit of these interrupt line status registers, the following slide will focus on the EXTI2 and EXTI3 interrupt lines. The left part of the figure represents the peripherals able to assert EXTI2 and EXTI3, respectively RTC, TAMPR and flash memory units. Regarding EXTI2, RTC and TAMPR interrupt requests are ORD together. Regarding EXTI3, flash memory ECC and flash interface interrupt requests are ORD together. Furthermore, EXTI2 and EXTI3 interrupt requests are also ORD together to generate the int number 5 received by the Cortex M0 plus NVIC. In the int5 interrupt service routine, software should first read the SIS-CFGIT line 6 register to determine whether EXTI2 or EXTI3 is pending, and then either SIS-CFGIT line 2 or SIS-CFGIT line 3 register to determine the exact cause of the interrupt. In addition to this training, you can refer to I2C, UCPD, IRTIM, GPIO, flash memory, interrupts and timers trainings. For more details, please refer to application note AN2606STM32 microcontroller system memory boot mode.