 Hello everyone. Myself, Sanjay Utke, assistant professor, department of electronics engineering, Valchand Institute of Technology, Solapur. Today, we are going to discuss sequential logic circuit part 2. Learning outcome. At the end of this session, students will be able to analyze various sequential logic circuits like shift registers and counters. Outline sequential logic circuit, shift registers, and their types. A synchronous counters, question, answer, synchronous counters, references. Sequential logic circuit part 2. In the earlier session, we had a discussion on flip-flop, which is a one-bit memory cell, capable of storing one bit of information. In this session, we will discuss registers and counters. In the registers, we are going to discuss shift registers, universal shift registers, shift right and shift left types, counters, a synchronous counters, and synchronous counters. The shift register is another type of sequential logic circuit that can be used for the storage or the transfer of binary data. This sequential device loads the data present on its inputs and then moves or shifts it to its output. Once every clock cycle, hence the name shift register. A shift register basically consists of several single-bit D-type data latches. One for each data bit, either logic 0 or 1, connected together in a serial type, daisy chain arrangement, so that the output from one data latch becomes the input of the next latch and so on. Data bits may be fed in or out of a shift register, serially that is one after the other, from either the left or the right direction or all together at the same time in a parallel configuration. In summary, the register, it is a group of flip-flops connected one after another in which data can be shifted from one flip-flop to the next that is from right side towards left side or from left side towards right side. Or the data can be entered through all the flip-flops once at a time called as parallel loading and can be retrieved at the same time called as parallel getting the outputs. Shift register, the number of individual data latches required to make up a single shift register device is usually determined by the number of bits to be stored with the most common being 8 bits, one byte, byte constructed from 8 individual data latches. Shift registers are used for the data storage or for the moment of data and are therefore commonly used inside calculators or computers to store data such as two binary numbers before they are added together or to convert the data from either a serial to parallel or parallel to serial format. Generally, the shift register operates in one of the four different modes with the serial into parallel out SIPO. The register is loaded with the serial data one bit at a time with the stored data being available at the output in parallel form. Serial into serial out SISO, the data is shifted serially in and out of the register one bit at a time in either a left or right direction under clock control. Shift register, parallel into serial out. The parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control. Parallel into parallel out PIPO. The parallel data is loaded simultaneously into the register and transferred together to their respective outputs by the same clock pulse. So, parallel in parallel out is the most high speed register because with the same single clock pulse data is been loaded simultaneously into the all flip-flops and can be retrieved at the output side. So, that is a which requires only single clock pulse. So, this PIPO that is parallel in parallel out is one of the most high speed register as compared to 3 that is SISO, SIPO and PISO. So, this is the shift register. Total flip-flops user 1, 2, 3, 4 capable of storing 4 bit of information. So, this is D is the serial data input. This is Q is the serial data output. D0, D1, D2, D3, all these are the parallel data inputs and the parallel data outputs are Q0, Q1, Q2, Q3. This is MSB and LSB. So, we can load the data in serial form. We can retrieve the data in serial form. We can load the data in parallel manner as well as we can retrieve the data in parallel manner also. This is the universal shift register in universal shift register with the addition of some combinational logic circuit which consists of AND gates and OR gates. This red color AND gates and yellow color OR gate. It is possible to convert a simple shift register into universal shift register. So, with shift is equals to 0, this AND gate will get 0, 0, 0. That will be disabled whereas this signal will become 1. This one is given to this B1, B2 and B3. So, all these B1, B2, B3 AND gates are enabled. So, data B1, B2, B3 parallel data has been loaded to all these 4 flip-flops. So, with the signal at 0 at shift or oblique load bar, we can load the data in the parallel manner. Whereas with this signal equals to 1, these AND gates are enabled and the data is been shifted from ff0 to ff1, ff1 to ff2, ff2 to ff3. Remember all these flip-flops are triggered with the same clock pulse. It means that same clock pulse is applied to all the flip-flops. So, they are clocked simultaneously. So, with this signal, we can shift oblique load bar to 0. The data can be loaded parallely. And with this signal shift equals to 1, the data can be shifted in a serial manner. So, with this we can perform loading operation as well as shifting operation. Here we have taken the shifting operation from right side to left side towards right side. That is from ff0 to ff1, ff1 to ff2, ff2 to ff3. Remember, for shifting the data 1 bit at a time towards right side, it will take 1 clock pulse. So, shifting 4 bit data through all these 4 flip-flops, 4 clock pulses are required. Detailed counter. A counter is a device which stores the number of times a particular event or process has occurred often in relation to a clock. The most common type is sequential digital logic circuit with an input line called the clock and multiple output lines. The values on the output lines represent a number in the binary or BCD number system. Each pulse applied to the clock input increments or decrements the number in the counter. So, digital counter is usually constructed of a number of flip-flops connected in cascade. Counters are very widely used component in digital circuits and manufactured as separate in IC and also incorporated as part of large integrated circuits. So, they are classified as asynchronous or ripple counter and synchronous counter. Also, they are further classified as decayed counter, up-down counter. A synchronous counter is a D-type flip-flop with JNK. This circuit can store 1 bit and hence can store from 0 to 1 before it overclose. This counter will increment once for every clock cycle and takes 2 clock cycles to overclose. So, every clock cycle it will alternate between transmission 0 to 1, 1 to 0. Output of a previous flip-flop is given as a clock input to the next flip-flop. The result is called as ripple counter. So, this is a 2-bit asynchronous counter. JNK inputs are permanently connected to logic 1 level. So, whenever the clock is present, Q will become 1. The output of 1 flip-flop is given as a clock input to the next flip-flop. So, when the clock is 1, then only this next flip-flop will give us output 1. So, at the arrival of every clock pulse, this output of the first flip-flop will shift from 1 to 0, 1 to 0. Whereas, output of the second flip-flop will change only when the previous will fall from 1 to 0. Accelerate Assignment. What is meant by asynchronous? It is the stands for the absence of a synchronization, something that is not existing or occurring at the same time. Synchronous counter generally refers to something which is coordinated with others based on time. Synchronous signals occurs at same clock rate and all the clocks follows the same. In synchronous counter, the clock input across all the flip-flops uses the same source and creates the same clock signal at the same time. This is the timing diagram. Thank you.