 మారార్ మారేబింది మోఠోట్ మోన్ పెల్ర్స్లు పడిపిమో పియార్వీస్త్ మరిలార్పింది స్మో మోట్ర్. పగానికంలో. we are going to be covering amba architecture okay so this is a different from whatever we have this is so far this is about the bus interconnect okay between action so we will be covering some overview of what amba architecture is all about and then I will show you a sample structure of an amba architecture along with arm processor unit and then we will go into the details of APB and APB bridges APB bus and what are the transactions and signals and then APB bridge also is one of the modules related to the amba architecture so before we go into this discussion I would like to give you some overview what is this specification and why it was designed by arm this is the interconnect standard from arm okay so what was the motivation how does it help in our design of an instruction look at the introduction part amba is a an acronym of advanced microcontroller best part this is a D factor standard for arm chip communication so what is the D factor standard standard suppose you have arm core and then when arm design this processor and then their model is also given as an IP and they also gave other IPs like cache controller right and then MMU, MPU okay these are all something which is these models are going to be in the SOC file okay and then SPU so they design different cache controller so this will in turn will be giving instruction and data caches so they design all these models as an IP now having given this if there is no uniform way of connecting them all together okay then there will be an issue the performance and power as well as cost everything that we gain using these models okay will be achievable only when we have an interconnect okay this is by design and meets the requirements of the low power design that is targeting this is the low power chips and for the applications the mobile applications are tablet and any other embedded low power devices so the target market is this kind of environment okay this kind of products so these IPs are given but there should be some standard interconnect also defined along with these IPs then it will be easier for people to buy these IPs and build their own IPs and interface with the customer items for modules in the IP so this burst architecture was a defective standard what does it mean it was originally designed for the use of ARM and it was later on made as an open standard and it became a defective standard that any it is not that it is only standard there are other standard components too but for the ARM products modules the AMBA architecture specification is an open standard which can be used not only to connect these which are coming from ARM people can build their own IP and interface with them so that is the way this market grew and presently so this SOC making an SOC with these interconnect along with these modules what is the ARM or coming up with this standard so the low power design and the performance in terms of when you say even burst is there and then you know we are talking about performance is the price per second okay how many how much of bytes can be transferred over this per second that is one that is bandwidth of this burst under one is a latency that is suppose memory MMU is connected to memory okay and memory is of course connected to the burst if it is on chip memory okay then it could be an interface could be there with the burst and then connecting to off-chain memory now latency is what when any address is sent out okay by the processor how long does it take for a maybe for a read cycle how long does it take for getting a a data getting the data back from memory to the processor so this is the latency and how fast any data can be transferred over the burst is what is bandwidth and how many devices that could be connected to this to the burst that is another design capability so if there are some limitations on number of modules that could be connected to it then there will be some limitations right so how many can be connected that is how adaptable or how easy it is for people to build their IP and connect it to the burst without impacting the performance of both all the features are supported in any burst communication I told you earlier there could be one master attack but it does not mean that only ARM can be a master in the whole burst okay there are other IP like a DSP processor could be sitting and then that could be a master for its own transaction on the burst and ARM could be what and then there could be a DMA who is initiating the transfer but it may be very productive MMA so this kind of multiple masters could be there in the system so this design should support multiple masters being in the system without computing you know they will all be computing for the burst ownership but it should be controlled by somebody okay there should be some control logic in this burst for them for the masters multiple masters connected to the burst to transactive over the burst so that should be a facility so may be Arbiter is one which I will talk about the data but just to give you an overview and Arbiter is the one who decides among multiple masters connected to the burst okay who can own a own that particular burst you know the burst for a transaction so what I am saying is may be you know time T0 to T1 ARM can transfer over the burst and then from T1 to T2 may be DSP processor who is on the burst can transfer over the burst and then later on may be DMA transfer could happen so who decides who is the master at a particular time Arbiter which is a centralized Arbiter who is the module is connected to all the masters and then there is only connected to two things okay two signals one is a request and another one is grant so every master who can initiate transaction over the burst are connected to the Arbiter and then they communicate to the Arbiter before they transactive over the burst that means they should be granted access to the burst so that facility should be there and then there should be a if you recall the non sequential access sequential access that we saw for the while talking about memory interfaces behind the different instruction how much time they take we said that okay one nano non sequential package and two sequential cycles so that means what burst transfer burst transfer should be supported that means the initiator gives one address okay that means addresses first address is given then the subsequent accesses are all to the address relative to this okay if the burst with data which is may be 4 bytes okay then plus 4 every address plus 4 transactive that means multiple bytes multiple burst over the burst starting from some address so that is a burst transfer that is called burst transfer and then there there should be a split transaction that means when we have multiple master trying to transactive over the burst one option is to say that okay one master communicate and then it finishes master communicates with whatever slave and then it communicates with transaction another one is each master initiating some transaction and then maybe this initially it was initiated then this then for some time then other master gets the burst and the data gets the burst the transaction is split across multiple types so split transaction that is another burst so maybe that is another feature that would help in making sure that the burst is always interlinked because whenever any memory is to be accessed it will take its own split time for decoding the address and then coming up with the data so doing that time those cycles maybe some other master can be allowed to use the burst to initiate some other transaction so the maybe it may be with the peripheral or it could be with some other external memory so the same memory is not involved in the case maybe no we can parallelize the transaction that is happening on the burst so split transaction burst transaction burst transfer and then low power so there should be some features which is part of the burst to handle the low power design that means transaction over the burst do not consume more power or when there is no transaction the burst is no not consuming power so these kind of a different features are built into this SOC this particular AMBO architecture and then released for for that to be used within the SOC so please remember this is not outside the SOC it is within the SOC you may have seen you may have heard about so many other burst standards like multiple ISCA ISCA in the PCI world you would have seen that PCI peripheral component interconnect and then multi burst what are the difference between these burst standards and what we are seeing here the AMBO burst is within the SOC that is within the chip whereas the multi burst ISCA and PCI they are all over the racks may be different or PCB within the PCB on the motherboard you can see that ISCA and PCI standards are there we plug in some PCI base add on cards to communicate with the motherboard of the PC or a multi burst is something like back bone kind of a rack so back plane there are bus address bus data bus it goes on the back plane and then the cards go into the rack so this is kind of a multi burst standard which is you know this was given by Gintam so this this standard burst standards were for either PCB or back plane kind of an environment whereas it is for within the SOC system on a chip this introduction gives you some overview of what we are trying to do in this ok now this is for the connection and management of functional blocks in a system on a chip it is connection as well as management of the functional blocks modules it facilitates right design with a large number of controllers so the SOC what we are trying to build using this standard is not limited to one or two a multiple processors could be there controllers could be there multiple processors master will be there on the chip and the AMBA architecture is adaptable for complex design and it should be easy and it should impact what first time features provided along with the AMBA specification that testing features ok you could test any module independent of other modules in the system in the SOC and then interface it with the SOC so a testing also is part of the design specification and there are features available supported in the AMBA architecture so AMBA promotes design reuse that is very important because anyone designing a graphics processor may be which is AMBA compliant ok graphics processor then it could be used not only in one particular you know companies SOC this could be sold to different vendors and it could be part of different so this since the interfacing is follows AMBA standard any SOC which follows AMBA standard this SOC could be reused there without any problem it is like a plug and play kind of a scenario so that design reuse is the most important thing for the quick adaptation of this particular standard for the SOC wide adoption of AMBA specification throughout the semiconductor industry has given a comprehensive market for the third party product so that is what I am telling you the design will use help in getting that which are AMBA compliant there is a plenty of IPs coming from different vendors which are AMBA compliant because there are lots of solutions which are ARM based and this IP products can be integrated with them without any issue so it actually helps in coming up with different SOCs with the multiple features and the SOC vendor also the semiconductor company can differentiate their design from other competitors by integrating their own IP as per third party IP which are AMBA compliant and then follow the AMBA specification for interfacing or connecting the multiple modules in which so this helps both the buyer as per the vendor for a quick time to market as well as easy to integrate and then development is easier and testing is easier because of this so this has enabled availability of good support for the development of AMBA if you put support in the ecosystem that is very important for any product to be successful in the system in the market so good ecosystem was developed around the AMBA system now what are the IP reuse later advantage IP reuse that is a common standard while supporting a wide variety of SOCs so there should be a common standard but it should not be restricted restrictive if it is restrictive then too many people may not be willing to use that so the common standard allowing multiple variety of SOCs supporting wide variety of SOCs is the most successful feature of AMBA so there is a different power and performance area required so SOCs will be different requirements see you may be interested in building a SOC for a 16 bit microcontroller for a very high very very low powered device low powered environment may be you know aeronautics or maybe it is for a small embedded system like some base base maker or something like that or it could be a big router with a powerful performance requirement high power performance requirement in SOCs it could be big so the AMBA specification should be generic enough for areas for a very low end 16 bit or even 8 bit controllers as well as 32 bit or 64 bit base systems so and high performance so this kind of a these two are very very wide requirement right but AMBA specification needs this so that is why it is successful and AMBA is a covariant of BHAG interface this is another standard interface AMBA that interface AMBA extends performance and scalability to many coherence processes so it is not even restricted to only single processor environment even multi processor environment the next level of specification of AMBA helps you in having multiple processors in the system cache coherency and then multiple possible to have your own cache may be L2 cache may be common then there should be cache coherency built into product so those kind of features are to be supported so the CHA takes care of that and multi layer architecture access a cross process between masters and players in AMBA 3 system so multi layer systems in terms of EADF when you have the interconnects going over multiple layers the effective source area occupied by the bus comes down and the width of the bus actually this AMBA bus varies in terms of width from 8 to 1024 bits the data bus width of the AHE bus could be varying from 8 bits to 1024 bits this is the very very wide support in terms of number of data lines in the bus if we need to support this without sacrificing on the area as well as signal integrity issues there should be some design kind of multi layer architecture which will help you in terms of achieving the speed that is required so meeting the performance and without sacrificing on the area or the noise on the bus so reliability of the system will be better when you increase the speed of the transaction over the bus so there should be some design element built into the system so that is also there so the parallel links allow the bandwidth of the interconnects to support the peak bandwidth of the masters to increase the frequency of the interconnect see when you have multiple layers then you can increase the data width once the data width is increased then without increasing the clock rate okay without increasing the clock rate the bandwidth can be increased because within one clock cycle okay so much of data is getting transferred so we get the peak performance peak bandwidth without increasing the frequency of the interconnect so that can be achieved so AMBA performance is generally used by depending common interface time for your system so this is the very important writing that it is a common interface time is for your system okay good so before we get into the some bus types and their interfaces let us see the what are the conventions this all of us are clear and wherever there is a grey area the value of the bus whether it is 1 or 0 is not defined okay then there is a bridge in the bus on the bus it will be interpreted like this which is expected okay and then when a bus from either from high or low is becoming a low sorry high becoming a high this is the signal when the bus is shown like this okay whatever time is okay this is all at whatever height so the value could be 1 or 0 okay it is completely stable given properly and high impedance state that means this is a very important property of putting a low power design because once the bus is on high impedance nobody is driving the bus so it is not drawing the parent and its capacity aspect on the so so high impedance state is shown like this and any bus any change in the signal is shown by this particular thing and when it is coming from high impedance to stable state it will be changing for a moment and then it becomes stable like this okay these are the different signals shared bus and signal areas are undefined the bus or signal can assume any value within the shaded area okay it could be 0 or 1 or it could be some intermediate values okay if we do not bother about no module which is connected to the bus will be sampling at this time so it is stable there is nothing no other module will go read or anything corrupt corrupted data during this time the actual level is unimportant and does not affect the current time it does not affect the normal operation of any of the modules connected to the bus okay let us now see a overview of the bus okay let us look at some more details about MBU so it was introduced in 1997 MBU has got 2 levels of hierarchy I have already told you this okay advanced high performance bus or AASB so this is one level okay another one is advanced peripheral bus so now we will use some more MBU is a standard architecture that is a multi microcontroller bus architecture under that different bus standards are there okay so either AASB or AASB will be in a system and AASB will be there I will give you a I will show you a diagram where you will understand what is this particular bus this is for a low power low performance okay very for us to be connected and when a low performance bus is connected to peripherals are connected to directly they are connected to the high performance bus because of the delay in the of the peripherals in the system the performance of the high performance bus are the the transactions on this bus by high performing modules like processors and memory most of the memory is not high performing in that atleast you know with the which has got a very good you know access time low will be delayed because of the presence of this so that is why they have divided this so low performance and low power you know not only low power actually low performance peripherals which are slow peripherals are not connected to the high performance bus that way because of the low speed peripherals the high performance bus and the modules connected to them are not flowed out okay that is the purpose of two levels on chip texture that is very important which I mentioned built in structure for testing modules on the bus so this is helps in time to market and a minimum of 32 bit data operation is recommended in the standard and it is extendable to 1024 okay minimum of a 32 bit is recommended but 8 bit also you can provide 8 bit data okay so this is the high level overview of now let us just I will I will tell you what are the some ideas on high performance bus okay here okay so in this battery okay this is okay this is this is okay okay okay okay the different processes in the system SOC, when I say system is SOC ok, because this verses are going to be inside the SOC. So, you know if you have a multiprocessor and this is actually supports multiple masters in the system. So, AHG supports multiple masters. So, you can have multiple processes in them and they are all connected to the AHV bus and on-chip as well as off-chip memories are connected extra memory also connected to the same AHV bus with low power peripheral macro system function. So, this low power peripheral macro system function also there, but may not be connected directly it could be through ATV grid that I will talk about later. AHV is also specified to ensure ease of use in an efficient design flow using synthesis in automatic processes. So, it also has easier design flow. So, that you will be able to integrate the modules different peripherals or different processors or memory in the SOC. Now, what is AHV ok? Advanced system bus the number AHV is for high performance system model ok. Actually this is that either AHV will be there ok in a system high performance bus or if we do not want in a system where this kind of a high performance system is needed because this complexity is more and power consumption will be more and it is meant for a high clock rate peripherals high clock rate per processor. But if that means the complexity is not needed then a designer can show a AHV there instead of AHV is a this or this ok any one of them. So, number AHV is an alternative system bus suitable for use where the high performance features of AHV are not required and AHV also supports efficient connection of processors not being mentioned. So, whatever AHV supports AHV also supports, but this is a meant for a low performance systems. So, naturally it will area requirement will be less compared to this complexity in field as here and power consumption also will be less. So, this is a design a choice is the use AHV or AHV. What is APB? It is advanced peripheral bus and by APB is a low power peripherals, it is for low power peripherals, it is optimized for minimal power consumption and reduced interface complexity to support peripherals. So, the interface is simpler, it is not complex design and minimum power consumption. ADV can be used in conjunction with the either version of AHV or AHV. So, APB can be connected used along with the either of this ok as I told you where processors and memory will be using these busses that means they will be residing on this bus and all low power peripherals will be on APB. So, they can be APB could be used along with this or this. A compatible bridge either AHV to APB or AHV to APB model is used for connecting the APB. So, there should be a bridge as I told you a high performance bus cannot be connected to a low performance bus directly. So, there should be a bridge I will tell you why it is required and how it helps in satisfying both the requirements ok. Let us hold on. Now, before that let me give a just a small overview of what is a macro cell ok. Those who are not from design background will be able to appreciate this. So, as it is a chip which is made bridge custom made for a particular application ok the name clearly mentions that application specific integrated structure chip. So, a macro cell array is an approach to the design and manufacture of APB ok. It is a one way of doing things may be not a complete as it may be a part of it. So, essentially this is a small step up from the other similar gate array design ok. Gate array if you are aware it will be provided with a different gate ok and then may be more nine and nor gate will be there ok. And then of course, some buffers and you know individual and all that. So, these kind of generic gates will be provided and then they will be connected according to the structure pattern. So, you may realize any structure using different generic gates or may be a specific nine and nor gates or you know the you know generic gate, but they will be could use other gates also to this you know implement a a final system executory which is a gate array rather than prefabricated array of simple logic gate the macro cell array ok is prefabricated array of higher level logic function. That means, instead of designing you know having an array of you know simple logic gate it is a free prefabricated high level logic which are a flip flop or ALU function for registers and that. So, you know these are the registers may be there and then you know may be flip flop will be there ok. So, this kind of thing may be ok or ALU functions ok. So, multiple may be 1 or 1 or 2 multiple will be there and then how they are connected is what is decided during the later stages ok. So, so macro cell enables in building such a solution with the basic functions which are high level logic. These audio functions are simply placed at regular predefined positions and manufactured on a data. A standard cell library is also sometimes called as macro cell library. So, they are later on they are interconnected to realize the final functionality that is required ok. This is just a to give you a role view of what is a macro cell. Now, typical AMBA based micro controller before we go into the detail of each of the birth and how birth contract can happen. Let me tell you a typical implementation of draft this is a one SOC ok which is having both AHB or AHB birth and AHB birth. And it has got a bridge bridge between the high performance birth and a low power low performance birth. And what are these devices they are all devices which has got very very low bandwidth bandwidth no bandwidth devices where is the data generated by these devices are all comparatively very very low rate ok very low rate. You can imagine I know how many key key entries can be generated from a key go is basically our our limitation on how many key that we can press. And this may be different you know may be it could go up to few kilo rates, but still it is not as big as gigabit range of transaction that happen over this birth. So, here they are 2 bytes or may be kilo bits of data here 2 gigabits of data that is the second of course ok. So, you can see the difference between these two I know almost around 10 power 6. So, that is why the bridge is coming in. So, this is the right time may be I can define now I can tell you something about what the functionality of a bridge here. So, suppose if any of the processor ok this is the ARM processor and then this is the ARM chip RAM and then the DMA and external bus interface memory. So, memory external memory is connected to this interface. So, this could be a master and this could become a master and so, this will be a slave memory and this will be a slave in the AHV bus or AA3 bus. Now, this master ok master is one which initiates transaction on the bus and slave responds with the whatever the master ask for. Now, this master could communicate your peripheral also. So, you might have written some code or may be a device driver interface with the you know connecting to the UR. So, now the ARM processor is talking to the peripheral means or you are trying to write one character into the bus into this particular register which needs to be UR to be connected to a PC may be ok. Let us assume this is a PC is there a fpxv or fp ok. These are all transmit and receive ok data flows in this way and data flows here. So, characters will be sent over the serial bus ok some board rate may be 9600 board rate to 11.7 kilo. So, 9600 is a standard may be we can say that this is a board rate. So, every character may be generated by this processor and then it is writing into the UR. Now, what happens UR is a very slow device. So, connecting into that if it waits for UR to give back acknowledgement, it will be unnecessarily holding this bus for long which is meant for a few gigabytes of transfer. So, it is not worthwhile to make this bus wait for some transaction over with the low performance devices low data rate devices. So, to remove that particular delay in transfer you know in interfacing with the or you know talking to these devices there is a bridge here. So, which is actually helps in buffering the data which is coming from either here or in this direction and then completing the remaining transaction. So, the on processor if you want to write into the UR it writes into this and then bridge says that ok I will take care of this talking to the UR. So, you can go ahead with the transaction. So, the transaction gets completed here and it can communicate with the bus memory or it can cut off with this or it can initiate from DMA with the memory whatever it can do. So, this bus is speed up for the next transfer while this bridge is helping in terms of completing the previous transfer that arm has neglected. So, that is the job of a bridge ok. So, APB bridge is always connected to the ASB, AHB or ASB through a bridge. So, that is it does not impact the performance of this bus ok. I hope this is clear to you. Let me tell you what each bus features are. High performance of course, pipeline operation what I mean by pipeline is when an address transaction happens ok. If the bus transaction actually you can street it into multiple things. So, address and data ok. Suppose if it is a re-cycle address will be generated after sometime the data will come from memory. So, in a pipeline operation while address is generated for the previous cycle and the data is yet to come another address generation could happen ok that transfers for another transaction that know something do with the we can overlap the operation that basically no typical to pipeline in the instruction where one instruction will be in a fetch stage and another instruction will be in a decode stage and another one will be in a typical stage. The bus transaction also can be in different stages. So, that is called pipeline operation. So, because of that the efficiency of the bus is improved. So, the bus is not ideally at any time waiting for some memory to respond the some other transaction can be initiated. For examples suppose arm wants to know write something into this bus or read from some this memory it will take some time for it to respond back to the data. By the time may be dmx can initiate some transaction with this external bus. So, address can be put here and it will be resolving that address for it to write something from may be know from RAM to you know external RAM or from some other peripheral here connected another processor here. So, or some other memory ok in a memory to or peripheral to memory whatever it is. So, when multiple transactions happen it could be pipelined. So, that is what is the advantage of the AHU bus ok sorry. So, multiple masters could be there. So, another processor can be there. So, this could be a master or arm could be a master or GNU also could be a master. Bus transfers are possible. That means, one arms equation cycle followed by multiple sequential cycle. Split transaction is possible multiple transaction can be split and they can be executed. So, the effectively the idling time of the bus is minimized ok. There is a features of AHB. AHB similar thing to you see this only these two are not there in the AHB. Because it is a complexity is less and it is for low performance devices where you do not want a complexity of AHB then we can go in for AHB ok. Now, what is APB advanced peripheral bus which is a low power latch to address and control, simple interface and suitable for many purpose. So, now you can get multiple peripherals can be connected there ok because of the latch to address control very good. So, now let us go into some more details of AHB. This is a typical bus transfer of AHB bus. You see here everything is appended with H to stay this is AHB signals ok. And H clock is the similar to M clock we saw ok main clock in the arm H clock is for the AHB bus the main clock. So, initially it is address phase and then the data phase in the clock. So, address is put in here assume that it is a read data ok. So, write data it could be this is showing you write data what is the happening in the read data ok. And here what is assumed is data width of 32 bits ok. It could be as I told you it could be very different age to 1024 bits. So, in a transaction you can transfer 1024 also bits also in one transaction, but the recommended is typical bit. And then what happens is during this address phase address is given ok and then the write data is available in the data phase. When after this H ready ok by the so memory is if you are the processor this is coming from processor suppose this is coming from memory you are sorry master it could be a on processor ok. It wants to transact over the bus with the memory. So, slave is a memory correct. So, if you it wants to write the data into the memory. So, the memory has to tell whether it is ready to accept the data by H ready is a positive value. So, when it becomes high it means that it is ready to accept the data. So, when this is made high then the data is put. Now, suppose in this clock cycle also if this remains continues to be low what will happen that is called the weight space. Because the memory wants to add more weight space because it is still yet to decode the address or the memory is a slow device it is a low you know performance memory. So, in the case it can in it know it can put some weight states by extending this it will not make it high and then it will delay the transaction. So, the master on has to wait for make data available until this goes high. Once this goes high in this way ok clock cycle then when it becomes low the data is made available and the memory can fetch that during this time it it will take the no data which is available on the bus and then it will bring down this value. So, if it happens to be no sequential access may be it will continue to how hold it and then it will give the other data that is to be data and what about this this is for reading the data. So, when it says that I am ready to provide the data then the master can read the data from here. So, it is showing a write data from master to slave this is a reading a data from slave by master ok. So, the data will be available when the ready the ready from a slave is made high I hope this is clear to use this particular transfer. Now, I mentioned that there is a centralized arbiter in the bus why is it required? Because multiple masters are supported in the AHB bus there should be an arbiter. If there is there was only one master in the system then there is no need for an arbiter. So, this is only what going to be initiating any transfer. So, this master is in control of the bus and he does not have to worry if anybody is using the bus or not. But once there are multiple masters in the bus then everyone everyone needs to make sure that the bus is free for the master to transfer over the bus. So, to unless otherwise there is somebody who is centralized and comes looking at the transaction happening over the bus the individual masters may not be aware of what is going on. So, that is why the centralized arbiter takes care of giving access to the bus ok. So, it can even associate some some master as a default master that means if nobody else is asking for the bus the default master will be given the control of the bus. So, if the default master will be suppose this is the non-processor maybe we can make it as a default master that is configurable. So, if no one else wants a bus this will be given otherwise there will be a priority and then accordingly the arbiter decides about who will be having the control of the bus at any particular point in time. So, this kind of what all the you know interfaces with the arbiter and the master there is a bus request coming to the arbiter ok. Requests coming bus request coming from the master to the arbiter and a grant going ok grant going to the particular master. So, how many such lines will be there with every ok master there will be a request and grant connection ok. One will be in this direction one will be in this direction ok request and grant. So, arbiter gets all the request from everybody every master in the system and then it chooses one of them based on some priority ok and then gives access to one of the master. So, grant it will be only one maybe it has chosen this then only one master will get the grant and then they then the master will get the address or data based on whether it is a right may be it is right for the data if it is a reset. So, this is how the AAP bus connected to by different masters communicate over it with the different layers. So, what is the order before any master wants to construct over the bus they need to get the permission from the arbiter which is a centralized arbiter looking at all the request coming all the master should be connected to the arbiter like I please go here and then they will be granted bus at a particular time. So, what happens one of them will be based on the choice one of the address coming from any one of the master will be going to the bus and then based on the choice again the data driven by ok data driven by any of the slaves will be going to the particular master ok only one will be driving anyway one of the slaves because based on the address one of the slaves will respond and then it will be given to the particular master and this must takes care of to see the particular master based on the grant given by the arbiter and then what happens the decoder the data coming is decoded and then it is given to the particular master ok three data master so this is this is how the interface is between a between the set of slaves and the set of masters in the ALHD bus ok I hope this is clear to you so AMBA AC bus protocol is designed to implement a machine master system unlike bus in architecture design for PCT base system the AMBA AC bus avoids price state implemented it avoids price state implementation where which is not a PCT based system ok the bus is not going to be on the PCT it is going to be on the inside the chip it employs central multiplexer interconnect mean ok so it is not the other devices need not have to be in a price state condition because there is a much in the system it provides high performance and low power than using price state buffer so because of that the performance is better and the low power also is as good if it is price state is now every device needs to drive the bus it will take some time for charging the bus because of the capacitive effect there will be the time taken for signals to stabilize on the bus will be longer ok in a typical price state system whereas if it is a max based system everything is actually connected but power may be a problem but the thing is it will be easier for in terms of achieving the power ok performance and it is a low power than using the price state buffer ok because it is not too many charging or recharging you know discharging of the bus so because of that the power this dissipator or buffer power consumed by the bus or the signal over the buses will be minimized the transactions are less ok if number of transaction over the bus is reduced then the power transaction will be less all bus the address and control signals indicating the type of transfer each bus or bus and then central orbit determines which bus or bus and the control signals routed to all the sleep so you know all between different lines or chooses the particular bus ok it grants the bus for a particular bus then that bus and the control signal what is the control signal that is control signal talks about whether it is a read or write whether what is the width of the transfer ok or may be a byte transfer so this kind of a different things can be communicated over the bus a central decoder structure selects appropriate read data and responds acknowledgement from the slave that it that is involved in the transaction so particular responding they know data coming from the slave device has to be connected to the master who is holding the bus so may be who has initiated the transaction so that person master will get the data coming from the slave I hope this is clear to you now data transfer it is a pipeline or tenured bus so address space of any transfer can accept during data space of previous time so it is overlapping address and data spaces ok of different transactions are overlap this is what is called pipeline or tenured bus because of this overlap performance of the bus is improved ok now what is the read rate suppose one transaction suppose you know it has got a non sequential address first address is non sequential and then the remaining addresses are sequential that means once this transaction is done then the next address would be then a plus 4 may be you know based on the territory or whatever a database so that is what is plus 4 is shown ok so this is the what type of transaction is happening non sequential or sequential ok and then why is it idling now idling signal is generated when the slave response with a read rate or it says that hd is low that means the after this transaction was completed ok hd is low that means the peripheral or the slave device has read that that I am not ready to accept the next transaction so because of that ok there is a read rate that means the data what was initially given ok the address and the data what was given is not may be written into the memory properly may be there was some problem may be there was a corruption in the data because there may be a parity check could be there and then may be because of glitches on the bus that means data could be corrupted and in the case that device memory device can initiate a read rate that means the same data is again address and data may be put on the bus for that to be accepted by the slave device so the I am giving a read rate example here and then burst transfer there you know we can have a multiple transaction for a first non sequential so different addresses are given now as you see that ok if you see there is a burst transfer that signal is sent that means it is communicated to the devices that the burst transfer is happening and then the different data for us basically those addresses are given on the bus ok so they are all provided you see here it was ready in this case and then it became low and then it becomes continue to be high that means it is ready to accept the data continuously so because of that becoming low you see this 38 is coming again ok it is kept for long and then this data is coming here ok this address is given this is delay actually and then because of that you see that this transaction is also taking more cycle after that the cycles are one to only this is taking 2 clock cycle because this device a slave device has said that I am not ready to take it take that particular transaction because initially the non sequential cycle takes more time after that the rest of the accesses will be solved you know faster so sequential class cycle that is why non sequential accesses will get more time it takes more time and then sequential accesses will become faster later on so it starts accepting all the data coming later so this is one typical example of the signal transaction I if you are not able to follow this please pause it for a while and then understand the sequence because this is very important to understand how the different signals are helping in constructing over the bus now what is the speed transfer what happens is one during one transfer a grand signal is withdrawn and then for a slave signal to split and then also changes the grand now no master raise that that means once the slave raise that see one master is communicating and let me explain one master is communicating this one slave may be call it as M1 and S1 now S1 says that I know slave signals a split transaction I like to have this transaction to be split that means this transaction bus cycle is terminated for now interminately and then during that time the arbiters could give the bus to another transaction between a master and a slave so new master raise that so that is why you see that another non sequential there is an ideal cycle because the arbiters take some time to grant the particular master and then the master has to drive the bus so this cycle is used for arbiters to choose another master and then communicate to the master so that the other master there should be something pending some grand request is pending so that arbiters could give a new master to use the bus and then it is generating another master and a different control signals and that transaction happens so the split transaction is communicated for breaking a transaction happening and then the arbiters decides and then gives the control to the bus to some other master so this is one particular example of that so what are the bus width scenarios one way to improve bus width without increasing the frequency of operation is to make the data part of the unpiped bus wider so this is possible I told you this minimum of 32 is used or maximum of 232 because even increasing the bus width is a little bit though it improves the performance there is a stability reliability issue might be there so they are recommended with the this for both read and write transfers the receiving model must select the data from the correct byte lane on the bus so as earlier if you remember if byte transfer is happening in particular odd address or even address a particular word byte sorry this is the word byte if suppose it is writing only this byte then maybe the same value can be driven on all the buses and then I was saying earlier that based on the memory which is there it could take this value and then internally it can write into a particular location in the memory but this actually the same data over the multiple buses actually increases the power consumption so in this case in the AHB the correct byte lane on the bus needs to be driven we do not have to replicate the data on all the byte lane okay so the module must select the data from the correct byte lane so any peripheral or a slave connected to the AHB bus should be capable of specifically based on the address you know which byte lane has to be used for reading the data this slave device should be aware of and then you should do it accordingly you are reading or writing replication of data address always lane is not required okay now let us search upon simple small introduction to APB so APB has three states one is ideal state and active state and enable state so these are the signals it will be in ideal state where nobody is driving the bus no power is drawn and it is all the devices are not into transacting over the bus and then if anyone wants to drive on the bus then it is into setup phase and then based on the transfer multiple transaction happens then it will be in enable and then setup phase it will go into this if no transfer is there then no state of the bus goes to ideal state okay this is the kind of a trans state transition and this is a select a particular peripheral device will be selected if it is one okay and then that will be enabled to transfer over the bus so here if you see all the signals are connected with the P that means it is to show that it is a very APB bus signal whereas AHB signals were given H as a prefix now APB state ideal state the default state for the peripheral bus setup when a transfer is required the bus moves into the setup phase where appropriate the select signal is asserted only one will be asserted okay and then the bus only remains in the setup phase for one clock cycle and will always move to the enable state on the next writing H so once it is set up it is actually one particular device in the APB bus then it will be in a setup phase after that it will be enable phase so that peripheral will be either reading or writing to the bus so enable in enable state what happens the enable signal P enable is asserted and after that write select signal remains stable during the transition of some setup to enable so either write or select signal will be active during the time so this is a typical transaction over the APB bus this is a clock this is actually a low frequency clock so address is given okay it is valid here and then the write signal is given that is writing into this address with a particular data and then a particular peripheral is selected and then enable so this is the from ideal state it enters okay so okay yeah so what happens it is in the idle state here and then it enters the setup phase and then enable state once it is enabled it is in the enable state so this is a setup phase setup this is enable state okay and then this is the idle state and the write signal continue to be idle where they are not driven below in order to reduce power consumption the address signal and the write signal will not change of a parameter until the next access access see as I told you when there is not much of no signal transitions then the power consumption will be consumed consumption will be reduced so to keep that and it is not tri-stated as you remember this is not tri-stated verse the peripherals may not be taken off from the verse or the bus may not be tri-stated so the address signal will remain whatever the earlier cycle whatever the address put on the verse it will continue to be there on the verse until the next select is happening and then the next address is put till then there will be same address and drive signal will be made so that is the read transfer this is the read transfer so the data comes in late so the device is selected and then enable and the data is driven by the peripheral device master reach from the slate read transfer I hope this is clear to you very simple so ATT bridge so this is the kind of ATT which I mentioned so all the you know the P data and all these are connected to this and then the system verse to the system verse either it could be ASB or ASB this particular ATB bridge looks like a slave so that is why the slave interface is connected so the AHB bus or AHB bus will be on this side connected to this so we are not showing any of the state signals here so it is from the AHB bus this is one of the slave device and then rest of the signal are all on the ATB bus side so APB bridge is the only bus master on the AMBA APB so AMBA APB APB bridge is the only bus master in addition the APB bridge is also a slave on the higher level system bus so on the ATB side the bridge is the master okay this is what is going to actually mimic any transaction happening between the devices on AHB side to the APB peripheral so actually this is the master as far as APB is concerned on the ATB bus the APB bridge is the master whereas on the AHB side this is a slave so this is AHB side all from APB and this is APB side it behaves like a master on this side and behaves like a slave on this side so whatever data is coming from AHB is buffered here and then later on delivers by choosing a particular one of the devices slave devices and then generating these the address would have come from this so it will varies on this address it will know which particular device is selected and then it drives the same address here may be modified and then particular peripheral device will be selected and with the data what was given suppose it was a read or sorry write the data is already buffered and address is also buffered both will be driving here so by the time this master who was actually originally driving this would have gone into some of the transaction may be happening on the AHB side whereas this is still going on on the APB that is what is the advantage of having a bridge so with this we have come to end of this session which talked about all the AMBA architecture this is the very very high level overview of these buses and I think with this introduction if you can read based on your intent or based on what you are trying to design or build either as a hardware designer or as a software developer you should be able to read through all the manuals of the different buses and understand more details about how certain things need to be interpreted in a SOC so I am very happy to share this with you and see you in the next lecture maybe looking at some of the peripherals so we will be talking about some peripherals in the next lecture okay have a nice day thank you very much for your attention bye bye