 Hello and welcome back. In this section we will cover the dedicated peripherals that can run in the low power modes. Let's start with the digital peripherals and the RTC. The RTC is designed to run in all power modes of the device, dependent on which clock source is used. As you can see from the block diagram, the RTC peripheral is fully functional with a wake up timer, alarms, tampers and a timestamp event. The RTC configuration registers, including pre-scaler programming, are not affected by system reset, except power on reset. When clocked by LSE, low speed external, the RTC clock is not stopped and remains active under system reset, again except for power on reset. The calendar in the RTC is expressed in birecoded decimal format with a sub-second register. Access to these values is done via free shadow registers. The wake up timer is a separate section in the RTC block, clocks from the same clock source as the calendar via a pre-scaler or the 1 Hz clock directly feeding the time register of the calendar. This 1 Hz clock, depending on configuration, can provide events from 1 second up to 36 hours with 1 second intervals. This section can provide wake up events independent of the calendar to bring the device out of low power modes, including standby. The backup domain is another separate section in the RTC block. Resources which are included in the backup domain are available and left untouched even in standby mode. Their configuration is not changed even by system reset. The backup registers are reset when the readout protection of the flash is changed from level 1 to level 0, or when a tamper detection event occurs except if the no erase bit has been set. Digital calibration is used to compensate the quartz inaccuracy and accuracy variation with temperature and aging. The accuracy which is given here is the resolution of the digital calibration. Final accuracy in the application would depend on the crystal parameters precision, temperature detection precision and how often the software calibration procedure is launched. In order to reach the precision of the calibration window, the measurement window must be multiples of the calibration window. All RTC registers are right protected even after reset. To modify the RTC, a specific function is required as shown. The two tamper input events can be configured either for edge detection or for level detection with filtering. The tamper detection can be configured for the following purposes. Erase the RTC backup registers, generate an interrupt, capability to wake up from stop and standby modes, generate a timestamp or generate a hardware trigger for the low power timer. Let's now have a look at the low power timer. We have two operation modes, continuous mode where many counter overruns are possible or one shot mode where the counter stops counting when the overrun value is reached. We have up to eight external triggers or configurable. We have up to five clock sources to achieve the lowest power consumption, four internal and one external. So the low power timer can be used as a pulse counter which can be useful in some applications. And we also have up to six interrupt sources available. The glitch filters protect either external or internal inputs with digital filters that prevent any glitches or noise perpetations to propagate inside the low power timer. This is in order to prevent spurious counts or triggers. Before activating the digital filters, an internal clock source should first be provided to the low power timer. This is necessary to guarantee the proper operation of the filters. The two 16-bit auto reload and compare registers are used to generate several different waveforms on LP-TIM output as shown. The free modes require that the auto reload register value be strictly greater than the compare register value. The encoder interface mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection. The low power timer counter can be used to count external events on the LP-TIM external input one pin or it can be used to count internal clock cycles. When the low power timer is configured to be clocked by an internal clock source and the low power timer counter is configured to be updated by active edges detected on the LP-TIM external one pin, the internal clock provided to the low power timer must not be prescaled. The LP-TIM external one pin is sampled with the internal clock provided to the low power timer. Consequently, in order not to miss any events, the frequency of the changes on the external one pin should never exceed the frequency of the internal clock provided to the low power timer. In case the low power timer is configured to count external events without the need of an internal clock source due to the selected low power mode, the signal injected on the LP-TIM external one pin is used as the system clock for the low power timer. Therefore, there will be some initial latency before the counter is incremented. And finally, let us look at the low power UART. The low power UART is a UART which allows bi-directional communications with a limited power consumption. Just by using the 32.768 kHz low speed external clock source allows the UART to communicate at up to 9600 bpm. Higher board rates can be reached when the low power UART is clocked by a clock source different from the LSE clock. This new clock source means it can be clocked even during stop mode. The board rate for the receiver and transmitter are both set to the same value as programmed in the board rate register using the formula shown. The board counters are updated to the new value in the board registers after a right operation to the register. Hence the board register value should not be changed during a communication. If we compare the functionality of the low power UART to the other UARTs on the device, you can see the basic functionality is identical. All it doesn't do is the advanced dual functions. Now let us look at the analog peripherals. The device has an integrated zero power on reset, power down reset, coupled with a brown out reset circuit. The device is operating between 1.8 and 3.6 volts. The BOR, brown out reset, is always active at power on and ensures proper operation starting from 1.8 volts. After 1.8 volts, the brown out reset threshold is reached, the option by loading process starts either to confirm or modify default thresholds or to disable brown out reset permanently. In which case the VDD min value at power down is 1.65 volts, extending battery lifetime. For selected devices operating between 1.65 volts and 3.65 volts, the brown out reset is permanently disabled. 5 BOR thresholds can be configured by option bytes, starting from 1.65 volts up to 3 volts. The device remains in reset mode when VDD is below a specified threshold, voltage power on reset, voltage power down reset or voltage brown out reset, without the need for any external reset circuitry. The device also features an embedded programmable voltage detector, PVD, that monitors the power supply and compares it to a threshold. 7 different PVD levels can be selected by software between 1.85 volts and 3.05 volts with a 200 millivolt step. An interrupt can be generated when supply drops below the PVD threshold. The interrupt service routine then generates a warning message and or puts the MCU into a safe state. The PVD is enabled by software. Let's now have a look at the comparators. The STM32L0 embeds two ultra low power comparators with rail to rail inputs on comparator number 2. All terminals of both comparators are available on external pins. The comparators can be used as standalone devices or be combined into one window comparator. They can be used for a variety of functions including wake up from low power mode triggered by an analog signal, analog signal conditioning or cycle by cycle current control loop when combined with a DAC and a PWM output from a timer. Here are some of the typical parameters for the two comparators. Finally, let us look at the LCD controller. The LCD controller is a digital controller driver for monochrome passive liquid crystal displays. We've up to 8 common terminals and up to 32 segment terminals to drive 128 at 4x32 or 224 at 8x28 LCD picture elements. Double buffered memory allows data in LCD RAM registers to be updated at any time by the application firmware without affecting the integrity of the data displayed. The LCD controller also fully supports the low power modes. The LCD controller can be displayed in sleep, low power run, low power sleep and stop modes or can be fully disabled to reduce power consumption. Used LCD segments and common pins should be configured as GPIO alternate functions and unused segments and common pins can be used for general purpose IO for any other peripheral or alternate function. The frequency generator consists of a pre-scaler, 16 bit ripple counter and a programmable clock divide factor of 16 to 31. The frame frequency is the frequency used to communicate with LCD devices. The user configures this frequency to be in the operation frequency range of the LCD. Here we have an example of the letter A on a 16 digit display with regards to the LCD RAM. Common signals are generated by the common driver block. Every common signal has identical waveforms at different phases with the settings shown. The segment driver block controls the seg lines according to the pixel data coming from the 8 to 1 mux driven in each phase by the common driver block. The LCD power supply source may come from either the internal step up converter or from an external voltage applied on the VLCD pin. In case of external source selected, the internal step up converter is disabled to reduce power consumption. When an external power source is selected, the VLCD voltage must be chosen from a specific range in the datasheets. The contrast can then be controlled by programming a dead time between frames. When the setup converter is selected as the source, the VLCD value can be chosen among a wide set of values from contrast control bits inside one of the registers. New values take effect at the beginning of a new frame. Internal resistor networks are used to generate all VLCD intermediate voltages required. Actually, one with low value resistors and one with high value resistors, which are respectively used to increase the current during transitions and to reduce power consumption in static state. Devices with VLCD rails offer the possibility to connect internal VLCD rails to optional capacitors to improve decoupling capabilities. Thank you for listening to this section.