 Welcome to the presentation of the STM32-G0-UCPD USB Type-C Power Delivery Interface. It covers the main features of this module. The UCPD units embed a PD physical layer of PHY with a direct connection to the configuration channel pins CC1 and CC2. The UCPD can be configured as a downstream facing port. DFP in short form or an upstream facing port, UFP in short form and also supports the fast roll swap protocol that enables swapping DFP and UFP states. In order to implement the protocol layers based on message exchange over CC1 or CC2, the UCPD offers a programming interface, enabling software to receive or send message payload bytes. Requests to external DMA channels may also be used to automatically transfer protocol messages to or from memory. The block diagram shows the two important parts of the UCPD module. The register interface on the left clocked by P-Clock that is used by software to configure and determine the current state of the module. Messages are transferred byte per byte by means of the TX and RX registers. The PD physical layer that encodes and decodes bytes appends and checks the CRC and also manages the transmission of ordered sets. The application benefits are integrated on chip PD PHY including RP and RD resistors. Dead battery mode supported, allowing connection detection at the peer device in a dead battery situation. PD message transmission and reception software is only in charge of handling the payloads. The UCPD controller is compliant with USB type C revision 1.2 and USB powered delivery revision 3.0 specifications. Regarding the PHY, only the CC signaling method is supported, so the type C cable is required. The reset and clock controller unit or RCC unit is in charge of resetting the UCPD unit by asserting the NP reset signal. It also provides the following reference clocks to the UCPD unit. P-Clock which is the APB clock used to access memory mapped registers and USB PD clock which is the main functional clock. USB PD clock can be pre-scaled in order to obtain the half-bit clock required by the by-mark phase coding. Note that for the timings called T-transition window and T-interframe gap, the clock frequency uncertainty should be taken into account in order to respect the timings in all cases. The UCPD module asserts clock request to the RCC in order to exit a clock gating low power state. This slide describes the pinout of the UCPD units. Pins UCPD XCC1 and UCPD XCC2 are the only signals to be routed to the USB type C receptacle. Note that the cable contains a unique CC signal connected to either CC1 or CC2 in the receptacle because the cable can be flipped. The UCPD XFRSTX pin is relevant when the dual roll port protocol is supported. It is used to control an external NMOS transistor that pulls down the CC1 or CC2 line respectively which is the way to request a roll swap. Pins UCPD XDBCC1 and UCPD XDBCC2 are used when the STM32G0 USB type C port indicates to the peer port a dead battery condition by connecting UCPD XDBCC1 to UCPD XCC1 and UCPD XDBCC2 to UCPD XCC2. The STM32G0 implements internal RP and RD resistors connected to CC1 and CC2 pins required by the USB PD specification 2. Detect a connection. Determine whether the cable is flipped. Determine the default available power as the current carrying capability depends on the values of RP. Finally, a unique CC pin CC1 or CC2 according to cable flip is used to transport PD messages. The unused CC pin may become the VCON pin which supplies the power to integrated circuits present in active cables. In order to conserve power, the unused CC pin can also be disabled by programming the CC enable field in the UCPD CR register. The UCPD is configured by software as either a downstream facing port or an upstream facing port. The DFP mode assuming no cable flip CC1 is connected to RP. The value of RP indicates the value of the default power that the DFP can source on VBUS. In DFP mode assuming no cable flip CC2 is connected to VCON. VCON is a 5 volt 1.0 watt power supply used to power devices within the plug that are needed to implement electronically marked cables and VCON powered accessories. In UFP mode assuming no cable flip CC1 and CC2 are connected to RD which is a 5.1 kilo ohm resistor. Since the UCPD supports both DFP and UFP operation, the internal switches represented in the figure select the current configuration. When the UCPD is used as an upstream facing port, the dead battery feature enables the UCPD to indicate to the peer node that it needs to be powered. This analog setting is functional even when the MCU power supply is switched off. This default behavior is configured by connecting the DBCC pins to the respective CC pins. After power arrives and the STM32G0 boots, the desired behavior should be programmed in the ANA mode and ANA sub mode fields of the UCPDCR register. And then USB PD strobe bit has to be set to 1 in a CIS CFG register called CIS config. Connecting DBCC pins to ground disables dead battery mode. In this case, the peer DFP is unable to distinguish a dead battery state from an unattached state. The fast roll swap protocol swaps the roles of DFP and UFP. The default power source node becomes the sync node and the default sync node becomes the source node. To request an FRS to the source node, the sync device temporarily connects the appropriate CC line to ground. This is achieved by external NMOS transistors on both CC lines. However, only one will receive the FRSTX pulse. The NMOS on the inactive CC line should be driven with a logic zero level using GPIO mode. The FRSRXEN bit in the UCPDCR register controls the FRS detection in the sync node. When this bit is set, the FRS detection is enabled. The digital controller is in charge of USB type C level detection with debounce, fast roll swap detection, CRC generation and checking, 4B 5B encode and decode, bifazed mark or BMC encode and decode, transmission and reception of ordered sets. A clock data recovery unit in the receiver recovers the transmission clock from the received bit stream. The digital controller offers a byte level interface for USB power delivery payload, generating interrupts. A DMA channel can assist the transfer of message payloads because the UCPD unit is able to request DMA transfers. The UCPD module implements two clock domains, APB register interface clocked by P clock and PHY clocked by USB PD clock. USB PD clock is divided by a programmable prescalar to provide the CC clock, whose maximum frequency is 300 kilobits per second. Due to the bifazed mark coding, two transitions may occur per transmitted bit. Therefore, the actual maximum clock frequency is 600 kHz. The PHY monitors the state of CC1 and CC2, either continuously or by polling, to detect and signal events to the software by setting flags in the UCPD SR register. In order to optimize power consumption, it is recommended to use polling because type C detectors are off between poles, rather than wake up from stop, which requires type C detectors permanently on. The static level on the CC pins is determined via threshold detectors in the PHY to give a voltage range value in registers, facilitating the type C state machine implementation in software, and also allowing the cable orientation to be determined. The type C debounce subunit filters events to be reported to software. It is also in charge of ensuring the coordination between event signaling and power delivery, TX, and RX activity. The PD software stack is executed by the Cortex M0 plus core in the STM32G0. It is based on messages and events. Events are reported to the Cortex M0 plus core through interrupts. Regarding messages, only the payload is under software control. The digital controller performs message encapsulation with preamble, start of packet, CRC, and end of packet. The software stack includes the protocol layer, the policy engine, the device policy manager, and the system policy manager. The system policy manager may control several PD ports in order to implement platform-level power management. Three software layers are defined in the PD specification. Layer 1 is device policy manager or DPM. It is in charge of device-level system management and monitoring. It determines the power plan and contracts depending on current power state. Layer 2 is policy engine or PE. It controls a single UCPD port. Message sequences are defined to request power resources, performing source or sync transitions. This layer implements power negotiation, swapping, and handles message flow errors and reset. Layer 3 is protocol layer or PL. It is in charge of constructing and deconstructing PD messages. This layer automatically returns good CRC when a message is correctly received and also handles transmission errors, such as timeout and retries. In addition to transporting data digits converted into 5-bit codes, the PD protocol also transports signaling patterns called ordered sets. They are composed of four 5-bit K codes and are tolerant to transmission errors through a redundancy mechanism. Ordered sets, such as start of packet or SOP, are necessarily present in packets. The digital controller automatically inserts them in the transmitter and strips them in the receiver after having checked their validity. The ordered sets defined in the PD specification are used to signal a cable or hard reset condition and delimit the beginning of packets. The PHY automatically inserts the preamble, the start of packet or SOP, the CRC, and the end of packet or EOP. The receiver PHY handles these fields and removes them. The header field and possibly the payload fields are entirely handled by software. The PHY does not interpret their contents. The preamble is not encoded. It is used by the receiver PHY to receive clock data. All the subsequent fields are encoded in the transmitter and decoded in the receiver. The Type-C connector does not support a dedicated reset signal. Consequently, reset conditions are signaled by using specific PD packets transferred over the CC line. Two types of reset are defined. Hard reset, which aborts the ongoing transfers and the cable reset, which does not require a high priority treatment. The sequence required to issue the reset packet is described in this slide. The PD specification describes built-in self-test or BIST packets used to test whether the CC line is functional. Bists are sent on a software decision based on fields in the UC PD-CR register. Software can enforce the transmission of a BIST packet and can also configure the receiver in test mode. Received BIST packets are not submitted to software, however their CRC is checked. Two formats of BIST packets are defined in the PD specification. BIST test data, which is a packet containing a payload used to test the digital controller. BIST carrier mode, which is a single-pattern, infinite-length message used to test the CC in an oscilloscope, for example. The Type-C state machine is implemented in software. The Type-C state machine depends not only on CC pin levels, but also on the port roll. In sync mode, it depends on the V-Bus presence detection. In source mode, it depends on the V-Con generation and the V-Bus state, on, off, voltage level and discharge. The UC PD module only controls the CC lines. Other modules are involved to control the V-Bus and V-Con power supplies. In source mode, GPIOs are required to control the power delivery dynamically. In sync mode, ADC channels are used to monitor V-Bus and V-Con supplies. The UC PD can be programmed to remain active in stop zero and stop one modes. The detection of a PD event while the MCU is in stop mode causes a wake-up condition, signaled to the EXTI unit and then to the PWR unit. The following events can be configured to cause a wake-up request. Events on the BMC receiver, such as message receipt, fast roll swap request, events on the Type-C detector, such as attachment and detachment. The UC PD is able to wake up the MCU from stop mode, if enabled by setting the WU PEN bit in the UC PD CFG2 register, when it recognizes one of the relevant events listed below. Type-C event relating to a change in the voltage range seen on either of the CC pins visible in Type-C V-State CCX or power delivery receive message with an ordered set matching those filtered according to 8 to 0 of RxOrdSetEN visible by reading RxOrdSet. At UC PD level, three types of events requiring kernel clock activity may occur during stop mode, Type-C, BMC, RX and FRS detection. In order to function correctly with the RCC, the clock request signal is activated if WU PEN bit is set when the following events are detected. Activity on the analog 5-voltage threshold detectors, which could later be confirmed to be a stable change between voltage ranges defined in the Type-C specification. Activity on power delivery, BMC receiver coming from the selected CC pin, which could potentially generate an Rx message event later, that is, RxOrdSet. Activity on power delivery FRS detector, which could potentially generate an FRS signaling detection event later, that is, FRSEVT. Type-C voltage threshold detectors coming from either CC pin, the power delivery receiver signal coming from the selected CC pin, the FRS detection signal coming from the selected CC pin. When an interrupt from the UC PD is received, then the software has to determine the source of the interrupt by reading the UC PD SR register. Depending on which bit is set to 1, the interrupt service routine should handle that condition and clear the bit by writing to the appropriate bit in the UC PD-ICR register. This slide summarizes all the events detected by the UC PD module that can cause interrupt requests. Please refer to the training linked to this peripheral for more information. STM32G0 DMA controller. Reset and clock controller. Extended interrupts and events controller. System configuration controller. Power controller.