 The purpose of this video is to explain the difference between two types of architectures that current microprocessors are having, which are called SISC and RISC. Let's first recall that a microprocessor is a digital circuit that is capable of executing very fast what we call machine instructions. These machine instructions, typically the way they look is initially they have an operation code, sometimes we just call it the opcode, and then they have several parameters, parameter 1 to parameter k. So this notion of instruction is what the microprocessor out there can execute. But then the question comes what kind of catalog is offered by the different microprocessors of these instructions to execute. And here is where these two different approaches emerge. The first approach, the CISC or SISC, is the acronym for complex instruction set computer. And the name is self-explanatory. The microprocessor with the CISC architecture offer the capacity to execute a fairly rich set of instructions, each of one is also capable of implementing sophisticated operations. Let's get an example. This is taken from a real microprocessor. Let's take a look at this machine instruction. Add $4, 14, %eax, %ebx, 8. As we can see this instruction follows the pattern we just described up there. The operation code in this case is add. The instruction is performing an addition and the parameters we described here are made up of these symbols in this expression. What this instruction is doing is the following. It's taking the number 14, it adds 14+, this is a register. The content of this register is added to the 14, eax, plus ebx is another register. And its value is multiplied by this number 8 we see at the end. And the result is added to a eax and 14. The result of this operation is a memory address. And the overall instruction is adding the number 4 to the data stored on this memory address. So again as we can see the microprocessor capable of executing this instruction has to perform several arithmetic operations. One addition, another addition, a multiplication and another addition plus an access to memory first to obtain the operand because we are adding the number 4 to whatever is stored in memory. So we first have to go to memory, get the operand, perform this addition and then deposit the result again in memory. So from the point of view of a microprocessor this is considered a complex machine instruction. Although there is no written rule about what it constitutes as complex or a simple machine instruction, the guideline here is that as you can see there are several arithmetic operations that are involved in its execution. So typically the microprocessors that have a SISC architecture, they provide a large number or a very rich catalog of instructions and some of them can do sophisticated operations like this one. Now large number of instructions means that it takes longer to execute. These type of instructions as you can see they have to perform several arithmetic operations, they have to go to memory, come back. So in this example we can see that it takes a little bit longer than another instruction that might perform some much more simplified operation. Now examples of architectures of this type are some of them that are recent, some other that are not so recent. For example IBM had a system called System360 that used microprocessors of type SISC. But perhaps the most famous one is the architecture of the personal computer back in the 70s which was called X86. Then it evolved into another architecture which was called AI32 which is where this example is taken from. And this architecture evolved into something else called AMD64 or X8664 or some other names. So these are just some examples just to show that these microprocessors are being used today. Now the interesting thing about this is that when we compare it to the alternative a very interesting trade-off appears. What is the alternative? Well rather than having a large and complex set of instructions the risk microprocessors appear as an alternative to this type of philosophy. And the acronym stands for Reduce Instruction Set Computer. So as we can see the philosophy here is in many senses the opposite is in here. Rather than having a microprocessor or a digital circuit capable of executing a large and complex set of instructions. What this type of architecture is going to propose is to use fewer instructions. So in other words this catalog we mentioned at the beginning will be much shorter and each one of them will be simpler. And this is perhaps the key observation. So rather than going for a large catalog of complex instructions the Reduce Instruction Set Computers propose using a much reduced set of instructions. And therefore each one of them performs much simpler operations. Now let me give you an example of the type of operations that would be carried out by a risk computer. This would be an example. As in the case of a SISC computer we saw here this is also performing an addition. But rather than adding a number to a location in memory this operation is only adding the content of register R7. This is what we mean by R7 here to the content of register in R5. Or another way of specifying that would be R5 takes the value of R5 plus R7. So in this example we already see the difference between the two philosophies. Here we have convoluted and sophisticated operations that do fairly interesting things. Whereas in here we have very simple operations. It is as if in this architecture what we want is to take very small steps when carrying out a computation. Now as I said before the interesting thing about these two architectures is appears when we compare them to each other. So if I want to carry out let's just say a generic complex task in this microprocessor. Well chances are I need to write of course a sequence of instructions. These instructions would be written here. And this instruction would have certain, this sequence would have certain size. If I am using complex operations that can perform sophisticated calculations it is very likely that this sequence will have a size or the number of instructions required is smaller, much smaller than the number of instructions or the size of the sequence that I need to perform exactly the same task in the RISC architecture. I will have again instructions but the size here is probably much longer. And the rationale is very intuitive. I can pack many more steps in one single instruction here therefore my sequence of instructions is smaller. Whereas in here if I take very small steps I probably need many more instructions to implement exactly the same task. However, even though we might think that this is worse because we are using many more instructions there is also another interesting trade-off. If my instructions are simpler they are also fast to execute. Why? Well because the type of operations that we are doing here is very simple. Whereas in here instructions in general take longer to execute. Why? Because it is a matter of packaging right? Here we are doing several operations in just one instruction whereas in here we need to execute several instructions to carry out perhaps the same calculation as in here. So here we have the trade-off and there is no clear winner. The two architectures are not comparable or not at the point of counting the number of instructions that are required. We will always get more instructions in the RISC world than in the SISC world. But there is another interesting trade-off. These instructions being simpler they are also very fast to decode. And by decode what we mean is that the microprocessor will have a much simpler task to detect what kind of instruction has been received in order to execute it. For two reasons. The first one is because we have a reduced set and the other one is because these instructions are simpler so we decode them very fast. Whereas in here probably we need some sophisticated decoding. So again we can see clearly the trade-off. In principle the circuit here is simpler to design. Whereas in here these microprocessors tend to be more complex because they have to deal with a much more complex type of execution. But as I said before there is not a clear winner between one philosophy and the other and today the two philosophies coexist. There is one little additional category that is worth mentioning which is orthogonal to SISC and RISC architectures which is the definition of or the classification of the microprocessor depending on the size of their instructions. We have two different types of microprocessors. Those that have fixed format for their instructions or length and those that have variable length for their instructions. And as you can see a RISC computer is much more likely to be close to this philosophy because if I have my instructions being very simple and all of them having a small number of operands it is very likely that all of them or most of them if not all will be encoded with a fixed format. Whereas in the SISC philosophy since I have so many instructions and some of them are so complex it is very likely that I have a wide variety of operands and that will force me to encode these instructions with variable length. So even though there is again not a written rule that tells you that every RISC computer has fixed format instructions and SISC computer has a variable length instruction these other classification based on the length of the instruction is also a feature that distinguishes microprocessors from each other and in some cases they go hand in hand with RISC and SISC. Let me finish just by give some examples of the typical RISC architectures that we have now and some of them would be for example the very well-known MIPS more recent one is ARM and an interesting one as well is the AVR Biomea.