 Hello, welcome to the lecture series on advanced VLSI design course. I will take you through the VLSI design verification process in this portion of the lecture series. In last lecture we discussed about various techniques for the design verification. One was the simulation or emulation based technique which is widely used in the industry. Another technique is the formal verification and we also discussed what are the differences between a simulation based technique and formal verification techniques. As we discussed that in simulation based verification we apply some test vectors to the input of the design. So, this design is in the form of VSDL or vary log code and then we check the output of the design and we verify with respect to or check with respect to the given specification or golden reference output. If there is a match in that case we say that most likely design is correct, but because we cannot apply test vectors exhaustively hence here we can never say that this design has no bug. So, we can say only the presence of bug, but we can never say the absence of bug if you use simulation or emulation based technique. Simulation is pretty slow process may be the speed is something like 1 to 5 hertz whereas the emulation is the emulation of the design on some reprogrammable logic like FPGA and that is much faster than the simulation and it is roughly 5 to 6 order of magnitude faster, but here the main challenge is how to find out the corner cases which you can exercise and test. So, it is like corner cases can be missed and then here you may miss some of the design bugs. Simulation based verification technique is very good for the initial design debug because here if you apply the random vectors even you are likely to capture some of the bugs whereas the formal verification technique uses some mathematical techniques to verify the design. So, now here what you need to do is how to supply the model of the or behavior of the design to the verifier and a set of properties and then it will tell you whether these set of properties are always respected by this design or they fail. If they fail then it gives you a trace of inputs under that it fails and that is known as counter example. So, like here say in order to model behavior of the design we if it is a sequential circuit then we can model that as a finite state machine and then what are the properties? Properties are something like if we want to design a traffic light controller then it is supposed to require not to give the green signal to both of the crossing roads. So, that is one of the property that we have to check whether there exist any state where in this can provide the green signal to both of the crossing roads. Other property could be like the signaling should follow some pattern like this red, yellow, green, red, yellow, green something like that. So, now here if the property passes in that case we can say that design is correct and this is so this is equivalent to all case simulation and if it is equivalent to all case simulation in that case here there is no concern about the corner case which can be missed say in simulation based verification. Now, here so there is no corner case with respect to given property hence we say that this is always correct for a given property. Now, here the challenge is to find out the complete properties of a given design. If you can verify for all the properties in that case here you can say that this design is correct in all respect and we can fairly rely on that. So, now here the what are the various challenges we have. So, this as I said that formal technique is based on mathematical reasoning and for the mathematical reasoning here we use the Boolean functions or Boolean algebra that is a propositional logic and in order to manipulate this here we use either satisfiability checker or binary decision diagrams. We also use the first order logic or higher order logic for the theorem proving. So, as I also mentioned in the last lecture that there are three kind of techniques we use in the formal verification one is the deductive verification. The second verification uses axioms and theorems to prove the correctness of design. So, it is like here you are either you prove this Pythagoras theorem mathematically or you take a scale and measure the both of the arms and then verify that. So, now we need to use a set of axioms like if you want to verify an adder in that case here its specification can be defined at more abstract way like in algebraic form. So, now if you add say 2 bit 1 1 then what would be the output and so now here if you have bit stream in that case here what would be the value of integer value of that bit stream and then if you are adding to bit stream in that case here what would be the outcome of that. So, that is at higher level of abstraction and then you have implementation of your design and you want to verify whether it gives you the same mathematical answer or not. So, now deductive verification as it uses axioms and theorems and then you have to use that in certain way. So, you need manual intervention in this technique is semi-automatic technique and it is bit difficult and more time consuming. The another technique is called as model checking in that you model your design like here if it is a sequential circuit as a finite state machine and then here you identify some of the properties and that you mathematically express and then you have to verify those properties on that given model checker. It is worth to mention that the inventor of model checker got during award very recently. So, you can see the effectiveness of the technique. So, now this technique is almost fully automatic technique. So, that means here you need to supply the model say as a very lower VHDL code. So, now your verifier will extract the finite state machine from your very low or VHDL code and then you express properties in terms of some mathematical logic and now here your verifier will check whether that property is respected all the time or not. So, now here the challenge is the number of states are exploding and then in order to complete the verification process in reasonable time here we use the symbolic algorithm like here we use binary design diagram to manipulate these systems. The third technique is equivalence checking. So, equivalence checking is like here checking of the equivalence of two designs. So, if you have two design in that case here both of the designs are supposed to produce the same output if you apply same primary input. So, now here like for example, if you design an adder that may be say ripple carry adder which is a cost effective in terms of area and you verified that with respect to the given specification that is mathematical specification you have may be using the deductive verification technique and after that. So, now here you minimize optimize that for say timing or something else. So, you have another design say carry look ahead adder which is more optimized for the timing. So, now you have one ripple carry adder another say carry look ahead adder ripple carry adder is already verified and now if you prove the equivalence of the carry look ahead adder with the ripple carry adder in that case here you can say that both of the designs are respecting the specification. So, if this equivalence checking is again another technique and this is fairly automatic technique. So, model checking and equivalence checking are the fairly automatic techniques whereas the deductive verification is semi automatic technique and industry always prefer to have a technique that is fairly automatic. So, that here human error cannot be introduced in that. So, now here first I will start from the combinational equivalence checking and so then again there are two parts one is the combinational equivalence checking and sequential equivalence checking. So, first I will start with the combinational equivalence checking then we will consider the theorem we will consider a model checker or a property checker. So, today's in the ASIC design flow if you look at the use of the combinational equivalence checking then you will find almost everywhere the combinational equivalence checker is being used. So, this design flow we discussed earlier that here you start from the RTL design you synthesize that you will get obtained the gate level netlist then you need to check whether you are obtained gate level netlist is equivalent to the your RTL design or not then you do the testability analysis and you insert the design for testability. So, after DFT insertion again you need to check whether your gate level netlist is functional equivalent to the the synthesize gate level netlist or not the after that you insert IOR and then you do the the placement routing and the so and then you introduce the clock tree at every stage you have to check whether your new transform alter the functionality or not. So, that means here before transformation and after transformation the functionality remain equivalent or not. So, now you can see the use of equivalence checker in today's design. So, as I said that here this combinational equivalence checker is currently the most practical and pervasive equivalence technique we have it can it is almost fully automatic technique. So, that means it is push button kind of job you say that submit to designs and say now here check for the equivalence it will tell you whether both of the designs are equivalent or not if they are not equivalent in that case it will return you the the trace or input vector that can give produce the different output from the two different designs. Now the combinational equivalence checker can also handle the millions of gates. So, that means here you can do almost the full chip verification. So, that means here if you have millions of gate in one design millions of gate in another design and if you want to check whether both of the designs are equivalent or not. So, you can almost handle handle the full designs. Problems so combinational equivalence checker is still a small portion most of the circuits are sequential circuits and now they the if now when you go for the sequential equivalence checker in that case here your design space explodes in order to handle that here one of the ways most of the people do use is you can formulate or convert the sequential equivalence checker problem as a combinational equivalence checker and then use the conventional combinational equivalence checker to check that design. So, if you look at the current industry offering for combinational equivalence checker in that case here you will see wide variety of tools are available like here formality from synopsis conformal suit from the cadence formal pro from the mentor graphics. So, and these tools have the enormous capability. So, that means they can handle several million gate level net list and they have the comprehensive debug capability that means here you can localize the bug. So, that means here why these two designs are where the bug is and some of the tools have the what if kind of capability as well. So, now here let us more look closely the combinational equivalence checker problem what means we want and how this is being done. So, for the combinational equivalence checker here you have two designs design A and design B and when I say apply some input to design A and design B here these two designs are supposed to produce the same output if they are producing different output in that case here both of the designs are not equivalent. Now, the question is may be for some of the inputs two designs are can be equivalent, but for some other input two designs are not equivalent. So, now here one of the ways is that we need to find out or we need to check whether for all the possible inputs both of the designs are producing the same output or not. Like here as I discussed in the last lecture if I have an OR gate and XOR gate. So, say I want to implement XOR gate and by mistake I have implemented OR gate. Now, here if I want to verify in that case here three inputs out of four inputs for the two input OR or XOR gate both of the designs are producing the same output and if I am checking for the those three inputs in that case here I will say that both of the designs are equivalent. So, like here 0 0 0 1 1 0 OR and XOR will produce the same output. So, now the complexity is we need to check for all the input and as I mentioned that here we cannot exhaustively check that because here this application of input and getting the output and checking whether outputs are same or not that is called as simulation based verification. So, now here but what we want we want to verify these two design that should give me the capability that both of the designs it is like here for all case simulation. So, now the one of the good thing with the equivalence checker is that we have seen earlier as well that this can be applied at one level of obstruction or across the level of obstruction. So, that means here you can check the gate level net list with respect to RTL, RTL with respect to gate level net list or RTL with respect to RTL gate level net list we say this gate level net list, gate level net list with your transistor implementation and so on and so forth. So, and that we have seen in that we are almost at every stage in the design transformation we use equivalence checker. So, let us go little bit more inside the theory of equivalence checker. So, say if you have these two designs design A and design B and I want to check because here these two designs are these two designs look differently if you look at the structure, but now here the question is if you want to check the correctness of these two designs or equivalence of these two designs in that case here you have to say that if for all possible inputs here output of these two designs should be same in that case we can say that both of the designs are same. So, now one of the ways is that you generate the truth table and check the entries in the truth table, but now here say assume I have 100 inputs to a design then you need to have 2 raise to the power 100 2 raise to the power 100 entry in the truth table and so now first thing is you have to store that and 2 raise to the power 100 is roughly 10 raise to the power 30, so that means here 10 raise to the power 30 storage location at least you need. So, that means here you cannot fit your total truth table in the storage space and hence that is impractical. So, now here you have to have some way that can represent that can have unique representation of this circuit that can have unique representation of this circuit. So, that means here if both of the functions are equivalent in that case here their unique representation must be same and now I can check that unique representation. So, the other thing like here you can say that the truth table is unique, but this is not manageable this is not compact. So, I have to I want to have a unique representation which is compact and easy to manipulate. So, these are the two requirement and we will see that. So, binary decision diagram is one of them. So, now here then there are two ways to verify the equivalence of these two designs. So, say this is one design this is another design one of the way is you have design A you have design 2 and then you you need to check the both of the design. So, now here if I say I explore the output of these two output should always remain 0. So, for all possible inputs output should always be 0 here if I explore these two. Now, if I find out some way some set of input for which if the output of this X go or get is 1 in that case I can say both of the designs are not equivalent and that that is in input is known as the counter example. So, that here for that input both of the designs are producing the different output. Now, how I can how I can do that. So, one of the technique is these are the set based technique or ATB pg based technique. So, that means here in set based technique we search a input assignment that can give different output for these two different designs and now here set so say three set problem is NP complete problem. So, now here you need to use heuristic in order to solve this in reasonable time we can use the branch and bound in that case you have to backtrack and until you succeed. In the same way here you can use the ATPG and what ATPG do is like here this is design 1 and this is design 2 and now here what you want because for a given input output is always 0. So, this is corresponds to the output of the design 2. So, this is corresponds to that output is always structure logic 0. So, now here I need to test need to generate a vector. So, I need to generate a vector that can produce output 1 here if I can produce output 1 here in that case I can distinguish the behavior of two designs. So, now means I can use the automatic test pattern generation techniques there are various techniques like here D-algorithm, PODEM algorithm FAN algorithm in this series of lecture I cover ATPG algorithm in VLSI test lecture series. So, you can refer to that I do not want to repeat that. So, now you can find out a set of input that can produce output 1 here if you can obtain the that set of vector in that case here you can say that the both of the design means that is at least once set of vector that produces 2 different outputs from these 2 different designs hence these 2 designs are not equivalent. So, whether you formulate this as a SAT problem or you formulate this as an ATPG problem both of the cases the challenges are that most of the time finding out this assignment is complete problems hence here you need to exercise lot of inputs before saying see generation of test vector is easier, but here saying that this test vector does not exist is the most difficult problem and now here so and in this case when both of design A and design B are equivalent in that case here there should not be any or there does not exist any test vector that produce output 1 here. So, now here in order to prove that here typically you need to explore the significant prop portion of input space. So, that means here the timing complexity is exponential. So, now the way is as I mentioned earlier is that we can use either set based techniques or ATPG based techniques in that you want to find out a set of input that can produce 2 different outputs from 2 different designs if there exist such such vector in that case here we can say both of the designs are not equivalent otherwise we say that both of the designs are absolutely equivalent. So, that is the the challenge. Other approach is the functional approach as I explained earlier as well that if you can represent the functionality of your design by unique representation. So, as I said that truth table is one of the unique representation, but it is not economical in terms of storage space and so now we need to have a unique representation that is compact. So, and now here so if both of the designs are functional equivalent I can have the unique representation of both of the designs and then I can compare. So, if there is a match in that case we can say both of the designs are equivalent or both of the designs are not equivalent. So, now here functional approach I will discuss little bit more in detail. So, now here say these are the two designs design T1 and design T2 if these two designs are absolutely equivalent in that case their unique representation or canonical form of representation should be identical and that should be compact and binary decision diagram is one of the compact way of representation that is the graphical representation of a truth table. So, now here this is the binary decision diagram wherein you have the inputs and now here based on say like here if a is 1 b is 1 in that case here output would be 0 and if a is 1 and b is 0 and c is 0 then output would be 1. So, now here this way I can read. So, now here from this I generate the binary decision diagram for this circuit I generate the binary decision diagram for this circuit if then here I can match these two graphs. So, this is graphical representation. So, I can match these two graphs how I match these two graphs I have to match node by node h by h. So, now here it has 5 nodes and 5 edges and here it has 5 nodes and 5 edges I can match these nodes and edges and if they are equivalent in that case here I can say that both of the designs are equivalent. So, we can say that functions are equal if and only the representation are identical in this here we are never enumerating the explicit function values we are just generating a compact representation and then we are comparing that we also explored the structure and regularity in the structure. So, now here let us come to this point how you obtain the binary decision diagram. So, binary as I said that binary decision diagram is a representation graphical representation of a circuit or Boolean function. So, now here say my Boolean function is function of some input x 1, x 2 x i, x n now this function I can use the Shannon's decomposition theorem I can see this function is evaluated to 0 or 1 based on the value of these variable x 1 to x n. So, say I decompose this function with respect to some variable say x i. So, now here I can write this using the Shannon's expansion theorem x i into f of all the variable with x i equal to 1 and x n. So, this is the evaluation of function when x i is equal to 1 plus x i bar because x i can also take the value 0 f of x 1 x i is equal to 0 x n. So, now here I can represent the this is the value of function when x i equal to 1. So, I can represent this function as x i f of x i plus x i bar f of x i bar. So, f of x i is the value of function when x i equal to 1 f of x i bar is the value of function when x i equal to 0. So, this way if I can represent my function in that here I can generate a graph wherein x i is 1 node and so x i is my node and now here this is my function f of x i it will evaluate to this one this is my function f of x i x i bar when I get 1 then it will go to evaluate this one when I get 0 this will go to evaluate this function f of x i bar. Now here again this function will have all variable x 1, x 2, x n except x i in the same way this will have all variable from x 1 to x n except x i. So, now again I can decompose that with respect to another variable say x j. So, now here again I can say this is x j and I will find out a function that is x i x j and then here there would be a function of x j bar and this way I keep on expanding this and I will get the binary decision tree. So, this would be a binary tree because from every node there can be two branches. So, how this binary decision tree is generated let us say this is my function that is represented by this truth table. Now it has 3 variable x 1, x 2, x 3, x n. So, I start from a variable x i and assume that I evaluate my function in given order of variable and that order of variable say I decided x 1, x 2, x 3. So, now here if I have x 1 in that case here either x 1 can be 1 or 0 if x 1 is 1 in that case here this would be the function and if x 1 is 0 in that case this would be the function. So, now here when say x now you evaluate with respect to x 2 and then you will have an x 2 equal to 1 this would be the function when x 1, x 2 is equal to 0 then this would be the function now here again you have only one variable and evaluate with respect to x 3. So, now when you have x 1 equal to 1, x 2 equal to 1, x 3 equal to 1 then the output is 0. So, that is corresponding to this entry. So, now here every path in this binary decision tree represents one entry in the truth table. Now you can say that what we achieve out of this here we have number of passes equal to the same number of entries that we have in the truth table and for the large number of inputs it is not possible to store these things. Yes that is true but there are some ways to minimize this I will discuss those how you can minimize. So, now here in this truth table you have only 8 entries whereas here if you see then you have 8 plus 4 plus 2 plus 1 total 15 nodes right and 15 nodes and 15 edges. So, now here you means this binary decision tree is much more bigger than your truth table. Now here the question is how you can minimize that. So, there are couple of properties for binary decision tree that here in every path the variables should be followed in some particular order there cannot be be haphazard that here somewhere you have x1, x2, x3 somewhere you have x1, x3, x2 so they should follow some order. So, this order x1, x2, x3 is ok x1, x3 is ok but here this cannot be x1, x3, x2. So, this order is not correct this order is not correct. Binary decision tree so now here no conflicting variable assignment here and now here binary decision diagrams are easy to manipulate. So, now the question is how to minimize that. You know that there is a lot of redundancy in these binary decision tree. There are couple of nodes which are storing the same value like here if you look at the leaf node they are storing either 0 or 1 but there are total 8 number of nodes and they are storing only 2 values. So, if there are 2 nodes in that case you have to store these 2 values at again and again or in redundant fashion so you can reduce that. So, now one of the way is that you merge the equivalent leaf nodes. Leaves nodes are the nodes which are storing always 0 or 1 value. So, now here if you merge these 2 in that case you can say there is a significant reduction in the binary decision tree and now this become a binary decision diagram or binary decision graph. So, here it has 15 nodes and now you reduce that to 9 nodes. Again there are couple of nodes which have the same binary decision tree below that node. So, like here if you look at this node x and this node x here both have the similar kind of binary decision trees in both of the branches. So, now here there is no point to store these 2 nodes differently. So, what we can do is we can merge these 2 nodes. So, now what you need to do is you need to bring in this branch here. So, when you merge these 2 then here this node has no role to do and hence I can remove this node. So, now in this diagram if you look at these are the 2 nodes say x1 and this is x2. So, no this x3 these 3 nodes are evaluating in the same fashion in that case we call these nodes isomorphic nodes and you merge those isomorphic nodes. So, now here once you merge isomorphic nodes you can again reduce that. Now again look at whether there is a possibility to reduce it further or not. So, now if you look at there is still possibility to reduce this further. Now if you look at these 2 nodes when both of the edges are going to the same node what does that mean? That mean that irrespective of what is the value of x your function will evaluate in the same way. So, that means x does not have any role in decision making process hence why I need to have x in the diagram itself I can remove that x. So, now here you remove this x and then here you bring in these in edges to x to y and so now here in this diagram if you look at that now this x 3 to 0 here you have both of the edges going to that and from here x2 to 0 you have both of the edges going to that. So, now here you can you can see that you can minimize this binary decision diagram binary decision tree which initially had 15 nodes and 15 edges to like here 5 nodes and 5 edges. So, there is a significant reduction from this binary decision diagram to binary decision tree and this is known as reduced because here we applied all 3 reduction techniques. So, this is reduced diagram and we also decided the order of variable hence this is known as reduced decision diagram and reduced the order the binary decision diagram always represent the canonical form of a given Boolean function or a circuit and that is the the simplest form. So, the another thing is because here if you change the order of of variable in that case here the shape and size of the binary decision diagram will change, but still this will give you the same unique representation or for a given function or given circuit that will have the same shape and size for a given order of variable. If you look at there is some function like here if it is a constant then you will have only one node if it is variable in that case you will have this kind of nodes you will have this kind of say generate some circuit if it is something symmetrical function in that case here your binary decision diagram will also be symmetrical one. So, these are couple of examples if you have say circuit like here 4 input adder in that case here you have 4 and 4 8 inputs and then here output would be 4 bit some output and 1 bit carry outputs of 5 outputs. So, if you generate this diagram in that case here binary decision diagram will look like this one. So, say for 4 input it is has 31 nodes and if you go for 64 input in that case here the number of nodes you will have is 571. So, now here with respect to the input the growth is linear one. As I said that here shape and size depends on the order of variable. So, now here say this function here if I take the order of variable as a1 b1 a2 b2 a3 b3 in that case here this would be the binary reduce order binary decision diagram. If you use the a1 a2 a3 b1 b2 b3 as order in that case you can see the reduce order binary decision diagram would be much fatter and it will have more number of nodes and edges. So, now here see what you want when you want to generate a bdd that represents the canonical form. So, now and after that if you need to generate for one design and another design and you want to compare node by node edge by edges. So, now what you want is that the number of nodes and number of edges should be as small as possible. So, that it will take less time in comparison and it will take less space in order to store these nodes. So, now it is very important to find out a good order of variable and the finding out the good order of variable is an intractable problem and hence here we need to use couple of heuristics to find out the good order of variable. There are various heuristics those are like here static heuristic that you can apply on using the fan in of the gate statically or you can apply the dynamic ordering. So, I will discuss here dynamic ordering which is being often used in the practical circuit. So, one of the way is that dynamically. So, when you are generating the RO bdd what you need to do is you have to check the swap the adjacent variables. And check whether the RO bdd is getting reduced or not. So, that it can come out from the localized effect. So, you add delete or alter only the nodes which are labeled to the swapping. So, now here say I want to swap the variable A1 and B1 and B2 in that case here all the nodes which are labeled by B1 and B2 here they can be new nodes can be introduced or some nodes can be deleted. So, and now if there is a reduction in the size here we keep that order otherwise here we keep the previous order. So, now here by swapping these two here you can see difference in the RO bdds. If there is a reduction we keep the newer order otherwise we go back to the previous order. So, like here other techniques are like here shifting. So, there we which was proposed by Richard Ruddell from the synopsis. So, what it does is it periodically attempt to improve the ordering of the variables. So, now here this move each variable from the given location to all other locations and find out the best place of that variable best place is the place where it result into the reduced RO bdds. So, and this is though this is very time consuming but it is very effective technique. So, how it works say now this is my RO bdds now I want to find out the best place for variable b1. So, what I will do is I start to shifting this from b1 to b3 here this side and b1 to a1 this side and I will find out the place where it result into the smallest bdds and I will fix it there. So, this is greedy approach. So, I fix it there and then I will work with the other variables I would not change the order of this variable. So, now here if you move to the next location shift to the next location in that case here this would be the bdds then if you shift this to the third position b3 in that case here this would be the bdds then you go up you move to a3 then a2 then a1. So, now here when you go to a2 in that case here this would be the bdds and then if you go to a1 then this would be the bdds. So, now these two bdds are the smallest one. So, now you will fix the location or order of a2 at second loop position or at the first position and once it is fixed then it is frozen you are not allowed to change that. So, now here this way you can find out the order of variable. So, now here finding out optimal order of variable is very difficult that is NP complete problem, but now here for most of the functions you can find out the ROBDD in reasonable time and algorithm remains practical up to say 1 million nodes in ordered binary decision diagram. If you look at something like here how the functions are changing or sensitive to order of variable like here ALU it has very high sensitivity in the best case you will have with respect to increase in the variable there can be a linear increase or there can be a exponential increase in the shape in the size of a ROBDD whereas symmetrical functions are not sensitive at all means it does not matter what order of variable you are looking for multiplication though here the sensitivity is low but the growth is always exponential so with respect to increase in the number of inputs this is the story I taught you how to construct ROBDD so from a given truth table so now from the truth table I showed you that how you can construct the binary decision tree construct the RO and minimize that and get the ROBDD but the size of binary decision tree is much bigger than the truth table so that is impractical so this was just to illustrate you how to do that in practical we do not do like that in practice say this is circuit you know this is a NAND implementation of an XOR gate so in practice here we apply function on ROBDD ROBDD and then we generate the BDD by graphical manipulation or mathematical manipulation on these BDD so now here say the BDD of X1 we know this is one variable BDD of X2 we know this is another variable so we know the BDD of this now you want to have BDD at the output in that case you apply the NAND functionality on that and generate the BDD so now here just by graphical manipulation we obtain this one and then again you apply the graphical manipulation and finally you will get this BDD and now here dynamically we keep on applying the dynamic variable ordering and then we restrict the explosion of BDD to certain extent so now if you have BDD you can say if you have function or two designs you can generate BDD and then you can compare these two BDDs and if they are equivalent in that case you can say that both of the circuits are equivalent now in general and BDDs means we cannot handle BDDs more than a million nodes so now here if the circuit is much bigger what to do with that we cannot even store the BDD so now means what you need to do is you need to partition BDDs and now so that means for that you need to decompose your function into smaller pieces and generate the BDD for that and compare these BDDs at some internal points so now if this is your design say F this is another design F days you find out the internal equivalent points and then you have to generate BDD for all these internal points and compare that so like here these are the two functions one is F and G so now you decompose in sub functions F1, F2 and G1, G2 and now here you have to compare at the intermediate points F and no Z and Z and then you compare it at G and G so now here you have to define the cut points these are the structurally equivalent cut points and then you have to verify that this Z and Z are equal so that means here this F1 and G1 are equivalent and then here in terms of you generate the BDD of F2 in terms of Z and Y and here you also generate the BDD for G2 in terms of Z and Y and then compare that so this way you can verify the combinational logic now generally in reality we do not have combinational circuits we have sequential circuits so now how to verify sequential circuits that is the biggest challenge and one of the ways you have to formulate that sequential equivalence checking problem into combinational equivalence checking how I can do that say this is my sequential circuit that has some combinational part and some flip flop to store the state variable and then there are some input and some primary output this is primary output how I can convert this circuit into a equivalent combinational logic see here this circuit will behave differently in different cycles so now here if I can convert the entire circuit into its behavior in as a combinational logic so initially say the flip flop may have some value then this is I am getting some value from the flip flop this is primary input and this will behave and this will produce some output that goes to flip flop now next time this output generated by this one here it will go to the same combinational logic as it is this would be the output and then you will get new output and then again the output produced by this again it goes to the combinational logic and it will produce some output and will get some input from the primary input so now if I expand this for couple of time frame in that case here you can say that this is equivalent to the combinational circuit which is represented here for given number of time frames so now here this is equivalent functional equivalent of sequential circuit for given number of time frames so now if you expand this using the time frame expansion into combinational logic your combinational logic is replicated n times if you have expanded this n times and now the complexity of this combinational logic will be n times and number of inputs will also be increased by n times so now your combinational logic would be much bigger but still you can use the combinational equivalence checking for that now here the only the problem is the circuit is too large and now this can give you guarantee up to certain number of time frames it cannot give you guarantee infinitely long sequences other way to check the sequential logic is you have say generally you know we express sequential circuit or we can model sequential circuit using state diagram so say this might be the state diagram of a combinational sequential circuit so if you have state diagram of two machines now you want to if these two machines are equivalent in that case here they must have isomorphic state transition graph state transition graph is simply your finite state machine so now what you need to do is you have to check whether the two machines are isomorphic or not say you have one machine as this one another machine as this one m1 and m2 these are not isomorphic so means by looking at this you can say that these two machines are not isomorphic hence you can say that these two machines are not equivalent but that is not the case so what you can do is there are state minimization technique you must have studied that so now you can apply the state minimization technique you can reduce the state diagram into this machine and now if you look at the reduced machine m1 minimize machine m1 and machine m2 in that case now these two machines are isomorphic you can compare node by node edge by edge now the machines are isomorphic if you can generate another machine re-labeling the states so if I can re-label this state 1.2 so that because this is obtained by merger of these two states as one in that case both of the machines are absolutely equivalent and hence you can say these two machines are equivalent this is another way to prove that so what you need to do is you have to reduce the both of the state machines and then you check the isomorphism of reduced state machines of two designs so today we discussed about combinational equivalence checking and how we can use combinational equivalence checking for the sequential circuits as well couple of techniques we discussed like here timeframe expansion model as well as the isomorphism of two state machines and we have also seen that how we can use standard decision diagrams to see the to check the equivalence so with this I complete today's lecture here and we will discuss the remaining portion of equivalence checking and property checking or model checking in the next lecture thank you very much good day