 Hello and welcome to this presentation of the STM32-L4 System Configuration Controller. STM32WB devices feature a set of configuration registers. The system configuration controller gives access to the following features. Remapping memory areas to Cortex-M4 address zero, managing the external interrupt line connection to the GPIOs, certain robustness features, SRAM-2 write protection and erase, floating point unit interrupts, the configuration of the 20 milliamp high drive IOs used for I2C fast mode, plus peripheral interrupt masking per CPU, and finally the Cortex-M0 plus peripheral security. Pictured here is the four gigabyte linear address mapping of the STM32WB microcontroller. The flash memory is up to one megabyte in a single bank configuration. The SRAM total size is 256 kilobytes. It is split into three parts. SRAM-1 is 192 kilobytes, starting from address 0XX2000000000 and SRAM-2A backup RAM is 32 kilobytes, starting from address 0X1000000 and also aliased at address 0X20003000000, followed by SRAM-2B non-backup, which is also 32 bytes, starting from address 0X1000800000 and aliased at address 0X20003800. SRAM-1 is located in the usual ARM memory space for RAM on the S-Bus, while SRAM-2A and SRAM-2B can also be directly accessed through data code and instruction code buses allowing zero weight states used for code execution. The memory remap at Cortex-M4 address 0 allows the boost of the performance thanks to instruction and data bus access instead of using the system bus. The memory remap at address 0 is selected using the mem mode bits in the system configuration remap register. They allow the selection of either the main flash memory or the system flash memory, the SRAM-1 or the quad SPI. Here we have the STM32WB's bus matrix. The bus masters are shown on top and the Cortex-M4 core, the Cortex-M0 plus core and the two DMA controllers communicate with the bus slaves, shown on the right via the circled intersections. The flash memory is read through the accelerator. Cortex-M4 instructions are fetched through instruction bus and literal pools are read through the data bus. The SRAM-1 is accessed by default by the system bus and can be accessed through I-bus and D-bus when it is remapped at address 0 shown by the dark blue circles in order to increase performance. SRAM-2 is accessible through the I-bus and D-bus allowing zero weight state code execution and through the S-bus. The quad SPI can be read and executed through the system bus by default and can be remapped at zero to increase performance. The Cortex-M0 plus also reads the flash memory through the adaptive real-time accelerator or ART and has access to the SRAM-2A and 2B memories and the AHB-1, AHB-2 and AHB shared peripherals. The two DMAs can access all memories and peripherals. Different bus masters are able to access different memories and peripherals simultaneously via the bus matrix, enabling high-performance compute operations. Simultaneous master accesses to the same bus are handled via round-robin arbitration. There are three boot modes which are selected by the N-boot-0 option bit or by the boot-0 pin and an option bit named N-boot-1. When the boot-0 pin or option bit is at a low level, the STM32WB boots from the user flash memory, which is aliased at address zero. This is the standard method of booting the STM32WB. When the boot-0 pin or option bit is set at a high level, the N-boot-1 option bit determines the boot mode. In addition to the N-boot-1 option bit, boot mode is selected either by the boot-0 pin or the N-boot-0 option bit depending on the value of the NSW-boot-0 option bit in the flash OPTR register as shown in this table. A flash empty check mechanism is implemented to force the boot from the system flash memory instead of the main flash memory if the first flash memory location is not programmed. The default level for the option bits is high, enabling the boot from the system memory portion of the flash memory. The other option is booting from the SRAM-1 memory region which may be used for debugging purposes. The on-chip bootloader allows the user to program the flash memory through a serial communications peripheral. The supported protocols are USART, USB, CAN, SPI, and I2C. The 64 kilobytes of SRAM-2 are particularly suitable for performance, integrity and safety, and low power. The SRAM-2 is accessed through the data and instruction buses without any remapping, which enables code execution at zero weight states and also through the S-Bus allowing RAM address continuity between SRAM-1 and SRAM-2 memories. The SRAM-2 supports parity check. The data bus width is 36 bits because four bits are available for parity check, one bit per byte. In order to increase memory robustness as required, for instance, by Class B or SIL standards. Class B and SIL are safety standards. Class B is for home appliances and SIL for the safety integrity level. The parity bits are computed and stored when writing into the SRAM. Then they are automatically checked when reading. If one bit fails, a non-mascable interrupt or NMI is generated. The same error can also be linked to the break input of the timers. The 32 kilobyte SRAM-A content can optionally be retained in standby mode. The SRAM-2 is also suitable for secure applications. The SRAM-2 can be write protected with a 1 kilobyte granularity. The SRAM-2 can also be read out protected via the RDP option byte. When protected, the SRAM-2 cannot be read or written by the JTAG or serial wire debug port and when the boot in system flash or boot in SRAM is selected. The SRAM-2 is erased when the read out protection is changed from level 1 to level 0. Please refer to the system memory protections training for further details. The SRAM-2 can be erased by software by setting the SRAM-2 ER bit in the SRAM-2 system configuration control and status register. The SRAM-2 can also be erased with the system reset depending on the option bit SRAM-2 RST in the user option bytes. Two SRAM-2 areas, one in SRAM-2A and one in SRAM-2B can be made secure via user option bytes only giving exclusive Cortex-M0 plus access to the Cortex-M0 plus core in these areas. The system configuration register 2 contains the control and status bits linked to safety and robustness such as the SRAM-2 parity error flag and the control bits to direct some error detection events to the timer's break inputs. This allows timer outputs to be placed in a known state during an application crash. Once programmed, the connection is locked until the next system reset. These internal events include a flash error code correction event, a power voltage detector event, SRAM-2 parity error event, and the Cortex-M4 hard fault. The system configuration controller manages the selection of the GPIO to the external interrupt or event signal which is used as a synchronous external interrupt or event with wake up from stop capability. It also allows the selected GPIO pin to be used as an internal interconnect trigger signal to the ADC. Configuration register 1 contains the floating point unit interrupt control bits. It also contains the I2C fast mode plus 20 milliamp drive enable control bits. Four IOs can be configured with high drive mode even if they are not used as I2C alternate functions. They can be used to drive LEDs, for instance. The IO analog switch voltage booster is also selected here. Peripheral interrupts sharing the same NVIC vector have a mask to prevent them from interrupting both CPUs. The AES accelerator 1, the AES accelerator 2, the public key accelerator, and the true random number generator peripherals can dynamically be made secure by the Cortex-M0 plus firmware through secure register bits in the system configuration block, enabling access to the secure part of the internal SRAM or flash memories. In addition to this training, you can refer to the reset and clock control, power controller, interrupts, flash and system memory protections, timers, I2C, encryption, public key, and true random number generator trainings. For more details, please refer to application notes AN2606, STM32 microcontroller system memory boot mode, and AN4435, guidelines for obtaining ULCSA IEC 6335 class B certification in any STM32 application.