 So, welcome to this lecture on in the course digital system design with PLDs and FPGA. Around last 42 lectures I have covered the digital design, the PLDs, FPGAs and VHDL to a great extent what is required for synthesis okay. Today we are going to discuss a reasonably complex case study okay what we can discuss in a classroom because we have limitation on the slide what we the diagram we can show on the slide and all that. But this case study captures in a nutshell everything that requires for a complex project is not that it is not useful if you thoroughly understand the process which will bring together almost all the aspects we have discussed. Now some will be evident when we put this when we use a tool which will be the next lecture I will show as I said I will kind of decouple the tool completely towards the end part so that that can the because the tools change and I do not want that to come into any of the kind of lectures which deal with the concept okay. So it will be completed the FPGA part, the VHDL part all that will be completed when we discuss the case study today I will show you the design how to go about designing it and outright the VHDL code also. Everything is that maybe when we implement that using the tool some of the FPGA related how much of the FPGA is used what is how the FPGA slices are wired up or something like that which we can see inside the device when we use the tool. So today we are going to discuss a case study which is nothing but a very simple 8 bit multiplier okay but I will go to every bit of detail with regard to the case study that we apply what all we have learnt what all possible can be crammed into this case study it is done. So let us look at this particular design example okay. So let us move on to the multiplier so we are trying to implement an unsigned integer multiplier this can be changed into a signed multiplier by you know one easy way of doing that is by doing the boot encoding you know radix for boot encoding you can do and if I mean you can build on this particular case study say you can do a radix for boot encoder which will support the sign multiplication you can modify this to do the division restoring division non-restoring division and so on you know lot of things can be done as an extension of this case study okay. But let us start with the algorithm and the naive way of implementing it then whether we can optimise it and so on okay. So and for the sake of clarity I am showing a 4 bit multiplication but the real design we are going to do an 8 bit multiplication okay. So we have a multiplicand which is 4 bit, multiplier 4 bit okay and you know how the multiplication is done on a paper. So what we do is that we take the least significant bit of the multiplier if it is 1 we form a partial product that is in the 2 raise to 0 kind of place okay. Then the 2 raise to 1 position the multiplier between look it is 0 so we write the partial product corresponding partial product that is nothing but the multiplicand kind of and at mass by this bit okay. So that is all 0 0 and that has to be shifted to the left because it is 2 raise to 1 position then 2 raise to 2 position partial product is written like that 2 raise to 3 is written like that okay. Then we add all the partial product together to get the product okay. So that is the algorithm and like this is a pencil paper method and that is the basic algorithm there is no difference it is the basic algorithm is same. So in this case if you try to implement this as it is written in the paper then we will need a register to store a multiplicand register to store a multiplier then we need a say 8 bit in this case a result register and we need to add all these and you know that these 2 partial products can be added using an adder then that result and this can be added with another adder and ultimately one more adder. So it requires 3 adders to do this parallely okay. So and in the case of 8 bit multiply multiplier algorithm we need in a paper pencil method we need 7 adders okay and that is a very costly operation to have a 7 adder. So you can imagine about 16 bit multiplication that will require 15 adders each that will be 15 bit okay or even a kind of extended because it need to be more than you know because here you see there it is shifted so instead of that there are 5 bit and then you need a 5 bit adder and so on okay. So we do not want to waste adders so we will try to use a single adder okay. So the idea is that we use this as an accumulator so make at the beginning everything 0 okay. So then what you do is that first partial product is added here the second partial product is added shift and so on okay. Now there is a better method of doing it okay instead of shifting the partial product to the left we can shift the accumulator to the right okay. So the idea is that make the accumulator 0 at the beginning then take the first partial product add it at the MSP part here and after adding we just shift it okay by 1 bit okay. Because then this part is shifted okay like that. Now the second partial product is added at the MSP because we right shift the accumulator that the left shift is it is equal to left shifting the partial product. So we add it here because it is convenient because we can add it at the same place every time okay and then you shift by 1 and so on okay. So the next partial bit partial product you add it here shift then this one you add it here shift okay then you get an 8 bit result okay. Now another optimisation this is not that is very kind of important but this add to little bit complexity and which is nice okay. So what we can do is that at the beginning this part is not used at all okay. So first time you add a partial product here and shift by 1 bit then this bit is occupied. The next time you add and shift 2 bits are occupied. So what we can do is that we need not waste another register for multiple at the beginning we can make this part 0 and store the multiplier here okay. Then look at the least significant bit of the result to check the current multiplier bit to check. If it is 1 add the multiplicand here then you shift so that bit is gone now that bit is no more required 0 comes here. So you look at this bit current bit if it is 0 then what we do is that we can add 0 here but there is another way of doing it. So we take this part just pump it back to this register okay so just put it back and shift okay. So instead of adding 0 we can just recirculate the MSP back to here and put it okay. Our idea is that everything goes on in the iteration we do not want anything to be stopped like when you start iterating you add either the multiplicand here or you recirculate the most significant byte. So that it is done say in this case 4 times okay in an 8 bit we have to do that 8 times okay. So by storing the multiplier we get an advantage that we do not need an additional storage and also we do not need to kind of look you know kind of you know move to find the current bit you know since it is getting shifted we need to look at the result 0th bit of result to find what is the current bit of the multiplier okay. So that is one major change we are going to do we are going to use a single adder we use an accumulator and we are going to add the partial product at the most significant bits half of the bits here and shift it right okay. And we are not going to add 0 whenever we want to add 0 we just take this part and put it back okay. So instead of adding 0 so that is when you add 0 the result is same so we take it and put it back okay that is the second kind of variation. Now there is another variation what we are going to do is that there is no point in adding this bit here because to add we need this part to the adder and this multiplicand to the adder you add together. But then there is no point in the result of the adder to be loaded back here and then shift it is a waste of time because to load we need a clock and to shift we need another clock okay. So it is a 2 clock per iteration so what we do is that we give this the highest bits to the adder multiplicand to the adder then we add together. And when we load we load it shifted okay by one bit because if you add 2, 4 bits you get a 5 bit and that 5th bit comes here, 4th here, 3rd here, 2nd here and the 1st bit here and everything gets shifted okay. So I hope you get the algorithm now we use an iterative multiplier okay that means we one by one iteratively we accumulate the partial product and we store the multiplier in the least significant bits and we add the multiplier, multiplicand along with this you know this partial product at this place and shift and we do not load and shift we will you know we will load shifted okay. So that we do everything in a single clock cycle okay so that is the algorithm the modified algorithm so we need now a multiplicand register in the case of 8 bit, 8 bit register we need an 8 bit adder okay which gives a 9 bit result then we need a 16 bit register okay. So that much is required and now to recirculate we need a MUX okay because we either have to choose the adder output or the current the most significant bits back. So we need a multiplexer and there are 2 other things which is required which is not maybe obvious okay I told you that this process of the loop has to be done in the case of 4 bit 4 times okay. And in an 8 bit multiplier you have to do this process of you know adding or recirculating 8 times. So we need to keep track of the iteration and so we need a counter which count from 0 to 7 okay. So that we get to know that when to stop okay. So a counter is required in addition to this data path elements okay. Data path elements are the multiplicand register result register which contains a multiplier register I know multiplier and adder now we need a counter to keep track of the iteration much more important. So we talked about the data path but we need a controller to control the data path okay maybe there is a start signal from the external world and that will start the whole operation. And when it is done it will indicate that it is done that can be sampled by a processor or it can be an interrupt to the processor or interrupt to the rest of the circuit whatever it is also we need a controller okay. So I hope you are clear the basic of multiplication the algorithm the modification to algorithm the elements what are the resources in terms of sequential elements and the combinational circuit what we require all that is clear to you. So let us move on and so this is what we have discussed we are our algorithm is shift and add. So basic algorithm is shifting the partial product to the left but we shift the accumulator to the right. We need 8 partial products but and not 7 adders we are going to use an accumulator and single adder with shifting the accumulator right. And in the result the least significant byte we are going to store the multiplier and we are not going to load the adder output into the accumulator in one clock cycle and shift in another clock cycle. We are going to do that in a single clock cycle okay just one clock cycle. Now if the multiplier bit is 0 we will as I said we are not going to add 0 but we recirculate the result with the shift okay. So that is the algorithm now the resources required is that we need a multiplicand register 8 bit because we are going to implement the 8 bit multiplier. We need a result register which is 16 bit least significant byte of that is multiplier. Then we need a 9 bit adder because we add 2 8 bits and produce a 9 bit. We need a 9 bit 2 to 1 multiplexer to select the adder output or the most significant byte of the result to recirculate. We need a bit counter which counts from 0 to 7 so we require 3 bit counter to keep track of the iteration. We need a controller which controls the whole data path operation okay. So it is quite detail I am writing it down so maybe when you design it is better to write the resources required so that there is absolutely no lack of clarity when you get to the data path and the controller design okay. So let us look at the data path at the beginning in a little abstract way at the top level okay. The top level is simple block with a multiplier like a multiplicand multiplier and result and some control start with that. But I am going to show you the next level level 1 partition of the data path okay not the controller data path. So this is the whole thing which is represented from a top to bottom data flow. So look at this part this is the multiplicand register it gets an input mc7 down to 0 multiplicand is mc that is only to hold the value like at the beginning of the iteration we load the value here. Then the output of this register is used for multiplication so the output is called md which is 7 down to 0. Now you look at the condo signal a power on reset called rst comes to it because at the power on this register is reset and once it is reset it is enough because every time a multiplication happens we are loading a new value it need not be reset every time at the power on we need to reset so that it does not get into metastability at the power on. Then we need a clock and we have seen how the controller can control with the clock not touched okay we have seen that the controller, condo signal will come directly to the data path to enable some marks and all that okay. Now the condo signal which it requires is called load because when the controller say load the input value it will load this mc7 down to 0 to md7 down to 0 okay. So only one condo signal load and we will take this and expand in the subsequent slide okay. Now let us look at the result register which is a 16 bit register which is r15 down to 0 the higher product register is a accumulator so it has a clock now it has a reset now mind you this is not the power on reset this I am calling a p reset or peripheral reset whatever and that comes from the controller okay. So that is a signal which is output of the controller because every new value you load to the multiplicand and multiplier this has to be cleared for multiple this has to be made 0. So the controller will clear at the beginning of the multiplication this particular register okay. Now we know that this has to be loaded with the adder output or the recirculating and that need a shift signal it can be called load also because we are just loading the value shifted but since the same condo signal is used for shifting this register we just use the word shift okay. So the same condo signal when it is active it gets loaded the shifted value gets loaded here whatever is you know the value s0 along with this is shifted and loaded okay. So in one clock cycle everything happens in one clock cycle but this if you look at the least significant byte of this register we know that at the beginning the multiplier is loaded here okay. So it need a load signal which will load this ml7 down to 0 to r7 down to 0 okay. Now we are going to look at the r0 to add the accumulator more significant byte with the multiplicand or to recirculate this part back here okay. Now this is the 8 bit 9 bit adder which add the most significant byte of this accumulator which is r15 down to 8 with the multiplicand and you get a 9 bit and this MUX depending on this bit is 1 or 0 will select if it is 1 it will select the adder output you see that it is a 9 bit output and the adder output is called su8 down to 0 the multiplier output is called s8 down to 0. Now you see 8 to 1 is loaded here which is already shifted okay because it is not that we are loading s7 here and shifting with s8 we are loading s8 to r15, s1 to r8 and s0 to r7 and whatever was there in r7 will be loaded back to r6, r6 will be loaded back to r5 and r0 will just go out okay. So when whatever we do either we whether it is adder output or recirculator output it is shifted okay in the clock cycle and if the r0 is 0 then you see this r15 8 which is shifted version is getting loaded here you know it is shifted with a 0 at the most significant bit because every operation we need a shifting and that is what this is representing and s0 goes down here. So it does not matter as far as iteration is concerned this way or this way. So initially we load the algorithm is like that when the start signal come controller will give this load signal and the multiplicand and multiplier get loaded and now the controller will look at the r0, r0 it goes to the controller. So if r0 is 1 the controller will give this select line as 1 then this gets added it gets load and if it is 0 this gets recirculated and controller will do that 8 times okay. So we need a counter the output of which will go to the controller okay and the controller will look at the r0 and you know select this line. Similarly the load signal is given by the controller both all the 3 load signal all the 2 and all the 2 shift signal is given by the controller, select signal is given by the controller and this PRST is given by the controller okay. This reset is a power on reset at the beginning now you see that I have put some red line dotted line on some signal what I do is that I am indicating that these are the external signal okay. So these are the ports clock reset MC ML which is coming from outside and R15 and R8 are the results okay. So why I am putting a dotted line is that when you write the VHDL code we can declare all the red line the cross line signal as port and rest of them as internal signal. So looking at the picture I will say entity multiplier I say port clock reset is in standard logic then select is like select is a signal so the R15 down to 0 is a out standard logic vector 15 down to 0 and so on okay. So and MC is standard logic vector 7 down to 0. So it is very easy and rest all signal I can declare as signals okay internal signal that is why I put this dotted line. So what we are going to do is that we are going to complete the data path it is not complete it we need a counter so the counter you know that has to keep track of the iteration. So the counter can use shift as an enable okay. So when the shift is one counter will increment otherwise counter will not increment okay and this reset the P reset when the accumulator is made 0 the counter also need to be reset because every iteration new data value the counter need to be reset okay. So we give the counter reset not the power on reset if you do the power on reset it may not be right. So we use the P reset for the counter so let us see the counter block diagram. So the counter as I am showing it as a single block we will expand it later okay we will see the level 2 diagram of the counter which gets clock which is an external signal. P reset which is coming from the controller shift which is enable whenever the shift is 1 it will count increment okay. So when shift is 1 it will increment so that is given by the controller and it is a 3 bit counter but now the controller should know when it has reached 7. So it is a decoder which is equal to 7 okay it is an an with 111 okay like Q2 is 1 Q1 is 1 Q0 is 1 this signal is high and the controller knows and this goes as input to the controller okay and controller knows then it has to stop the iteration okay. So what comes out of the controller is the select line the load line the P reset line and the shift line okay and R0 goes as an input to the controller then depending on that it will generate the select line and also this max from the decoded value of the counter goes as an input to the controller okay. Now we can draw the controller block diagram so let us put the controller which anyway get the clock and reset, reset is required because that has to come to the first initial state and clock is the one being the controller being synchronous we need the clock and R0 is the least significant bit of the result which is also the current bit of the multiplier okay that is why it is taken into the controller. The max signal is decoded value of the counter that will tell the controller to stop or business and the start is an external signal which is coming to the controller which say start the multiplication now okay. So the external world is giving the multiplicand and the multiplier and it will give a start signal and then the controller will start loading multiplying and all that and all these are the control signal P reset which goes to the counter and the accumulator load which is going to multiplicand and multiplier shift is going to the multiplier and the accumulator select is to select the max to choose the adder output or the recirculating output and the done is to indicate that the multiplication is complete okay. So that is what is the data path and the controller okay. So looking so we started with the algorithm okay and we modified the algorithm optimise the algorithm we found what are the resources required then we started with the data path registers and adders and multiplexers and as I said these block need further expansion okay we will do that and a counter is required to keep track of the iteration and a controller which control the data path and the counter or counter we can think of it as a part of the data path. Now what we are going to do is that we are going to expand it we are going to take this register expand it this one we will expand this one we will expand and this one this counter we will expand and then that is it and then what we do is that we will write the state diagram for this controller okay because we are clear in algorithm now we have told the algorithm clearly I have not written it down but then with that description we will go to the state machine okay. So let us take the multiplicand register that is this register what is required is that when the load signal comes upon the clock this gets loaded and then it is remembered it is recirculated. So that is what is shown here we have an 8 bit register which get the power on reset and the clock upon the reset this is made 0 when the load signal from this the controller comes the input multiplicand mc goes to md and if it is 0 this multiplicand is recirculated okay I am not showing a path like that but that you imagine there is a connection like that okay. Once again upon the reset multiplicand is made 0 the output is made 0 upon the clock if load is 1 the input gets loaded otherwise it gets remembered okay. So how do we write the VHDL code so we write a process clock, reset both are like reset is asynchronous so we put it in the sensitivity list begin if reset is 1 then this output md is other 0 because it is 8 bit else if clock event clock is equal to 1 if load is 1 then md get mc and if means else it is recirculated okay. So that is how the code for this is written very simple you know if you do this approach everything is simple and when you synthesize you will get what you have written okay there is no need to complicate so let us pick up this particular register now high product register it is almost same you see here what we are going to do p reset is 1 this is made 0 if upon the clock if shift is 1 what is done is that s81 gets loaded here that is otherwise it will recirculate okay so very simple so we have the higher product register okay or the accumulator part and the p reset is a reset which will reset r15 down to 8 to 0 upon the clock if shift is 1 that multiplexer output s81 get loaded into r15 8 if not that is recirculated it is remember okay so that only when this shift signal come this will get kind of you know loaded okay and that is the VHDL code for it if p reset is 1 then r15 down to 8 is other 0 else if clock event clock is equal to 1 and if shift is 1 then r15 down to 8 gets s81 down to 1 okay so r15 down to 8 gets s8 down to 1 and if that means if it is shift is not 1 shift is 0 this is recirculated okay so see how simple is the coding it is very straightforward if you draw the diagram after some practice maybe you do not need to do this you can kind of imagine in your head like you know that what is that this is that register and you can write the code. But at the beginning I suggest that you go through this little bit tedious process so that everything is clear even if you are an expert drawing such a block diagram will help a lot there will be less errors it will be much more optimised than arbitrarily writing the code okay. So let us pick up this particular register which is the most complex register we have so it has 2 condo signal so upon the reset r7 down to 0 is 0 now the load as priority load is 1 then r7 down to 0 gets ml7 down to 0 if not else if shift is 1 s0 get into msp r7 get into 6 bit r6 get into 5th bit and so on okay so it gets right shifted okay so that is what is we are going to see the detailed block diagram. So that is shown here so there are 2 control signal with load as a priority so you see 2 muxes so upon the reset r7 down to 0 is 0 if not upon the clock when the load is 1 which has priority the multiplier input gets to the multiplier output okay and if not if load is 0 then if shift is 1 okay then you see that s0 is a most significant byte bit r7 is a next and up to 1 and r0 goes off okay if not the r7 gets you know recirculated okay so that is the multiplier register or the lower product term the detailed block diagram. Now let us look at the VHDL code we write a process the clock and reset in the sensitivity list if reset is 1 then this is 0 r7 down to 1 assign other 0 else if clock even clock is equal to 1 load is 1 r7 down to 0 is ml okay which is 7 down to 0 else if shift is 1 then r7 down to 0 is s0 and r7 down to 1 and end if okay so that means if not then it is recirculated okay end if end if end process. So very simple now the code the way the code is returned same as in all the register only the control signal comes in the proper priority and these diagrams definitely help it brings in clarity and if you write a code like this from the block diagram when you synthesize you will get this back you know exactly similar and we need at the last the counter we have to show the detailed view of the counter so that is where we are coming. So if the counter is that it is a 3 bit counter 3 flip flops p reset because it need to be reset at the beginning of an iteration and the clock and you see when the shift is 0 then the count is recirculated when the shift is 1 the count is incremented and loaded okay. So that is what we need when the shift is 1 counter gets incremented so the code is if p reset process clock and p reset p reset is 1 count is other 0 else if clock even clock is equal to 1 if shift is 1 then count is count plus 1 end if okay if shift is 1 then the count is count plus 1 otherwise it recirculates okay. So that is how what the detailed block diagram of the various elements of the data path now what is remaining to be seen is state machine okay so we know the controller or the state machine as this view the state flip flops next side logic which is looking at the present state and inputs and output logic and I have shown earlier the picture of the controller which gets clock and reset start r0 and max are the inputs and prst load shift select done are the outputs okay. So that is what we are going to see now we are going to see the state diagram okay because by from the state diagram we can arrive at the next side logic and output logic we have seen that but when we write the code we just write the code for the state machine and the synthesis tool will find the equation for the next side logic and output logic okay. And we have you know that the more output when the output is a function of the present state milli output when the output is a function of the present state and the input and we have said we can have a 2 block view where the output logic and the next side logic gets the inputs similar inputs so we can combine these 2 blocks called logic and take the output from here okay. So that is a 2 block view you have the logic which is comprising of the next side logic and output logic which gives the next side and output. So we are going to use this view we are going to code the next side logic and output together okay it is very convenient because looking at the state diagram we can write the VHDL code in that case. So we will use this block for implementing the state machine or the controller okay. So this is the state diagram of the algorithm we have discussed. Look at the state diagram at the power on we come to a starting state okay now at this point the state machine is waiting for the start signal to come from external world and maybe it is a processor which is giving the signal as long as the start is low remain in the state and we have to initialize all the signal properly. Normally the reset is 1 because the counter is reset the accumulator is reset all the control signals take the inactive value. So the select can be 1 or 0 it does not matter but the shift load all that are control signal that has to be 0 the done is 0 because we have not done yet okay. So when the start comes from the external world we assume that the multiplicand and multiplier input is given. So what we do is when the start comes we keep the reset high because we do not want the counter to start now because still we are not start at the iteration. So reset is 1 and the load is 1 okay there is no issue even if the reset is removed because the counter is controlled by the shift. Unless shift is 1 counter would not be incrementing but it is okay to have the reset 1 the load is made 1. So you know that at this state this S1 state the multiplicand and the multiplier will get loaded upon the clock into the multiplicand register and the result register. Now we can start the multiply multiplication process we come to this state and we make shift as 1. So now you can see many things happening so what happens is that the counter will start counting and this select line at each bit will reflect the current value of R0. So either this will happen or this will happen like that you know depending on like maybe this is 3 times this is 1 time whatever depending on the bit pattern that will happen. So that is this place but the state machine has to make the shift 1 so that the registers are loaded properly this particular register and this register gets loaded the counter gets incremented and all that. So the shift is made 1 and the select line has to be chosen properly it is 1 if this bit is 1 then you have to choose this path 0 this path. So the select line is nothing but the R0 okay and the done bit is 0 okay we have not done it and this state has to continue till the counter decoded value is 7 okay when the 7 comes next clock cycle it can exit because we have done 8 iteration the counter started with 0. So in the next clock cycle it is incremented to 1 so when we reach 8 it is the 8 iteration at the end of it it can get out of that state so that is as long as the max is low remain here if the max is high come to this state now we should make the load 0 shift 0 the select does not matter but we will say the result is there already because all the iteration has finished and the done is made 1 this can be sampled by the rest of the circuit or by a processor. Now what we are going to do is that as long as the start is low remain here the new start comes and we assume start is a small pulse because if start is very of long duration when it comes even if it completes still the start may be high and we start again okay. So we assume that start is a pulse okay so that is the state diagram at the beginning as I said reset upon the start come to a state load values then you start the iteration by making shift is 1 select is r0 wait for max signal when the max signal comes make everything inactive and make the done by 1 okay. So in like as far as the design is concerned we have completed the design because this can be coded directly in VHDL we have done the data path design at the level 1 showing all the blocks we have taken each block and implemented that in a detail and we have seen the corresponding VHDL code we have the algorithm at the beginning and we have come out with a state diagram for to implement that algorithm. So now by writing the VHDL code we can get everything together so we are now going to look at the VHDL code for this particular multiplier okay. So let us move to that so here this is a VHDL code we have the library declaration standard logic 1164 where the standard logic is defined standard logic unsigned because somewhere we are going to use plus 1 for the counter as I said wherever there is dash okay and red dotted line we declare it as the port. So clock reset start is in standard logic done is out standard logic MCML is 8 bit vector product is 16 bit vector okay. Now we can declare all the other signals you know as with appropriate width which is shown here as internal signal okay. So we need since we have a state machine which is consisting of 4 states we need a state type declaration so that is shown here type state type is S0, S1, S2, S3 signal present state next state is of this type and I have mentioned this in the lecture where we discuss the VHDL coding of the state machine. So the most tools allow you to kind of define an enumerated state and declare the present state and the next state using that and that will be treated as a standard logic vector and all the other signal like P reset, max, load, select, shift all that are standard logic the output of the registers they are of appropriate width the MD is 8 bit multiplicand, SU is output of the adder 9 bit, S is output of the multiplexer 9 bit, count is 3 bit counter, R is the real result which will be assigned to this particular product because we are going to recirculate R. So if you use product it cannot be recirculated because being an output it cannot come on the right hand side of the assignment that is why we use another signal called R and now you see at the begin what we do is somewhere we assign R to the product okay. Now I am showing all the VHDL code the multiplicand register we have discussed this so I give a label process clock reset then begin if reset is 1, MD is other 0 else if clock 1, clock is equal to 1 if load is 1 MD gets MC there is only 1 control signal which is load. Now this is the multiplier come lower product register which has 2 control signal load and shift so process clock and reset if reset is 1 R7 down to 0 is other 0 so we are talking about this okay and if load is 1 R7 down to 0 get the multiplier input if shift is 1 R7 down to 0 get S0 and the shifted version of R7 down to 0 that is R7 down to 1. So we are talking about this load is 1 this gets in here if shift is 1 then S0 with R7 down to 1 which is a shifted version gets loaded here so that is a code which is showing this. The next is a multiplexer because this we need a multiplexer which is nothing but if select is 1 this S8 down to 0 is SU8 down to 0 else it is 0 and R15 down to 8. So that is that S8 down to 0 is 0 and R15 down to 8 when select is 0 else it is SU8 down to 0 so that is exactly one concurrence statement. So it is very simple and higher product register so we are talking about this so if shift is 1 this gets loaded that is all. So that is if p reset and clock in the sensitivity list if p reset is 1 R15 down to 8 is 0 else if clock even clock is equal to 1 if shift is 1 R15 down to 8 is S8 down to 1 okay. Now so that is the completion of the higher product register as I said the R is the internal signal which is assigned to the external product and we have the counter which we discussed before process clock p reset if p reset is 1 then count is other 0 else if clock even clock is equal to 1 if shift is 1 count is count plus 1 end if that means otherwise it re-circulate. We need a decoder so which is a concurrence statement we do not need to write it internally and confused if you write it in the wrong place it will get a flip flop like if you write this statement within this else if clock even clock is equal to 1 there will be a flip flop coming there and it will add 1 bit latency and it can create timing issue unless you address it. So we write it as a concurrence statement max is 1 when count is 7 else 0 okay so it just indicates when the counter reaches 7 okay. Now this is the adder a particular adder we use a plus operator so this adder we are using a plus operator to have optimized implementation in the FPGA we have discussed if we use plus we will implement using the lookup table and the carry chain so 0 because a 9 bit adder 0 upended with AMD plus 0 upended with R15 down to 8 so that we get the 9 bit result okay. Now what we are going to do is that we are going to implement this state diagram and we are going to combine the next state logic and output logic together okay. So idea is that we keep this in front and write the VHDL code for the next state logic and output logic so it is very simple straightforward I hope you remember this we will go to the logic part of it. So a process the present state is input to the process all the inputs also like you have start r0 max these are the input to the state machine so that has to be in the sensitivity list then we say case present state is when s0 like in the state s0 because all the outputs are more outputs so we just write the output p reset is 1 rest all are 0 then we write the transition if start is 1 then the next state is s1 else you remain there okay. So that is it start is 1 then go here else you remain there and this is the value which is written here so when it come to when s1 like reset is 1 load is 1 and there is no condition no unconditionally it is transiting to the next state so the next state is s2 in the s2 you see the shift is 1 select is r0 but as long as max is 1 go to the next state s3 else remain there you know so that is what is shown here. If the max is 1 go here else remain there okay. Now the last state so when s3 the done is 1 rest all is 0 and if start is 1 then go to the next state s1 else next state s3 okay. Now I have made a slight modification the diagram shows that it goes to s0 but the problem with s0 is that maybe okay like it is kind of repeated so you do not need to go to this state you can come here because the reset is made 1 here so we can say 1 clock cycle so just if the start is 1 you can come straight away here okay. Now we need to specify the flip-flop registers this particular register which is nothing but upon the reset the present state is made the first state otherwise upon the clock the present state get the next state okay. So that is what is written here so the flip-flop process reset clock begin if reset is 1 present state is s0 starting state else if clock event clock is equal to 1 present state get next state end if end process end the architecture. So the complete design is over only thing is that maybe you can like we have shown say take these 2 registers you see that it is working with the same clock working with the same reset if you want to combine them into a single process you can do that okay. So I have shown that say like we have a single process with clock and pre reset if pre reset is 1 r15 down to 80 is 0 count is 0 else if clock event clock is equal to 1 if shift is 1 r15 down to 80 is s8 down to 1 and you can maybe include the count also here count is count plus 1 end if or you can write a separate if shift is 1 for counter but this can be combined similarly you look at this particular code like the multiplicand register and the multiplier register can be combined but when you combine we cannot see here it uses only a single load signal here it is load and shift is there so we cannot combine in the same if statement there has to be separate if statement if you combine that so that is what is shown here upon the reset r15 down to 80 count is 0 no this is earlier 1. So this is the multiplicand and multiplier upon the reset multiplicand is 0 result is r7 down to 0 is 0 then we write the multiplicand register with 1 if and multiplier come lower product with register with another if ok. So it is a little bit concise way of coding it but you should not mix up this process with this process because the reset is different so you should not mix it so that is how the VHDL code is written. So I will in the next lecture I will show this in a board with the tool and all that but what we have done today is looking at a multiplier case study we have looked at the algorithm we have optimised the algorithm we have found the resources we have from the algorithm we have put down the data path at the top level block diagram partition then one by one we have taken each piece design in detail you know up to a register and multiplexer we have written the VHDL code from the controller algorithm we have developed the state diagram then from the state diagram and these second level blocks we have written the VHDL code you know for the data path and for the controller. Now the implementation is over you know I am very like if you write with this much detail nothing can go wrong you know very very minute mistakes will be there in one short the design will work there will be only minor errors if you do the design like this. So I suggest that you go through this process do not skip anything as far as possible write things down in detail and try to write the VHDL code so in the next lecture which I am kind of concluding I will show you the tool with some simple combinational exercise sequential exercise and this case study on a with the tool on a particular board FPGA board so that you get a complete picture of the course. So I suggest you try some variation of this design as I said divider or the radix for booth encoder multiplier and all that which will enhance your learning so you can try that exercises so please revise I wish you all the best and thank you.