 Hello, and welcome to this presentation of the STM32 General Purpose I.O. interface. It covers the general purpose input and output interface and how it allows connectivity to the environment around the STM32 MP1 series. The general purpose I.O. pins of STM32 products provide an interface with the external environment. This configurable interface is used by the MCU as well as other embedded peripherals to interface with both digital and analog signals. Application benefits include a wide range of supported I.O. supply voltages as well as the ability to externally wake up the MCU from low power modes. The general purpose I.O. ports provide bi-directional operation according to the input memory map. I.O. ports are directly connected to the AHB bugs. This allows fast I.O. pin operations, such as toggling and output, with an independent configuration for each I.O. pin. They are shared across 12 ports, named GPIO-A to GPIO-K, plus GPIO-Z, each of them hosting up to 16 I.O. pins. I.O. ports support atomic bit set and reset operations through the BSSRR and BRR registers. It allows I.O. toggling every two clock cycles. Most of the I.O. pins are 5 volt tolerant when supplied from VDD above 1.8 volts. General purpose I.O. pins can be configured for use in several operating modes. An I.O. pin can be configured in an input mode with floating input, input mode with an internal pull-up or pull-down resistor, or as an analog input. An I.O. pin can also be configured in an output mode with a push-pull output or an open-drain output with an internal pull-up or pull-down resistor. For each I.O. pin, the slew rate speed can be selected from four ranges for the best compromise between maximum speed and emissions from the I.O. switching and to adjust the application's EMI performance. I.O. pins are also used by other embedded peripherals to interface with the external environment. Alternate function registers are used to select the configuration for the peripherals in this case. The configuration of the I.O. ports can be locked to increase robustness of the application. Once the configuration is locked by applying the correct write sequence to the lock register, the I.O. pins configuration cannot be modified until the next reset. Several integrated peripherals such as the USART, TIMERS, SPI, and others share the same I.O. pins in order to interface with the external environment. Peripherals are configured through an alternate function multiplexer, which ensures that only one peripheral is connected to an I.O. pin at a single time. Of course, this selection can be changed while the application is running through the GPIOX, AFRL, and AFRH registers. During and after reset, the alternate functions are not active. When the external oscillator is switched off, pins related to this oscillator can be used as standard I.O. pins. This is the default state after device reset. When the external clock source is used instead of a crystal oscillator, only the OSC-in pin is used for the clock. Notice that boot ROM makes use of the OSC-out level during reset to define the bypass mode.