 Hello everyone. This video is about ARM core dataflow model. Myself Rohini Merugu from Walchin Institute of Technology from ENTC department talking about the ARM core dataflow model. The learning outcomes. Learning outcomes of this video. At the end of this video you will be able to draw and the dataflow model of ARM core processor. You will be able to illustrate the functional importance of elements in dataflow model of ARM core processor. What is an ARM core processor? ARM core processor follows a risk architecture. Do you remember what is a risk architecture? Please recall the video of hardware architecture of embedded system in which I talked about the two architecture models risk and sysc. So sysc is the complex instruction set computer architecture and risk is the reduced instruction set architecture. So ARM core processor uses reduced instruction set architecture. It uses a load store architecture. Load store means a load instruction copies data from memory to registers data from memory to registers and what does the store instruction does? Store instruction copy data from registers to memory. So this is the load store architecture. No data processing is directly possible in a memory. Hence for data processing compulsorily these need to be carried out in registers. The elements of ARM core processor. What are the different elements? Instruction decoder. For decoding the instructions there need to be the instruction decoder. A register file as I said for computing purpose for manipulation purposes. We need a register file or the source need to be a register file. Then sign extend is an hardware. We will talk about the sign extend. A barrel shifter. Then MAC. MAC is a multiply accumulate unit. ALU arithmetic logic unit. Address register and an increment. So these are the different elements of ARM core processor. The same elements we will see in the diagram. This is the diagram of ARM core data flow model. As I already talked the sign extend hardware, instruction decoder, register file, barrel shifter, MAC, ALU, address register and incrementer. Everywhere there are the flow lines that you can see. These are the buses which are carrying data and instructions. The different processor architectures are available. What are the different processor architectures that you can recall? You recall the video about the hardware architecture of an embedded system in that I talked about the different processor architectures. The basic processor architectures are already I talked that is risk and SISC architecture. But beyond that based on the number of data possess used based on the data and address possess used the different architectures are there. Can you recall and write the answer to the question. What are the different processor architectures? You can pause the video for some time and can write the answer to this question. Thank you. I hope you have written the answer. Processor architectures based on number of program and databases used there are three types of processor architectures. The types are one Newman architecture, hardwood architecture and super hardwood architecture. So here the one Newman architecture is shown in the previous diagram of ARM core data flow model. Why I can see it is a one Newman architecture because the same bus is used for accessing the data and instructions. Whereas we have seen in hardware architecture of an embedded system video that hardwood architecture and super hardwood architecture uses the separate buses for accessing data and instructions. Whereas one Newman architecture uses the same bus for accessing data and instructions. Now let us look at the elements of this ARM core data flow model. Now here we can see the data can be accessed or instructions can be accessed and from here this block is nothing but the instruction decoder. As the name is instruction decoder, it is decoding the instructions. Means what? They are translating the instructions before they are executed. That job is done by instruction decoder. Next this big block that you can see is nothing but a resistor file. There is a storage bank of 32 bit resistors. There is a storage bank of 32 bit resistors and data processing is carried out in resistors. At the start only as I said the data processing cannot be directly carried out in memory. Any instruction is not available in which the directly data processing can be carried out in the memory but for data processing data need to be compulsorily in the resistor file and that can be done in the resistor file. So, the resistor bank is provided total 16 resistors from R0 to R15. The different modes are there based on that different resistors are active. In user mode the 16 resistors are active that is R0 to R15. So, these resistors are accessible and can be used for data processing. The different modes such as privilege, non-privilege modes and the details of that and details of the resistor banks will be coming in upcoming videos and this video is only focusing on data flow model. So, I will not be talking much about the resistor file at this stage but a detailed video of the resistor file will be coming up next. There is a hardware which is sign extend what it does sign extend means what. So, actually as I said the resistors are holding a 32 bit values signed or unsigned numbers signed or unsigned values. So, what sign extend is doing is actually the data which is accessed from memory it can be from of 8 bit or can be of 16 bit numbers but my resistor capability of 32 32 bits. So, the conversion is needed from this 8 bit and 16 or 16 bit to 32 bit and that conversion can be done by using sign extend resistor and the conversion can be done by using sign extend hardware. MAC MAC m stands for multiply ac stands for accumulate multiply accumulate unit. What it does this multiply accumulate unit as you can see it takes the values from two resistors Rn and Rm. You can see these lines takes the values from Rn and Rm using the buses A and B computes the result. This result is available on this bus and the data processing instruction will write this result into the destination resistor Rd and this result is back onto the resistor file. Rd stands for destination resistor. So, multiply accumulate as the name is there it is doing the data processing and it computes the results and the result is accumulated into the resistor. The one of the important unit that is ALU. A stands for arithmetic L is the logic U is the unit arithmetic and logic unit. This arithmetic and logic unit it does very important job in the load store instruction uses the ALU to generate the address to be held in the address resistor. As you can see here there is a address resistor this is holding one of the address and this address will be generated by ALU. So, load store instruction use ALU to generate address to be held in address resistor. The address is broadcast onto the address bus. Resistor Rm can be pre-processed in barrel shifter. This resistor Rm can be pre-processed in barrel shifter and this barrel shifter and ALU together will calculate a wide range of addresses and wide range of expressions and addresses. Next block comes is the incrementer. As the name is there increment see every time we are not accessing the same address right we are we need to access the different addresses and for that the updation of address is needed and update the address resistor before it read or write the next resistor value from or to the next sequential location and that job is done by incrementer. So, these are the different elements of data flow model of ARM core. These are the references used. Thank you.