 In this video we're going to explain the structure of what is known as the execution cycle in the AVR architecture. In other words, the steps that occur when an instruction is executed. The execution cycle is divided into two big blocks. The first one is known as the instruction fetch, or for us will abbreviate it as IF. The instruction fetch is the stage at which the following occurs. Let's assume we have here the 8-bit bus, data bus, and we have connected here the program memory. Remember that this program memory addresses 16 bits in each cell, and it has up to 32 k bytes. This program memory, which by the way is a flash memory, this program memory is accessed using as address the value of the register called the program counter. Now a read operation is scheduled here, so this memory is read, but also at the same time the value of the program counter as soon as this read operation is finished is updated. And the result of this read operation, the data is captured immediately in the instruction register and fed into what we call the decoding instruction block, which in itself is in charge of generating numerous signals, which we call the control signals, to instruct the rest of the data path on how to execute this instruction. This is the first stage, instruction fetch, and the second stage we're going to call it the execution itself, part of the execution cycle, which is itself divided into three sub-stages. The first one we're going to call it register, operand fetch, which we're going to abbreviate as ROF. The second one that occurs is the ALU execution, we're going to abbreviate that simply as ALU. And the third one is result writeback, which we call RW. So what occurs in this second stage of the execution, the first sub-stage register operation fetch is basically that the register file, remember, we have a register file here with 32 registers of 8 bits each. Now, this register file is accessed in two operands, or sometimes only one, come out of this block and are going to be used by the following block. Now, the operands might come from the register file, or both of them, or one of them from the register file, the other is taken from the instruction register. And this is for the case, for those instructions in which one of the operands is part of the instruction itself. What we have here is a multiplexer that allows us to select the operand to either come from the register file or the instruction register. So what we're going to do here is a read operation on this stage on the register file. This would be on this sub-stage here. Next sub-stage part of the execution phase is the ALU execution. So the ALU is receiving these two operands from the register file or the register file and instruction register, and it's producing a result. Now, remember, all these blocks, all of them are connected to the 8-bit data bus. So during this second sub-stage of the execution stage of the cycle, what happens is the ALU performs the operation that is required for the instruction. And finally, in the third sub-stage result writeback, what happens is that the result produced by the ALU is written in the bus and at the same time is read by the register file and from the bus and written as the result in another register. Now, some of the instructions used to register files, some of the instructions access the data memory. Now, this data memory is also connected to the bus and it may receive the addresses from two sources, either the register file or also the other option is coming directly from the instruction. So remember, this is the address of the operation. So for an instruction that reads or writes from memory, the three stages are the same with the exception that instead of having the ALU performing an operation, what we have is the memory reading the data or writing the data and then the result, in case it is a read operation, then we'll go back to the bus and back on our register and if it is a write operation, then the data would be coming out of the register file and the address entering the data memory and a write operation is performed. Now, the way these stages are executed is obviously in a sequential fashion. In other words, here we would have the instruction fetch, which typically is longer and then typical execution would need these three phases, ROF, the first one here, ALU and RWB. And the main purpose of this circuit is to execute these phases continuously and as fast as possible. So if we take this sequence in time, the microprocessor will execute one of these instructions following this execution cycle and at the end of it, we'll start with the instruction. If this instruction number I would be instruction I plus one. Now, most of the improvements on a microprocessor in terms of performance, in other words, to achieve the execution of instructions faster are derived from optimizations on this execution cycle and one of the most common techniques is called pipelining. We're going to illustrate pipelining with this architecture by dividing the execution cycle into these two blocks, the instruction fetch and the other three phases and then executing in parallel when we are executing the instruction fetch of one instruction. We then have the three phases, which we call ROF, ALU and RWB. But now the architecture is typically designed such that while the second part of the execution cycle is being executed for instruction I, in parallel, we are going to be executing the instruction fetch of instruction I plus one. In other words, we take these two blocks. Okay, this would be part A, this would be part B. We take these two blocks and we give the processor the possibility of executing them in parallel. So the result is the one that is shown here, which is that at any point in time, we are executing the three substages of the stage B of the execution cycle of instruction I in parallel with the instruction fetch first stage of the execution cycle of instruction I plus one. With this, we obtain a much faster speed in other words, the microcontroller is capable of executing the instruction faster and that typically translates into a higher performance of the overall system.